1#ifndef B43_XMIT_H_ 2#define B43_XMIT_H_ 3 4#include "main.h" 5#include <net/mac80211.h> 6 7 8#define _b43_declare_plcp_hdr(size) \ 9 struct b43_plcp_hdr##size { \ 10 union { \ 11 __le32 data; \ 12 __u8 raw[size]; \ 13 } __packed; \ 14 } __packed 15 16/* struct b43_plcp_hdr4 */ 17_b43_declare_plcp_hdr(4); 18/* struct b43_plcp_hdr6 */ 19_b43_declare_plcp_hdr(6); 20 21#undef _b43_declare_plcp_hdr 22 23/* TX header for v4 firmware */ 24struct b43_txhdr { 25 __le32 mac_ctl; /* MAC TX control */ 26 __le16 mac_frame_ctl; /* Copy of the FrameControl field */ 27 __le16 tx_fes_time_norm; /* TX FES Time Normal */ 28 __le16 phy_ctl; /* PHY TX control */ 29 __le16 phy_ctl1; /* PHY TX control word 1 */ 30 __le16 phy_ctl1_fb; /* PHY TX control word 1 for fallback rates */ 31 __le16 phy_ctl1_rts; /* PHY TX control word 1 RTS */ 32 __le16 phy_ctl1_rts_fb; /* PHY TX control word 1 RTS for fallback rates */ 33 __u8 phy_rate; /* PHY rate */ 34 __u8 phy_rate_rts; /* PHY rate for RTS/CTS */ 35 __u8 extra_ft; /* Extra Frame Types */ 36 __u8 chan_radio_code; /* Channel Radio Code */ 37 __u8 iv[16]; /* Encryption IV */ 38 __u8 tx_receiver[6]; /* TX Frame Receiver address */ 39 __le16 tx_fes_time_fb; /* TX FES Time Fallback */ 40 struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP header */ 41 __le16 rts_dur_fb; /* RTS fallback duration */ 42 struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP header */ 43 __le16 dur_fb; /* Fallback duration */ 44 __le16 mimo_modelen; /* MIMO mode length */ 45 __le16 mimo_ratelen_fb; /* MIMO fallback rate length */ 46 __le32 timeout; /* Timeout */ 47 48 union { 49 /* The new r410 format. */ 50 struct { 51 __le16 mimo_antenna; /* MIMO antenna select */ 52 __le16 preload_size; /* Preload size */ 53 PAD_BYTES(2); 54 __le16 cookie; /* TX frame cookie */ 55 __le16 tx_status; /* TX status */ 56 struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */ 57 __u8 rts_frame[16]; /* The RTS frame (if used) */ 58 PAD_BYTES(2); 59 struct b43_plcp_hdr6 plcp; /* Main PLCP header */ 60 } new_format __packed; 61 62 /* The old r351 format. */ 63 struct { 64 PAD_BYTES(2); 65 __le16 cookie; /* TX frame cookie */ 66 __le16 tx_status; /* TX status */ 67 struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */ 68 __u8 rts_frame[16]; /* The RTS frame (if used) */ 69 PAD_BYTES(2); 70 struct b43_plcp_hdr6 plcp; /* Main PLCP header */ 71 } old_format __packed; 72 73 } __packed; 74} __packed; 75 76/* MAC TX control */ 77#define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */ 78#define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */ 79#define B43_TXH_MAC_KEYIDX_SHIFT 20 80#define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */ 81#define B43_TXH_MAC_KEYALG_SHIFT 16 82#define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */ 83#define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */ 84#define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */ 85#define B43_TXH_MAC_FRAMEBURST 0x00001000 /* Frameburst */ 86#define B43_TXH_MAC_SENDCTS 0x00000800 /* Send CTS-to-self */ 87#define B43_TXH_MAC_AMPDU 0x00000600 /* AMPDU status */ 88#define B43_TXH_MAC_AMPDU_MPDU 0x00000000 /* Regular MPDU, not an AMPDU */ 89#define B43_TXH_MAC_AMPDU_FIRST 0x00000200 /* First MPDU or AMPDU */ 90#define B43_TXH_MAC_AMPDU_INTER 0x00000400 /* Intermediate MPDU or AMPDU */ 91#define B43_TXH_MAC_AMPDU_LAST 0x00000600 /* Last (or only) MPDU of AMPDU */ 92#define B43_TXH_MAC_40MHZ 0x00000100 /* Use 40 MHz bandwidth */ 93#define B43_TXH_MAC_5GHZ 0x00000080 /* 5GHz band */ 94#define B43_TXH_MAC_DFCS 0x00000040 /* DFCS */ 95#define B43_TXH_MAC_IGNPMQ 0x00000020 /* Ignore PMQ */ 96#define B43_TXH_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */ 97#define B43_TXH_MAC_STMSDU 0x00000008 /* Start MSDU */ 98#define B43_TXH_MAC_SENDRTS 0x00000004 /* Send RTS */ 99#define B43_TXH_MAC_LONGFRAME 0x00000002 /* Long frame */ 100#define B43_TXH_MAC_ACK 0x00000001 /* Immediate ACK */ 101 102/* Extra Frame Types */ 103#define B43_TXH_EFT_FB 0x03 /* Data frame fallback encoding */ 104#define B43_TXH_EFT_FB_CCK 0x00 /* CCK */ 105#define B43_TXH_EFT_FB_OFDM 0x01 /* OFDM */ 106#define B43_TXH_EFT_FB_EWC 0x02 /* EWC */ 107#define B43_TXH_EFT_FB_N 0x03 /* N */ 108#define B43_TXH_EFT_RTS 0x0C /* RTS/CTS encoding */ 109#define B43_TXH_EFT_RTS_CCK 0x00 /* CCK */ 110#define B43_TXH_EFT_RTS_OFDM 0x04 /* OFDM */ 111#define B43_TXH_EFT_RTS_EWC 0x08 /* EWC */ 112#define B43_TXH_EFT_RTS_N 0x0C /* N */ 113#define B43_TXH_EFT_RTSFB 0x30 /* RTS/CTS fallback encoding */ 114#define B43_TXH_EFT_RTSFB_CCK 0x00 /* CCK */ 115#define B43_TXH_EFT_RTSFB_OFDM 0x10 /* OFDM */ 116#define B43_TXH_EFT_RTSFB_EWC 0x20 /* EWC */ 117#define B43_TXH_EFT_RTSFB_N 0x30 /* N */ 118 119/* PHY TX control word */ 120#define B43_TXH_PHY_ENC 0x0003 /* Data frame encoding */ 121#define B43_TXH_PHY_ENC_CCK 0x0000 /* CCK */ 122#define B43_TXH_PHY_ENC_OFDM 0x0001 /* OFDM */ 123#define B43_TXH_PHY_ENC_EWC 0x0002 /* EWC */ 124#define B43_TXH_PHY_ENC_N 0x0003 /* N */ 125#define B43_TXH_PHY_SHORTPRMBL 0x0010 /* Use short preamble */ 126#define B43_TXH_PHY_ANT 0x03C0 /* Antenna selection */ 127#define B43_TXH_PHY_ANT0 0x0000 /* Use antenna 0 */ 128#define B43_TXH_PHY_ANT1 0x0040 /* Use antenna 1 */ 129#define B43_TXH_PHY_ANT01AUTO 0x00C0 /* Use antenna 0/1 auto */ 130#define B43_TXH_PHY_ANT2 0x0100 /* Use antenna 2 */ 131#define B43_TXH_PHY_ANT3 0x0200 /* Use antenna 3 */ 132#define B43_TXH_PHY_TXPWR 0xFC00 /* TX power */ 133#define B43_TXH_PHY_TXPWR_SHIFT 10 134 135/* PHY TX control word 1 */ 136#define B43_TXH_PHY1_BW 0x0007 /* Bandwidth */ 137#define B43_TXH_PHY1_BW_10 0x0000 /* 10 MHz */ 138#define B43_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */ 139#define B43_TXH_PHY1_BW_20 0x0002 /* 20 MHz */ 140#define B43_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */ 141#define B43_TXH_PHY1_BW_40 0x0004 /* 40 MHz */ 142#define B43_TXH_PHY1_BW_40DUP 0x0005 /* 50 MHz duplicate */ 143#define B43_TXH_PHY1_MODE 0x0038 /* Mode */ 144#define B43_TXH_PHY1_MODE_SISO 0x0000 /* SISO */ 145#define B43_TXH_PHY1_MODE_CDD 0x0008 /* CDD */ 146#define B43_TXH_PHY1_MODE_STBC 0x0010 /* STBC */ 147#define B43_TXH_PHY1_MODE_SDM 0x0018 /* SDM */ 148#define B43_TXH_PHY1_CRATE 0x0700 /* Coding rate */ 149#define B43_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */ 150#define B43_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */ 151#define B43_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */ 152#define B43_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */ 153#define B43_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */ 154#define B43_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */ 155#define B43_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */ 156#define B43_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */ 157#define B43_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */ 158#define B43_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */ 159#define B43_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */ 160#define B43_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */ 161 162 163/* r351 firmware compatibility stuff. */ 164static inline 165bool b43_is_old_txhdr_format(struct b43_wldev *dev) 166{ 167 return (dev->fw.rev <= 351); 168} 169 170static inline 171size_t b43_txhdr_size(struct b43_wldev *dev) 172{ 173 if (b43_is_old_txhdr_format(dev)) 174 return 100 + sizeof(struct b43_plcp_hdr6); 175 return 104 + sizeof(struct b43_plcp_hdr6); 176} 177 178 179int b43_generate_txhdr(struct b43_wldev *dev, 180 u8 * txhdr, 181 struct sk_buff *skb_frag, 182 struct ieee80211_tx_info *txctl, u16 cookie); 183 184/* Transmit Status */ 185struct b43_txstatus { 186 u16 cookie; /* The cookie from the txhdr */ 187 u16 seq; /* Sequence number */ 188 u8 phy_stat; /* PHY TX status */ 189 u8 frame_count; /* Frame transmit count */ 190 u8 rts_count; /* RTS transmit count */ 191 u8 supp_reason; /* Suppression reason */ 192 /* flags */ 193 u8 pm_indicated; /* PM mode indicated to AP */ 194 u8 intermediate; /* Intermediate status notification (not final) */ 195 u8 for_ampdu; /* Status is for an AMPDU (afterburner) */ 196 u8 acked; /* Wireless ACK received */ 197}; 198 199/* txstatus supp_reason values */ 200enum { 201 B43_TXST_SUPP_NONE, /* Not suppressed */ 202 B43_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */ 203 B43_TXST_SUPP_FLUSH, /* Suppressed due to flush request */ 204 B43_TXST_SUPP_PREV, /* Previous fragment failed */ 205 B43_TXST_SUPP_CHAN, /* Channel mismatch */ 206 B43_TXST_SUPP_LIFE, /* Lifetime expired */ 207 B43_TXST_SUPP_UNDER, /* Buffer underflow */ 208 B43_TXST_SUPP_ABNACK, /* Afterburner NACK */ 209}; 210 211/* Receive header for v4 firmware. */ 212struct b43_rxhdr_fw4 { 213 __le16 frame_len; /* Frame length */ 214 PAD_BYTES(2); 215 __le16 phy_status0; /* PHY RX Status 0 */ 216 union { 217 /* RSSI for A/B/G-PHYs */ 218 struct { 219 __u8 jssi; /* PHY RX Status 1: JSSI */ 220 __u8 sig_qual; /* PHY RX Status 1: Signal Quality */ 221 } __packed; 222 223 /* RSSI for N-PHYs */ 224 struct { 225 __s8 power0; /* PHY RX Status 1: Power 0 */ 226 __s8 power1; /* PHY RX Status 1: Power 1 */ 227 } __packed; 228 } __packed; 229 __le16 phy_status2; /* PHY RX Status 2 */ 230 __le16 phy_status3; /* PHY RX Status 3 */ 231 __le32 mac_status; /* MAC RX status */ 232 __le16 mac_time; 233 __le16 channel; 234} __packed; 235 236/* PHY RX Status 0 */ 237#define B43_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */ 238#define B43_RX_PHYST0_PLCPHCF 0x0200 239#define B43_RX_PHYST0_PLCPFV 0x0100 240#define B43_RX_PHYST0_SHORTPRMBL 0x0080 /* Received with Short Preamble */ 241#define B43_RX_PHYST0_LCRS 0x0040 242#define B43_RX_PHYST0_ANT 0x0020 /* Antenna */ 243#define B43_RX_PHYST0_UNSRATE 0x0010 244#define B43_RX_PHYST0_CLIP 0x000C 245#define B43_RX_PHYST0_CLIP_SHIFT 2 246#define B43_RX_PHYST0_FTYPE 0x0003 /* Frame type */ 247#define B43_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */ 248#define B43_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */ 249#define B43_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */ 250#define B43_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */ 251 252/* PHY RX Status 2 */ 253#define B43_RX_PHYST2_LNAG 0xC000 /* LNA Gain */ 254#define B43_RX_PHYST2_LNAG_SHIFT 14 255#define B43_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */ 256#define B43_RX_PHYST2_PNAG_SHIFT 10 257#define B43_RX_PHYST2_FOFF 0x03FF /* F offset */ 258 259/* PHY RX Status 3 */ 260#define B43_RX_PHYST3_DIGG 0x1800 /* DIG Gain */ 261#define B43_RX_PHYST3_DIGG_SHIFT 11 262#define B43_RX_PHYST3_TRSTATE 0x0400 /* TR state */ 263 264/* MAC RX Status */ 265#define B43_RX_MAC_RXST_VALID 0x01000000 /* PHY RXST valid */ 266#define B43_RX_MAC_TKIP_MICERR 0x00100000 /* TKIP MIC error */ 267#define B43_RX_MAC_TKIP_MICATT 0x00080000 /* TKIP MIC attempted */ 268#define B43_RX_MAC_AGGTYPE 0x00060000 /* Aggregation type */ 269#define B43_RX_MAC_AGGTYPE_SHIFT 17 270#define B43_RX_MAC_AMSDU 0x00010000 /* A-MSDU mask */ 271#define B43_RX_MAC_BEACONSENT 0x00008000 /* Beacon sent flag */ 272#define B43_RX_MAC_KEYIDX 0x000007E0 /* Key index */ 273#define B43_RX_MAC_KEYIDX_SHIFT 5 274#define B43_RX_MAC_DECERR 0x00000010 /* Decrypt error */ 275#define B43_RX_MAC_DEC 0x00000008 /* Decryption attempted */ 276#define B43_RX_MAC_PADDING 0x00000004 /* Pad bytes present */ 277#define B43_RX_MAC_RESP 0x00000002 /* Response frame transmitted */ 278#define B43_RX_MAC_FCSERR 0x00000001 /* FCS error */ 279 280/* RX channel */ 281#define B43_RX_CHAN_40MHZ 0x1000 /* 40 Mhz channel width */ 282#define B43_RX_CHAN_5GHZ 0x0800 /* 5 Ghz band */ 283#define B43_RX_CHAN_ID 0x07F8 /* Channel ID */ 284#define B43_RX_CHAN_ID_SHIFT 3 285#define B43_RX_CHAN_PHYTYPE 0x0007 /* PHY type */ 286 287 288u8 b43_plcp_get_ratecode_cck(const u8 bitrate); 289u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate); 290 291void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp, 292 const u16 octets, const u8 bitrate); 293 294void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr); 295 296void b43_handle_txstatus(struct b43_wldev *dev, 297 const struct b43_txstatus *status); 298bool b43_fill_txstatus_report(struct b43_wldev *dev, 299 struct ieee80211_tx_info *report, 300 const struct b43_txstatus *status); 301 302void b43_tx_suspend(struct b43_wldev *dev); 303void b43_tx_resume(struct b43_wldev *dev); 304 305 306/* Helper functions for converting the key-table index from "firmware-format" 307 * to "raw-format" and back. The firmware API changed for this at some revision. 308 * We need to account for that here. */ 309static inline int b43_new_kidx_api(struct b43_wldev *dev) 310{ 311 return (dev->fw.rev >= 351); 312} 313static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx) 314{ 315 u8 firmware_kidx; 316 if (b43_new_kidx_api(dev)) { 317 firmware_kidx = raw_kidx; 318 } else { 319 if (raw_kidx >= 4) /* Is per STA key? */ 320 firmware_kidx = raw_kidx - 4; 321 else 322 firmware_kidx = raw_kidx; /* TX default key */ 323 } 324 return firmware_kidx; 325} 326static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx) 327{ 328 u8 raw_kidx; 329 if (b43_new_kidx_api(dev)) 330 raw_kidx = firmware_kidx; 331 else 332 raw_kidx = firmware_kidx + 4; /* RX default keys or per STA keys */ 333 return raw_kidx; 334} 335 336/* struct b43_private_tx_info - TX info private to b43. 337 * The structure is placed in (struct ieee80211_tx_info *)->rate_driver_data 338 * 339 * @bouncebuffer: DMA Bouncebuffer (if used) 340 */ 341struct b43_private_tx_info { 342 void *bouncebuffer; 343}; 344 345static inline struct b43_private_tx_info * 346b43_get_priv_tx_info(struct ieee80211_tx_info *info) 347{ 348 BUILD_BUG_ON(sizeof(struct b43_private_tx_info) > 349 sizeof(info->rate_driver_data)); 350 return (struct b43_private_tx_info *)info->rate_driver_data; 351} 352 353#endif /* B43_XMIT_H_ */ 354