1#define USE_PCI_CLOCK 2static char rcsid[] = 3"Revision: 3.4.5 Date: 2002/03/07 "; 4 5 6#include <linux/module.h> 7#include <linux/kernel.h> 8#include <linux/mm.h> 9#include <linux/ioport.h> 10#include <linux/pci.h> 11#include <linux/errno.h> 12#include <linux/string.h> 13#include <linux/init.h> 14#include <linux/delay.h> 15#include <linux/net.h> 16#include <linux/skbuff.h> 17#include <linux/if_arp.h> 18#include <linux/netdevice.h> 19#include <linux/etherdevice.h> 20#include <linux/spinlock.h> 21#include <linux/if.h> 22#include <linux/slab.h> 23#include <net/arp.h> 24 25#include <asm/io.h> 26#include <asm/uaccess.h> 27 28#include "pc300.h" 29 30#define CPC_LOCK(card,flags) \ 31 do { \ 32 spin_lock_irqsave(&card->card_lock, flags); \ 33 } while (0) 34 35#define CPC_UNLOCK(card,flags) \ 36 do { \ 37 spin_unlock_irqrestore(&card->card_lock, flags); \ 38 } while (0) 39 40#undef PC300_DEBUG_PCI 41#undef PC300_DEBUG_INTR 42#undef PC300_DEBUG_TX 43#undef PC300_DEBUG_RX 44#undef PC300_DEBUG_OTHER 45 46static DEFINE_PCI_DEVICE_TABLE(cpc_pci_dev_id) = { 47 /* PC300/RSV or PC300/X21, 2 chan */ 48 {0x120e, 0x300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x300}, 49 /* PC300/RSV or PC300/X21, 1 chan */ 50 {0x120e, 0x301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x301}, 51 /* PC300/TE, 2 chan */ 52 {0x120e, 0x310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x310}, 53 /* PC300/TE, 1 chan */ 54 {0x120e, 0x311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x311}, 55 /* PC300/TE-M, 2 chan */ 56 {0x120e, 0x320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x320}, 57 /* PC300/TE-M, 1 chan */ 58 {0x120e, 0x321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x321}, 59 /* End of table */ 60 {0,}, 61}; 62MODULE_DEVICE_TABLE(pci, cpc_pci_dev_id); 63 64#ifndef cpc_min 65#define cpc_min(a,b) (((a)<(b))?(a):(b)) 66#endif 67#ifndef cpc_max 68#define cpc_max(a,b) (((a)>(b))?(a):(b)) 69#endif 70 71/* prototypes */ 72static void tx_dma_buf_pt_init(pc300_t *, int); 73static void tx_dma_buf_init(pc300_t *, int); 74static void rx_dma_buf_pt_init(pc300_t *, int); 75static void rx_dma_buf_init(pc300_t *, int); 76static void tx_dma_buf_check(pc300_t *, int); 77static void rx_dma_buf_check(pc300_t *, int); 78static irqreturn_t cpc_intr(int, void *); 79static int clock_rate_calc(u32, u32, int *); 80static u32 detect_ram(pc300_t *); 81static void plx_init(pc300_t *); 82static void cpc_trace(struct net_device *, struct sk_buff *, char); 83static int cpc_attach(struct net_device *, unsigned short, unsigned short); 84static int cpc_close(struct net_device *dev); 85 86#ifdef CONFIG_PC300_MLPPP 87void cpc_tty_init(pc300dev_t * dev); 88void cpc_tty_unregister_service(pc300dev_t * pc300dev); 89void cpc_tty_receive(pc300dev_t * pc300dev); 90void cpc_tty_trigger_poll(pc300dev_t * pc300dev); 91void cpc_tty_reset_var(void); 92#endif 93 94/************************/ 95/*** DMA Routines ***/ 96/************************/ 97static void tx_dma_buf_pt_init(pc300_t * card, int ch) 98{ 99 int i; 100 int ch_factor = ch * N_DMA_TX_BUF; 101 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase 102 + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t)); 103 104 for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) { 105 cpc_writel(&ptdescr->next, (u32)(DMA_TX_BD_BASE + 106 (ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t))); 107 cpc_writel(&ptdescr->ptbuf, 108 (u32)(DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN)); 109 } 110} 111 112static void tx_dma_buf_init(pc300_t * card, int ch) 113{ 114 int i; 115 int ch_factor = ch * N_DMA_TX_BUF; 116 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase 117 + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t)); 118 119 for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) { 120 memset_io(ptdescr, 0, sizeof(pcsca_bd_t)); 121 cpc_writew(&ptdescr->len, 0); 122 cpc_writeb(&ptdescr->status, DST_OSB); 123 } 124 tx_dma_buf_pt_init(card, ch); 125} 126 127static void rx_dma_buf_pt_init(pc300_t * card, int ch) 128{ 129 int i; 130 int ch_factor = ch * N_DMA_RX_BUF; 131 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase 132 + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t)); 133 134 for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) { 135 cpc_writel(&ptdescr->next, (u32)(DMA_RX_BD_BASE + 136 (ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t))); 137 cpc_writel(&ptdescr->ptbuf, 138 (u32)(DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN)); 139 } 140} 141 142static void rx_dma_buf_init(pc300_t * card, int ch) 143{ 144 int i; 145 int ch_factor = ch * N_DMA_RX_BUF; 146 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase 147 + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t)); 148 149 for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) { 150 memset_io(ptdescr, 0, sizeof(pcsca_bd_t)); 151 cpc_writew(&ptdescr->len, 0); 152 cpc_writeb(&ptdescr->status, 0); 153 } 154 rx_dma_buf_pt_init(card, ch); 155} 156 157static void tx_dma_buf_check(pc300_t * card, int ch) 158{ 159 volatile pcsca_bd_t __iomem *ptdescr; 160 int i; 161 u16 first_bd = card->chan[ch].tx_first_bd; 162 u16 next_bd = card->chan[ch].tx_next_bd; 163 164 printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch, 165 first_bd, TX_BD_ADDR(ch, first_bd), 166 next_bd, TX_BD_ADDR(ch, next_bd)); 167 for (i = first_bd, 168 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, first_bd)); 169 i != ((next_bd + 1) & (N_DMA_TX_BUF - 1)); 170 i = (i + 1) & (N_DMA_TX_BUF - 1), 171 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i))) { 172 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d", 173 ch, i, cpc_readl(&ptdescr->next), 174 cpc_readl(&ptdescr->ptbuf), 175 cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len)); 176 } 177 printk("\n"); 178} 179 180#ifdef PC300_DEBUG_OTHER 181/* Show all TX buffer descriptors */ 182static void tx1_dma_buf_check(pc300_t * card, int ch) 183{ 184 volatile pcsca_bd_t __iomem *ptdescr; 185 int i; 186 u16 first_bd = card->chan[ch].tx_first_bd; 187 u16 next_bd = card->chan[ch].tx_next_bd; 188 u32 scabase = card->hw.scabase; 189 190 printk ("\nnfree_tx_bd = %d\n", card->chan[ch].nfree_tx_bd); 191 printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch, 192 first_bd, TX_BD_ADDR(ch, first_bd), 193 next_bd, TX_BD_ADDR(ch, next_bd)); 194 printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n", 195 cpc_readl(scabase + DTX_REG(CDAL, ch)), 196 cpc_readl(scabase + DTX_REG(EDAL, ch))); 197 for (i = 0; i < N_DMA_TX_BUF; i++) { 198 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i)); 199 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d", 200 ch, i, cpc_readl(&ptdescr->next), 201 cpc_readl(&ptdescr->ptbuf), 202 cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len)); 203 } 204 printk("\n"); 205} 206#endif 207 208static void rx_dma_buf_check(pc300_t * card, int ch) 209{ 210 volatile pcsca_bd_t __iomem *ptdescr; 211 int i; 212 u16 first_bd = card->chan[ch].rx_first_bd; 213 u16 last_bd = card->chan[ch].rx_last_bd; 214 int ch_factor; 215 216 ch_factor = ch * N_DMA_RX_BUF; 217 printk("#CH%d: f_bd = %d, l_bd = %d\n", ch, first_bd, last_bd); 218 for (i = 0, ptdescr = (card->hw.rambase + 219 DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t)); 220 i < N_DMA_RX_BUF; i++, ptdescr++) { 221 if (cpc_readb(&ptdescr->status) & DST_OSB) 222 printk ("\n CH%d RX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d", 223 ch, i, cpc_readl(&ptdescr->next), 224 cpc_readl(&ptdescr->ptbuf), 225 cpc_readb(&ptdescr->status), 226 cpc_readw(&ptdescr->len)); 227 } 228 printk("\n"); 229} 230 231static int dma_get_rx_frame_size(pc300_t * card, int ch) 232{ 233 volatile pcsca_bd_t __iomem *ptdescr; 234 u16 first_bd = card->chan[ch].rx_first_bd; 235 int rcvd = 0; 236 volatile u8 status; 237 238 ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd)); 239 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) { 240 rcvd += cpc_readw(&ptdescr->len); 241 first_bd = (first_bd + 1) & (N_DMA_RX_BUF - 1); 242 if ((status & DST_EOM) || (first_bd == card->chan[ch].rx_last_bd)) { 243 /* Return the size of a good frame or incomplete bad frame 244 * (dma_buf_read will clean the buffer descriptors in this case). */ 245 return (rcvd); 246 } 247 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next)); 248 } 249 return (-1); 250} 251 252/* 253 * dma_buf_write: writes a frame to the Tx DMA buffers 254 * NOTE: this function writes one frame at a time. 255 */ 256static int dma_buf_write(pc300_t *card, int ch, u8 *ptdata, int len) 257{ 258 int i, nchar; 259 volatile pcsca_bd_t __iomem *ptdescr; 260 int tosend = len; 261 u8 nbuf = ((len - 1) / BD_DEF_LEN) + 1; 262 263 if (nbuf >= card->chan[ch].nfree_tx_bd) { 264 return -ENOMEM; 265 } 266 267 for (i = 0; i < nbuf; i++) { 268 ptdescr = (card->hw.rambase + 269 TX_BD_ADDR(ch, card->chan[ch].tx_next_bd)); 270 nchar = cpc_min(BD_DEF_LEN, tosend); 271 if (cpc_readb(&ptdescr->status) & DST_OSB) { 272 memcpy_toio((card->hw.rambase + cpc_readl(&ptdescr->ptbuf)), 273 &ptdata[len - tosend], nchar); 274 cpc_writew(&ptdescr->len, nchar); 275 card->chan[ch].nfree_tx_bd--; 276 if ((i + 1) == nbuf) { 277 /* This must be the last BD to be used */ 278 cpc_writeb(&ptdescr->status, DST_EOM); 279 } else { 280 cpc_writeb(&ptdescr->status, 0); 281 } 282 } else { 283 return -ENOMEM; 284 } 285 tosend -= nchar; 286 card->chan[ch].tx_next_bd = 287 (card->chan[ch].tx_next_bd + 1) & (N_DMA_TX_BUF - 1); 288 } 289 /* If it gets to here, it means we have sent the whole frame */ 290 return 0; 291} 292 293/* 294 * dma_buf_read: reads a frame from the Rx DMA buffers 295 * NOTE: this function reads one frame at a time. 296 */ 297static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb) 298{ 299 int nchar; 300 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 301 volatile pcsca_bd_t __iomem *ptdescr; 302 int rcvd = 0; 303 volatile u8 status; 304 305 ptdescr = (card->hw.rambase + 306 RX_BD_ADDR(ch, chan->rx_first_bd)); 307 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) { 308 nchar = cpc_readw(&ptdescr->len); 309 if ((status & (DST_OVR | DST_CRC | DST_RBIT | DST_SHRT | DST_ABT)) || 310 (nchar > BD_DEF_LEN)) { 311 312 if (nchar > BD_DEF_LEN) 313 status |= DST_RBIT; 314 rcvd = -status; 315 /* Discard remaining descriptors used by the bad frame */ 316 while (chan->rx_first_bd != chan->rx_last_bd) { 317 cpc_writeb(&ptdescr->status, 0); 318 chan->rx_first_bd = (chan->rx_first_bd+1) & (N_DMA_RX_BUF-1); 319 if (status & DST_EOM) 320 break; 321 ptdescr = (card->hw.rambase + 322 cpc_readl(&ptdescr->next)); 323 status = cpc_readb(&ptdescr->status); 324 } 325 break; 326 } 327 if (nchar != 0) { 328 if (skb) { 329 memcpy_fromio(skb_put(skb, nchar), 330 (card->hw.rambase+cpc_readl(&ptdescr->ptbuf)),nchar); 331 } 332 rcvd += nchar; 333 } 334 cpc_writeb(&ptdescr->status, 0); 335 cpc_writeb(&ptdescr->len, 0); 336 chan->rx_first_bd = (chan->rx_first_bd + 1) & (N_DMA_RX_BUF - 1); 337 338 if (status & DST_EOM) 339 break; 340 341 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next)); 342 } 343 344 if (rcvd != 0) { 345 /* Update pointer */ 346 chan->rx_last_bd = (chan->rx_first_bd - 1) & (N_DMA_RX_BUF - 1); 347 /* Update EDA */ 348 cpc_writel(card->hw.scabase + DRX_REG(EDAL, ch), 349 RX_BD_ADDR(ch, chan->rx_last_bd)); 350 } 351 return (rcvd); 352} 353 354static void tx_dma_stop(pc300_t * card, int ch) 355{ 356 void __iomem *scabase = card->hw.scabase; 357 u8 drr_ena_bit = 1 << (5 + 2 * ch); 358 u8 drr_rst_bit = 1 << (1 + 2 * ch); 359 360 /* Disable DMA */ 361 cpc_writeb(scabase + DRR, drr_ena_bit); 362 cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit); 363} 364 365static void rx_dma_stop(pc300_t * card, int ch) 366{ 367 void __iomem *scabase = card->hw.scabase; 368 u8 drr_ena_bit = 1 << (4 + 2 * ch); 369 u8 drr_rst_bit = 1 << (2 * ch); 370 371 /* Disable DMA */ 372 cpc_writeb(scabase + DRR, drr_ena_bit); 373 cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit); 374} 375 376static void rx_dma_start(pc300_t * card, int ch) 377{ 378 void __iomem *scabase = card->hw.scabase; 379 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 380 381 /* Start DMA */ 382 cpc_writel(scabase + DRX_REG(CDAL, ch), 383 RX_BD_ADDR(ch, chan->rx_first_bd)); 384 if (cpc_readl(scabase + DRX_REG(CDAL,ch)) != 385 RX_BD_ADDR(ch, chan->rx_first_bd)) { 386 cpc_writel(scabase + DRX_REG(CDAL, ch), 387 RX_BD_ADDR(ch, chan->rx_first_bd)); 388 } 389 cpc_writel(scabase + DRX_REG(EDAL, ch), 390 RX_BD_ADDR(ch, chan->rx_last_bd)); 391 cpc_writew(scabase + DRX_REG(BFLL, ch), BD_DEF_LEN); 392 cpc_writeb(scabase + DSR_RX(ch), DSR_DE); 393 if (!(cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) { 394 cpc_writeb(scabase + DSR_RX(ch), DSR_DE); 395 } 396} 397 398/*************************/ 399/*** FALC Routines ***/ 400/*************************/ 401static void falc_issue_cmd(pc300_t *card, int ch, u8 cmd) 402{ 403 void __iomem *falcbase = card->hw.falcbase; 404 unsigned long i = 0; 405 406 while (cpc_readb(falcbase + F_REG(SIS, ch)) & SIS_CEC) { 407 if (i++ >= PC300_FALC_MAXLOOP) { 408 printk("%s: FALC command locked(cmd=0x%x).\n", 409 card->chan[ch].d.name, cmd); 410 break; 411 } 412 } 413 cpc_writeb(falcbase + F_REG(CMDR, ch), cmd); 414} 415 416static void falc_intr_enable(pc300_t * card, int ch) 417{ 418 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 419 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 420 falc_t *pfalc = (falc_t *) & chan->falc; 421 void __iomem *falcbase = card->hw.falcbase; 422 423 /* Interrupt pins are open-drain */ 424 cpc_writeb(falcbase + F_REG(IPC, ch), 425 cpc_readb(falcbase + F_REG(IPC, ch)) & ~IPC_IC0); 426 /* Conters updated each second */ 427 cpc_writeb(falcbase + F_REG(FMR1, ch), 428 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_ECM); 429 /* Enable SEC and ES interrupts */ 430 cpc_writeb(falcbase + F_REG(IMR3, ch), 431 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~(IMR3_SEC | IMR3_ES)); 432 if (conf->fr_mode == PC300_FR_UNFRAMED) { 433 cpc_writeb(falcbase + F_REG(IMR4, ch), 434 cpc_readb(falcbase + F_REG(IMR4, ch)) & ~(IMR4_LOS)); 435 } else { 436 cpc_writeb(falcbase + F_REG(IMR4, ch), 437 cpc_readb(falcbase + F_REG(IMR4, ch)) & 438 ~(IMR4_LFA | IMR4_AIS | IMR4_LOS | IMR4_SLIP)); 439 } 440 if (conf->media == IF_IFACE_T1) { 441 cpc_writeb(falcbase + F_REG(IMR3, ch), 442 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC); 443 } else { 444 cpc_writeb(falcbase + F_REG(IPC, ch), 445 cpc_readb(falcbase + F_REG(IPC, ch)) | IPC_SCI); 446 if (conf->fr_mode == PC300_FR_UNFRAMED) { 447 cpc_writeb(falcbase + F_REG(IMR2, ch), 448 cpc_readb(falcbase + F_REG(IMR2, ch)) & ~(IMR2_LOS)); 449 } else { 450 cpc_writeb(falcbase + F_REG(IMR2, ch), 451 cpc_readb(falcbase + F_REG(IMR2, ch)) & 452 ~(IMR2_FAR | IMR2_LFA | IMR2_AIS | IMR2_LOS)); 453 if (pfalc->multiframe_mode) { 454 cpc_writeb(falcbase + F_REG(IMR2, ch), 455 cpc_readb(falcbase + F_REG(IMR2, ch)) & 456 ~(IMR2_T400MS | IMR2_MFAR)); 457 } else { 458 cpc_writeb(falcbase + F_REG(IMR2, ch), 459 cpc_readb(falcbase + F_REG(IMR2, ch)) | 460 IMR2_T400MS | IMR2_MFAR); 461 } 462 } 463 } 464} 465 466static void falc_open_timeslot(pc300_t * card, int ch, int timeslot) 467{ 468 void __iomem *falcbase = card->hw.falcbase; 469 u8 tshf = card->chan[ch].falc.offset; 470 471 cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch), 472 cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) & 473 ~(0x80 >> ((timeslot - tshf) & 0x07))); 474 cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch), 475 cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) | 476 (0x80 >> (timeslot & 0x07))); 477 cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch), 478 cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) | 479 (0x80 >> (timeslot & 0x07))); 480} 481 482static void falc_close_timeslot(pc300_t * card, int ch, int timeslot) 483{ 484 void __iomem *falcbase = card->hw.falcbase; 485 u8 tshf = card->chan[ch].falc.offset; 486 487 cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch), 488 cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) | 489 (0x80 >> ((timeslot - tshf) & 0x07))); 490 cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch), 491 cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) & 492 ~(0x80 >> (timeslot & 0x07))); 493 cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch), 494 cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) & 495 ~(0x80 >> (timeslot & 0x07))); 496} 497 498static void falc_close_all_timeslots(pc300_t * card, int ch) 499{ 500 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 501 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 502 void __iomem *falcbase = card->hw.falcbase; 503 504 cpc_writeb(falcbase + F_REG(ICB1, ch), 0xff); 505 cpc_writeb(falcbase + F_REG(TTR1, ch), 0); 506 cpc_writeb(falcbase + F_REG(RTR1, ch), 0); 507 cpc_writeb(falcbase + F_REG(ICB2, ch), 0xff); 508 cpc_writeb(falcbase + F_REG(TTR2, ch), 0); 509 cpc_writeb(falcbase + F_REG(RTR2, ch), 0); 510 cpc_writeb(falcbase + F_REG(ICB3, ch), 0xff); 511 cpc_writeb(falcbase + F_REG(TTR3, ch), 0); 512 cpc_writeb(falcbase + F_REG(RTR3, ch), 0); 513 if (conf->media == IF_IFACE_E1) { 514 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff); 515 cpc_writeb(falcbase + F_REG(TTR4, ch), 0); 516 cpc_writeb(falcbase + F_REG(RTR4, ch), 0); 517 } 518} 519 520static void falc_open_all_timeslots(pc300_t * card, int ch) 521{ 522 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 523 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 524 void __iomem *falcbase = card->hw.falcbase; 525 526 cpc_writeb(falcbase + F_REG(ICB1, ch), 0); 527 if (conf->fr_mode == PC300_FR_UNFRAMED) { 528 cpc_writeb(falcbase + F_REG(TTR1, ch), 0xff); 529 cpc_writeb(falcbase + F_REG(RTR1, ch), 0xff); 530 } else { 531 /* Timeslot 0 is never enabled */ 532 cpc_writeb(falcbase + F_REG(TTR1, ch), 0x7f); 533 cpc_writeb(falcbase + F_REG(RTR1, ch), 0x7f); 534 } 535 cpc_writeb(falcbase + F_REG(ICB2, ch), 0); 536 cpc_writeb(falcbase + F_REG(TTR2, ch), 0xff); 537 cpc_writeb(falcbase + F_REG(RTR2, ch), 0xff); 538 cpc_writeb(falcbase + F_REG(ICB3, ch), 0); 539 cpc_writeb(falcbase + F_REG(TTR3, ch), 0xff); 540 cpc_writeb(falcbase + F_REG(RTR3, ch), 0xff); 541 if (conf->media == IF_IFACE_E1) { 542 cpc_writeb(falcbase + F_REG(ICB4, ch), 0); 543 cpc_writeb(falcbase + F_REG(TTR4, ch), 0xff); 544 cpc_writeb(falcbase + F_REG(RTR4, ch), 0xff); 545 } else { 546 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff); 547 cpc_writeb(falcbase + F_REG(TTR4, ch), 0x80); 548 cpc_writeb(falcbase + F_REG(RTR4, ch), 0x80); 549 } 550} 551 552static void falc_init_timeslot(pc300_t * card, int ch) 553{ 554 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 555 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 556 falc_t *pfalc = (falc_t *) & chan->falc; 557 int tslot; 558 559 for (tslot = 0; tslot < pfalc->num_channels; tslot++) { 560 if (conf->tslot_bitmap & (1 << tslot)) { 561 // Channel enabled 562 falc_open_timeslot(card, ch, tslot + 1); 563 } else { 564 // Channel disabled 565 falc_close_timeslot(card, ch, tslot + 1); 566 } 567 } 568} 569 570static void falc_enable_comm(pc300_t * card, int ch) 571{ 572 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 573 falc_t *pfalc = (falc_t *) & chan->falc; 574 575 if (pfalc->full_bandwidth) { 576 falc_open_all_timeslots(card, ch); 577 } else { 578 falc_init_timeslot(card, ch); 579 } 580 // CTS/DCD ON 581 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1, 582 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) & 583 ~((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch))); 584} 585 586static void falc_disable_comm(pc300_t * card, int ch) 587{ 588 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 589 falc_t *pfalc = (falc_t *) & chan->falc; 590 591 if (pfalc->loop_active != 2) { 592 falc_close_all_timeslots(card, ch); 593 } 594 // CTS/DCD OFF 595 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1, 596 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) | 597 ((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch))); 598} 599 600static void falc_init_t1(pc300_t * card, int ch) 601{ 602 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 603 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 604 falc_t *pfalc = (falc_t *) & chan->falc; 605 void __iomem *falcbase = card->hw.falcbase; 606 u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0); 607 608 /* Switch to T1 mode (PCM 24) */ 609 cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD); 610 611 /* Wait 20 us for setup */ 612 udelay(20); 613 614 /* Transmit Buffer Size (1 frame) */ 615 cpc_writeb(falcbase + F_REG(SIC1, ch), SIC1_XBS0); 616 617 /* Clock mode */ 618 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */ 619 cpc_writeb(falcbase + F_REG(LIM0, ch), 620 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS); 621 } else { /* Slave mode */ 622 cpc_writeb(falcbase + F_REG(LIM0, ch), 623 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS); 624 cpc_writeb(falcbase + F_REG(LOOP, ch), 625 cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_RTM); 626 } 627 628 cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI); 629 cpc_writeb(falcbase + F_REG(FMR0, ch), 630 cpc_readb(falcbase + F_REG(FMR0, ch)) & 631 ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1)); 632 633 switch (conf->lcode) { 634 case PC300_LC_AMI: 635 cpc_writeb(falcbase + F_REG(FMR0, ch), 636 cpc_readb(falcbase + F_REG(FMR0, ch)) | 637 FMR0_XC1 | FMR0_RC1); 638 /* Clear Channel register to ON for all channels */ 639 cpc_writeb(falcbase + F_REG(CCB1, ch), 0xff); 640 cpc_writeb(falcbase + F_REG(CCB2, ch), 0xff); 641 cpc_writeb(falcbase + F_REG(CCB3, ch), 0xff); 642 break; 643 644 case PC300_LC_B8ZS: 645 cpc_writeb(falcbase + F_REG(FMR0, ch), 646 cpc_readb(falcbase + F_REG(FMR0, ch)) | 647 FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1); 648 break; 649 650 case PC300_LC_NRZ: 651 cpc_writeb(falcbase + F_REG(FMR0, ch), 652 cpc_readb(falcbase + F_REG(FMR0, ch)) | 0x00); 653 break; 654 } 655 656 cpc_writeb(falcbase + F_REG(LIM0, ch), 657 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_ELOS); 658 cpc_writeb(falcbase + F_REG(LIM0, ch), 659 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0)); 660 /* Set interface mode to 2 MBPS */ 661 cpc_writeb(falcbase + F_REG(FMR1, ch), 662 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD); 663 664 switch (conf->fr_mode) { 665 case PC300_FR_ESF: 666 pfalc->multiframe_mode = 0; 667 cpc_writeb(falcbase + F_REG(FMR4, ch), 668 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_FM1); 669 cpc_writeb(falcbase + F_REG(FMR1, ch), 670 cpc_readb(falcbase + F_REG(FMR1, ch)) | 671 FMR1_CRC | FMR1_EDL); 672 cpc_writeb(falcbase + F_REG(XDL1, ch), 0); 673 cpc_writeb(falcbase + F_REG(XDL2, ch), 0); 674 cpc_writeb(falcbase + F_REG(XDL3, ch), 0); 675 cpc_writeb(falcbase + F_REG(FMR0, ch), 676 cpc_readb(falcbase + F_REG(FMR0, ch)) & ~FMR0_SRAF); 677 cpc_writeb(falcbase + F_REG(FMR2, ch), 678 cpc_readb(falcbase + F_REG(FMR2,ch)) | FMR2_MCSP | FMR2_SSP); 679 break; 680 681 case PC300_FR_D4: 682 pfalc->multiframe_mode = 1; 683 cpc_writeb(falcbase + F_REG(FMR4, ch), 684 cpc_readb(falcbase + F_REG(FMR4, ch)) & 685 ~(FMR4_FM1 | FMR4_FM0)); 686 cpc_writeb(falcbase + F_REG(FMR0, ch), 687 cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_SRAF); 688 cpc_writeb(falcbase + F_REG(FMR2, ch), 689 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_SSP); 690 break; 691 } 692 693 /* Enable Automatic Resynchronization */ 694 cpc_writeb(falcbase + F_REG(FMR4, ch), 695 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_AUTO); 696 697 /* Transmit Automatic Remote Alarm */ 698 cpc_writeb(falcbase + F_REG(FMR2, ch), 699 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA); 700 701 /* Channel translation mode 1 : one to one */ 702 cpc_writeb(falcbase + F_REG(FMR1, ch), 703 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CTM); 704 705 /* No signaling */ 706 cpc_writeb(falcbase + F_REG(FMR1, ch), 707 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_SIGM); 708 cpc_writeb(falcbase + F_REG(FMR5, ch), 709 cpc_readb(falcbase + F_REG(FMR5, ch)) & 710 ~(FMR5_EIBR | FMR5_SRS)); 711 cpc_writeb(falcbase + F_REG(CCR1, ch), 0); 712 713 cpc_writeb(falcbase + F_REG(LIM1, ch), 714 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1); 715 716 switch (conf->lbo) { 717 /* Provides proper Line Build Out */ 718 case PC300_LBO_0_DB: 719 cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja)); 720 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x5a); 721 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x8f); 722 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20); 723 break; 724 case PC300_LBO_7_5_DB: 725 cpc_writeb(falcbase + F_REG(LIM2, ch), (0x40 | LIM2_LOS1 | dja)); 726 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x11); 727 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x02); 728 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20); 729 break; 730 case PC300_LBO_15_DB: 731 cpc_writeb(falcbase + F_REG(LIM2, ch), (0x80 | LIM2_LOS1 | dja)); 732 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x8e); 733 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01); 734 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20); 735 break; 736 case PC300_LBO_22_5_DB: 737 cpc_writeb(falcbase + F_REG(LIM2, ch), (0xc0 | LIM2_LOS1 | dja)); 738 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x09); 739 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01); 740 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20); 741 break; 742 } 743 744 /* Transmit Clock-Slot Offset */ 745 cpc_writeb(falcbase + F_REG(XC0, ch), 746 cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01); 747 /* Transmit Time-slot Offset */ 748 cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e); 749 /* Receive Clock-Slot offset */ 750 cpc_writeb(falcbase + F_REG(RC0, ch), 0x05); 751 /* Receive Time-slot offset */ 752 cpc_writeb(falcbase + F_REG(RC1, ch), 0x00); 753 754 /* LOS Detection after 176 consecutive 0s */ 755 cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a); 756 /* LOS Recovery after 22 ones in the time window of PCD */ 757 cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15); 758 759 cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f); 760 761 if (conf->fr_mode == PC300_FR_ESF_JAPAN) { 762 cpc_writeb(falcbase + F_REG(RC1, ch), 763 cpc_readb(falcbase + F_REG(RC1, ch)) | 0x80); 764 } 765 766 falc_close_all_timeslots(card, ch); 767} 768 769static void falc_init_e1(pc300_t * card, int ch) 770{ 771 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 772 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 773 falc_t *pfalc = (falc_t *) & chan->falc; 774 void __iomem *falcbase = card->hw.falcbase; 775 u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0); 776 777 /* Switch to E1 mode (PCM 30) */ 778 cpc_writeb(falcbase + F_REG(FMR1, ch), 779 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_PMOD); 780 781 /* Clock mode */ 782 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */ 783 cpc_writeb(falcbase + F_REG(LIM0, ch), 784 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS); 785 } else { /* Slave mode */ 786 cpc_writeb(falcbase + F_REG(LIM0, ch), 787 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS); 788 } 789 cpc_writeb(falcbase + F_REG(LOOP, ch), 790 cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_SFM); 791 792 cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI); 793 cpc_writeb(falcbase + F_REG(FMR0, ch), 794 cpc_readb(falcbase + F_REG(FMR0, ch)) & 795 ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1)); 796 797 switch (conf->lcode) { 798 case PC300_LC_AMI: 799 cpc_writeb(falcbase + F_REG(FMR0, ch), 800 cpc_readb(falcbase + F_REG(FMR0, ch)) | 801 FMR0_XC1 | FMR0_RC1); 802 break; 803 804 case PC300_LC_HDB3: 805 cpc_writeb(falcbase + F_REG(FMR0, ch), 806 cpc_readb(falcbase + F_REG(FMR0, ch)) | 807 FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1); 808 break; 809 810 case PC300_LC_NRZ: 811 break; 812 } 813 814 cpc_writeb(falcbase + F_REG(LIM0, ch), 815 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0)); 816 /* Set interface mode to 2 MBPS */ 817 cpc_writeb(falcbase + F_REG(FMR1, ch), 818 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD); 819 820 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x18); 821 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x03); 822 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x00); 823 824 switch (conf->fr_mode) { 825 case PC300_FR_MF_CRC4: 826 pfalc->multiframe_mode = 1; 827 cpc_writeb(falcbase + F_REG(FMR1, ch), 828 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS); 829 cpc_writeb(falcbase + F_REG(FMR2, ch), 830 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1); 831 cpc_writeb(falcbase + F_REG(FMR2, ch), 832 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0); 833 cpc_writeb(falcbase + F_REG(FMR3, ch), 834 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW); 835 836 /* MultiFrame Resynchronization */ 837 cpc_writeb(falcbase + F_REG(FMR1, ch), 838 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS); 839 840 /* Automatic Loss of Multiframe > 914 CRC errors */ 841 cpc_writeb(falcbase + F_REG(FMR2, ch), 842 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF); 843 844 /* S1 and SI1/SI2 spare Bits set to 1 */ 845 cpc_writeb(falcbase + F_REG(XSP, ch), 846 cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS); 847 cpc_writeb(falcbase + F_REG(XSP, ch), 848 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP); 849 cpc_writeb(falcbase + F_REG(XSP, ch), 850 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15); 851 852 /* Automatic Force Resynchronization */ 853 cpc_writeb(falcbase + F_REG(FMR1, ch), 854 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR); 855 856 /* Transmit Automatic Remote Alarm */ 857 cpc_writeb(falcbase + F_REG(FMR2, ch), 858 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA); 859 860 /* Transmit Spare Bits for National Use (Y, Sn, Sa) */ 861 cpc_writeb(falcbase + F_REG(XSW, ch), 862 cpc_readb(falcbase + F_REG(XSW, ch)) | 863 XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4); 864 break; 865 866 case PC300_FR_MF_NON_CRC4: 867 case PC300_FR_D4: 868 pfalc->multiframe_mode = 0; 869 cpc_writeb(falcbase + F_REG(FMR1, ch), 870 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS); 871 cpc_writeb(falcbase + F_REG(FMR2, ch), 872 cpc_readb(falcbase + F_REG(FMR2, ch)) & 873 ~(FMR2_RFS1 | FMR2_RFS0)); 874 cpc_writeb(falcbase + F_REG(XSW, ch), 875 cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS); 876 cpc_writeb(falcbase + F_REG(XSP, ch), 877 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF); 878 879 /* Automatic Force Resynchronization */ 880 cpc_writeb(falcbase + F_REG(FMR1, ch), 881 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR); 882 883 /* Transmit Automatic Remote Alarm */ 884 cpc_writeb(falcbase + F_REG(FMR2, ch), 885 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA); 886 887 /* Transmit Spare Bits for National Use (Y, Sn, Sa) */ 888 cpc_writeb(falcbase + F_REG(XSW, ch), 889 cpc_readb(falcbase + F_REG(XSW, ch)) | 890 XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4); 891 break; 892 893 case PC300_FR_UNFRAMED: 894 pfalc->multiframe_mode = 0; 895 cpc_writeb(falcbase + F_REG(FMR1, ch), 896 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS); 897 cpc_writeb(falcbase + F_REG(FMR2, ch), 898 cpc_readb(falcbase + F_REG(FMR2, ch)) & 899 ~(FMR2_RFS1 | FMR2_RFS0)); 900 cpc_writeb(falcbase + F_REG(XSP, ch), 901 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0); 902 cpc_writeb(falcbase + F_REG(XSW, ch), 903 cpc_readb(falcbase + F_REG(XSW, ch)) & 904 ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4)); 905 cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff); 906 cpc_writeb(falcbase + F_REG(FMR2, ch), 907 cpc_readb(falcbase + F_REG(FMR2, ch)) | 908 (FMR2_RTM | FMR2_DAIS)); 909 cpc_writeb(falcbase + F_REG(FMR2, ch), 910 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA); 911 cpc_writeb(falcbase + F_REG(FMR1, ch), 912 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR); 913 pfalc->sync = 1; 914 cpc_writeb(falcbase + card->hw.cpld_reg2, 915 cpc_readb(falcbase + card->hw.cpld_reg2) | 916 (CPLD_REG2_FALC_LED2 << (2 * ch))); 917 break; 918 } 919 920 /* No signaling */ 921 cpc_writeb(falcbase + F_REG(XSP, ch), 922 cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN); 923 cpc_writeb(falcbase + F_REG(CCR1, ch), 0); 924 925 cpc_writeb(falcbase + F_REG(LIM1, ch), 926 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1); 927 cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja)); 928 929 /* Transmit Clock-Slot Offset */ 930 cpc_writeb(falcbase + F_REG(XC0, ch), 931 cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01); 932 /* Transmit Time-slot Offset */ 933 cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e); 934 /* Receive Clock-Slot offset */ 935 cpc_writeb(falcbase + F_REG(RC0, ch), 0x05); 936 /* Receive Time-slot offset */ 937 cpc_writeb(falcbase + F_REG(RC1, ch), 0x00); 938 939 /* LOS Detection after 176 consecutive 0s */ 940 cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a); 941 /* LOS Recovery after 22 ones in the time window of PCD */ 942 cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15); 943 944 cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f); 945 946 falc_close_all_timeslots(card, ch); 947} 948 949static void falc_init_hdlc(pc300_t * card, int ch) 950{ 951 void __iomem *falcbase = card->hw.falcbase; 952 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 953 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 954 955 /* Enable transparent data transfer */ 956 if (conf->fr_mode == PC300_FR_UNFRAMED) { 957 cpc_writeb(falcbase + F_REG(MODE, ch), 0); 958 } else { 959 cpc_writeb(falcbase + F_REG(MODE, ch), 960 cpc_readb(falcbase + F_REG(MODE, ch)) | 961 (MODE_HRAC | MODE_MDS2)); 962 cpc_writeb(falcbase + F_REG(RAH2, ch), 0xff); 963 cpc_writeb(falcbase + F_REG(RAH1, ch), 0xff); 964 cpc_writeb(falcbase + F_REG(RAL2, ch), 0xff); 965 cpc_writeb(falcbase + F_REG(RAL1, ch), 0xff); 966 } 967 968 /* Tx/Rx reset */ 969 falc_issue_cmd(card, ch, CMDR_RRES | CMDR_XRES | CMDR_SRES); 970 971 /* Enable interrupt sources */ 972 falc_intr_enable(card, ch); 973} 974 975static void te_config(pc300_t * card, int ch) 976{ 977 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 978 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 979 falc_t *pfalc = (falc_t *) & chan->falc; 980 void __iomem *falcbase = card->hw.falcbase; 981 u8 dummy; 982 unsigned long flags; 983 984 memset(pfalc, 0, sizeof(falc_t)); 985 switch (conf->media) { 986 case IF_IFACE_T1: 987 pfalc->num_channels = NUM_OF_T1_CHANNELS; 988 pfalc->offset = 1; 989 break; 990 case IF_IFACE_E1: 991 pfalc->num_channels = NUM_OF_E1_CHANNELS; 992 pfalc->offset = 0; 993 break; 994 } 995 if (conf->tslot_bitmap == 0xffffffffUL) 996 pfalc->full_bandwidth = 1; 997 else 998 pfalc->full_bandwidth = 0; 999 1000 CPC_LOCK(card, flags); 1001 /* Reset the FALC chip */ 1002 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1, 1003 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) | 1004 (CPLD_REG1_FALC_RESET << (2 * ch))); 1005 udelay(10000); 1006 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1, 1007 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) & 1008 ~(CPLD_REG1_FALC_RESET << (2 * ch))); 1009 1010 if (conf->media == IF_IFACE_T1) { 1011 falc_init_t1(card, ch); 1012 } else { 1013 falc_init_e1(card, ch); 1014 } 1015 falc_init_hdlc(card, ch); 1016 if (conf->rx_sens == PC300_RX_SENS_SH) { 1017 cpc_writeb(falcbase + F_REG(LIM0, ch), 1018 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON); 1019 } else { 1020 cpc_writeb(falcbase + F_REG(LIM0, ch), 1021 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON); 1022 } 1023 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2, 1024 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) | 1025 ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch))); 1026 1027 /* Clear all interrupt registers */ 1028 dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) + 1029 cpc_readb(falcbase + F_REG(FISR1, ch)) + 1030 cpc_readb(falcbase + F_REG(FISR2, ch)) + 1031 cpc_readb(falcbase + F_REG(FISR3, ch)); 1032 CPC_UNLOCK(card, flags); 1033} 1034 1035static void falc_check_status(pc300_t * card, int ch, unsigned char frs0) 1036{ 1037 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 1038 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 1039 falc_t *pfalc = (falc_t *) & chan->falc; 1040 void __iomem *falcbase = card->hw.falcbase; 1041 1042 /* Verify LOS */ 1043 if (frs0 & FRS0_LOS) { 1044 if (!pfalc->red_alarm) { 1045 pfalc->red_alarm = 1; 1046 pfalc->los++; 1047 if (!pfalc->blue_alarm) { 1048 // EVENT_FALC_ABNORMAL 1049 if (conf->media == IF_IFACE_T1) { 1050 /* Disable this interrupt as it may otherwise interfere 1051 * with other working boards. */ 1052 cpc_writeb(falcbase + F_REG(IMR0, ch), 1053 cpc_readb(falcbase + F_REG(IMR0, ch)) 1054 | IMR0_PDEN); 1055 } 1056 falc_disable_comm(card, ch); 1057 // EVENT_FALC_ABNORMAL 1058 } 1059 } 1060 } else { 1061 if (pfalc->red_alarm) { 1062 pfalc->red_alarm = 0; 1063 pfalc->losr++; 1064 } 1065 } 1066 1067 if (conf->fr_mode != PC300_FR_UNFRAMED) { 1068 /* Verify AIS alarm */ 1069 if (frs0 & FRS0_AIS) { 1070 if (!pfalc->blue_alarm) { 1071 pfalc->blue_alarm = 1; 1072 pfalc->ais++; 1073 // EVENT_AIS 1074 if (conf->media == IF_IFACE_T1) { 1075 /* Disable this interrupt as it may otherwise interfere with other working boards. */ 1076 cpc_writeb(falcbase + F_REG(IMR0, ch), 1077 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN); 1078 } 1079 falc_disable_comm(card, ch); 1080 // EVENT_AIS 1081 } 1082 } else { 1083 pfalc->blue_alarm = 0; 1084 } 1085 1086 /* Verify LFA */ 1087 if (frs0 & FRS0_LFA) { 1088 if (!pfalc->loss_fa) { 1089 pfalc->loss_fa = 1; 1090 pfalc->lfa++; 1091 if (!pfalc->blue_alarm && !pfalc->red_alarm) { 1092 // EVENT_FALC_ABNORMAL 1093 if (conf->media == IF_IFACE_T1) { 1094 /* Disable this interrupt as it may otherwise 1095 * interfere with other working boards. */ 1096 cpc_writeb(falcbase + F_REG(IMR0, ch), 1097 cpc_readb(falcbase + F_REG(IMR0, ch)) 1098 | IMR0_PDEN); 1099 } 1100 falc_disable_comm(card, ch); 1101 // EVENT_FALC_ABNORMAL 1102 } 1103 } 1104 } else { 1105 if (pfalc->loss_fa) { 1106 pfalc->loss_fa = 0; 1107 pfalc->farec++; 1108 } 1109 } 1110 1111 /* Verify LMFA */ 1112 if (pfalc->multiframe_mode && (frs0 & FRS0_LMFA)) { 1113 /* D4 or CRC4 frame mode */ 1114 if (!pfalc->loss_mfa) { 1115 pfalc->loss_mfa = 1; 1116 pfalc->lmfa++; 1117 if (!pfalc->blue_alarm && !pfalc->red_alarm && 1118 !pfalc->loss_fa) { 1119 // EVENT_FALC_ABNORMAL 1120 if (conf->media == IF_IFACE_T1) { 1121 /* Disable this interrupt as it may otherwise 1122 * interfere with other working boards. */ 1123 cpc_writeb(falcbase + F_REG(IMR0, ch), 1124 cpc_readb(falcbase + F_REG(IMR0, ch)) 1125 | IMR0_PDEN); 1126 } 1127 falc_disable_comm(card, ch); 1128 // EVENT_FALC_ABNORMAL 1129 } 1130 } 1131 } else { 1132 pfalc->loss_mfa = 0; 1133 } 1134 1135 /* Verify Remote Alarm */ 1136 if (frs0 & FRS0_RRA) { 1137 if (!pfalc->yellow_alarm) { 1138 pfalc->yellow_alarm = 1; 1139 pfalc->rai++; 1140 if (pfalc->sync) { 1141 // EVENT_RAI 1142 falc_disable_comm(card, ch); 1143 // EVENT_RAI 1144 } 1145 } 1146 } else { 1147 pfalc->yellow_alarm = 0; 1148 } 1149 } /* if !PC300_UNFRAMED */ 1150 1151 if (pfalc->red_alarm || pfalc->loss_fa || 1152 pfalc->loss_mfa || pfalc->blue_alarm) { 1153 if (pfalc->sync) { 1154 pfalc->sync = 0; 1155 chan->d.line_off++; 1156 cpc_writeb(falcbase + card->hw.cpld_reg2, 1157 cpc_readb(falcbase + card->hw.cpld_reg2) & 1158 ~(CPLD_REG2_FALC_LED2 << (2 * ch))); 1159 } 1160 } else { 1161 if (!pfalc->sync) { 1162 pfalc->sync = 1; 1163 chan->d.line_on++; 1164 cpc_writeb(falcbase + card->hw.cpld_reg2, 1165 cpc_readb(falcbase + card->hw.cpld_reg2) | 1166 (CPLD_REG2_FALC_LED2 << (2 * ch))); 1167 } 1168 } 1169 1170 if (pfalc->sync && !pfalc->yellow_alarm) { 1171 if (!pfalc->active) { 1172 // EVENT_FALC_NORMAL 1173 if (pfalc->loop_active) { 1174 return; 1175 } 1176 if (conf->media == IF_IFACE_T1) { 1177 cpc_writeb(falcbase + F_REG(IMR0, ch), 1178 cpc_readb(falcbase + F_REG(IMR0, ch)) & ~IMR0_PDEN); 1179 } 1180 falc_enable_comm(card, ch); 1181 // EVENT_FALC_NORMAL 1182 pfalc->active = 1; 1183 } 1184 } else { 1185 if (pfalc->active) { 1186 pfalc->active = 0; 1187 } 1188 } 1189} 1190 1191static void falc_update_stats(pc300_t * card, int ch) 1192{ 1193 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 1194 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 1195 falc_t *pfalc = (falc_t *) & chan->falc; 1196 void __iomem *falcbase = card->hw.falcbase; 1197 u16 counter; 1198 1199 counter = cpc_readb(falcbase + F_REG(FECL, ch)); 1200 counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8; 1201 pfalc->fec += counter; 1202 1203 counter = cpc_readb(falcbase + F_REG(CVCL, ch)); 1204 counter |= cpc_readb(falcbase + F_REG(CVCH, ch)) << 8; 1205 pfalc->cvc += counter; 1206 1207 counter = cpc_readb(falcbase + F_REG(CECL, ch)); 1208 counter |= cpc_readb(falcbase + F_REG(CECH, ch)) << 8; 1209 pfalc->cec += counter; 1210 1211 counter = cpc_readb(falcbase + F_REG(EBCL, ch)); 1212 counter |= cpc_readb(falcbase + F_REG(EBCH, ch)) << 8; 1213 pfalc->ebc += counter; 1214 1215 if (cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) { 1216 mdelay(10); 1217 counter = cpc_readb(falcbase + F_REG(BECL, ch)); 1218 counter |= cpc_readb(falcbase + F_REG(BECH, ch)) << 8; 1219 pfalc->bec += counter; 1220 1221 if (((conf->media == IF_IFACE_T1) && 1222 (cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_LLBAD) && 1223 (!(cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_PDEN))) || 1224 ((conf->media == IF_IFACE_E1) && 1225 (cpc_readb(falcbase + F_REG(RSP, ch)) & RSP_LLBAD))) { 1226 pfalc->prbs = 2; 1227 } else { 1228 pfalc->prbs = 1; 1229 } 1230 } 1231} 1232 1233/*---------------------------------------------------------------------------- 1234 * falc_remote_loop 1235 *---------------------------------------------------------------------------- 1236 * Description: In the remote loopback mode the clock and data recovered 1237 * from the line inputs RL1/2 or RDIP/RDIN are routed back 1238 * to the line outputs XL1/2 or XDOP/XDON via the analog 1239 * transmitter. As in normal mode they are processsed by 1240 * the synchronizer and then sent to the system interface. 1241 *---------------------------------------------------------------------------- 1242 */ 1243static void falc_remote_loop(pc300_t * card, int ch, int loop_on) 1244{ 1245 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 1246 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 1247 falc_t *pfalc = (falc_t *) & chan->falc; 1248 void __iomem *falcbase = card->hw.falcbase; 1249 1250 if (loop_on) { 1251 // EVENT_FALC_ABNORMAL 1252 if (conf->media == IF_IFACE_T1) { 1253 /* Disable this interrupt as it may otherwise interfere with 1254 * other working boards. */ 1255 cpc_writeb(falcbase + F_REG(IMR0, ch), 1256 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN); 1257 } 1258 falc_disable_comm(card, ch); 1259 // EVENT_FALC_ABNORMAL 1260 cpc_writeb(falcbase + F_REG(LIM1, ch), 1261 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RL); 1262 pfalc->loop_active = 1; 1263 } else { 1264 cpc_writeb(falcbase + F_REG(LIM1, ch), 1265 cpc_readb(falcbase + F_REG(LIM1, ch)) & ~LIM1_RL); 1266 pfalc->sync = 0; 1267 cpc_writeb(falcbase + card->hw.cpld_reg2, 1268 cpc_readb(falcbase + card->hw.cpld_reg2) & 1269 ~(CPLD_REG2_FALC_LED2 << (2 * ch))); 1270 pfalc->active = 0; 1271 falc_issue_cmd(card, ch, CMDR_XRES); 1272 pfalc->loop_active = 0; 1273 } 1274} 1275 1276/*---------------------------------------------------------------------------- 1277 * falc_local_loop 1278 *---------------------------------------------------------------------------- 1279 * Description: The local loopback mode disconnects the receive lines 1280 * RL1/RL2 resp. RDIP/RDIN from the receiver. Instead of the 1281 * signals coming from the line the data provided by system 1282 * interface are routed through the analog receiver back to 1283 * the system interface. The unipolar bit stream will be 1284 * undisturbed transmitted on the line. Receiver and transmitter 1285 * coding must be identical. 1286 *---------------------------------------------------------------------------- 1287 */ 1288static void falc_local_loop(pc300_t * card, int ch, int loop_on) 1289{ 1290 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 1291 falc_t *pfalc = (falc_t *) & chan->falc; 1292 void __iomem *falcbase = card->hw.falcbase; 1293 1294 if (loop_on) { 1295 cpc_writeb(falcbase + F_REG(LIM0, ch), 1296 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_LL); 1297 pfalc->loop_active = 1; 1298 } else { 1299 cpc_writeb(falcbase + F_REG(LIM0, ch), 1300 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_LL); 1301 pfalc->loop_active = 0; 1302 } 1303} 1304 1305/*---------------------------------------------------------------------------- 1306 * falc_payload_loop 1307 *---------------------------------------------------------------------------- 1308 * Description: This routine allows to enable/disable payload loopback. 1309 * When the payload loop is activated, the received 192 bits 1310 * of payload data will be looped back to the transmit 1311 * direction. The framing bits, CRC6 and DL bits are not 1312 * looped. They are originated by the FALC-LH transmitter. 1313 *---------------------------------------------------------------------------- 1314 */ 1315static void falc_payload_loop(pc300_t * card, int ch, int loop_on) 1316{ 1317 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 1318 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 1319 falc_t *pfalc = (falc_t *) & chan->falc; 1320 void __iomem *falcbase = card->hw.falcbase; 1321 1322 if (loop_on) { 1323 // EVENT_FALC_ABNORMAL 1324 if (conf->media == IF_IFACE_T1) { 1325 /* Disable this interrupt as it may otherwise interfere with 1326 * other working boards. */ 1327 cpc_writeb(falcbase + F_REG(IMR0, ch), 1328 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN); 1329 } 1330 falc_disable_comm(card, ch); 1331 // EVENT_FALC_ABNORMAL 1332 cpc_writeb(falcbase + F_REG(FMR2, ch), 1333 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_PLB); 1334 if (conf->media == IF_IFACE_T1) { 1335 cpc_writeb(falcbase + F_REG(FMR4, ch), 1336 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_TM); 1337 } else { 1338 cpc_writeb(falcbase + F_REG(FMR5, ch), 1339 cpc_readb(falcbase + F_REG(FMR5, ch)) | XSP_TT0); 1340 } 1341 falc_open_all_timeslots(card, ch); 1342 pfalc->loop_active = 2; 1343 } else { 1344 cpc_writeb(falcbase + F_REG(FMR2, ch), 1345 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_PLB); 1346 if (conf->media == IF_IFACE_T1) { 1347 cpc_writeb(falcbase + F_REG(FMR4, ch), 1348 cpc_readb(falcbase + F_REG(FMR4, ch)) & ~FMR4_TM); 1349 } else { 1350 cpc_writeb(falcbase + F_REG(FMR5, ch), 1351 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~XSP_TT0); 1352 } 1353 pfalc->sync = 0; 1354 cpc_writeb(falcbase + card->hw.cpld_reg2, 1355 cpc_readb(falcbase + card->hw.cpld_reg2) & 1356 ~(CPLD_REG2_FALC_LED2 << (2 * ch))); 1357 pfalc->active = 0; 1358 falc_issue_cmd(card, ch, CMDR_XRES); 1359 pfalc->loop_active = 0; 1360 } 1361} 1362 1363/*---------------------------------------------------------------------------- 1364 * turn_off_xlu 1365 *---------------------------------------------------------------------------- 1366 * Description: Turns XLU bit off in the proper register 1367 *---------------------------------------------------------------------------- 1368 */ 1369static void turn_off_xlu(pc300_t * card, int ch) 1370{ 1371 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 1372 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 1373 void __iomem *falcbase = card->hw.falcbase; 1374 1375 if (conf->media == IF_IFACE_T1) { 1376 cpc_writeb(falcbase + F_REG(FMR5, ch), 1377 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLU); 1378 } else { 1379 cpc_writeb(falcbase + F_REG(FMR3, ch), 1380 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLU); 1381 } 1382} 1383 1384/*---------------------------------------------------------------------------- 1385 * turn_off_xld 1386 *---------------------------------------------------------------------------- 1387 * Description: Turns XLD bit off in the proper register 1388 *---------------------------------------------------------------------------- 1389 */ 1390static void turn_off_xld(pc300_t * card, int ch) 1391{ 1392 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 1393 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 1394 void __iomem *falcbase = card->hw.falcbase; 1395 1396 if (conf->media == IF_IFACE_T1) { 1397 cpc_writeb(falcbase + F_REG(FMR5, ch), 1398 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLD); 1399 } else { 1400 cpc_writeb(falcbase + F_REG(FMR3, ch), 1401 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLD); 1402 } 1403} 1404 1405/*---------------------------------------------------------------------------- 1406 * falc_generate_loop_up_code 1407 *---------------------------------------------------------------------------- 1408 * Description: This routine writes the proper FALC chip register in order 1409 * to generate a LOOP activation code over a T1/E1 line. 1410 *---------------------------------------------------------------------------- 1411 */ 1412static void falc_generate_loop_up_code(pc300_t * card, int ch) 1413{ 1414 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 1415 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 1416 falc_t *pfalc = (falc_t *) & chan->falc; 1417 void __iomem *falcbase = card->hw.falcbase; 1418 1419 if (conf->media == IF_IFACE_T1) { 1420 cpc_writeb(falcbase + F_REG(FMR5, ch), 1421 cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLU); 1422 } else { 1423 cpc_writeb(falcbase + F_REG(FMR3, ch), 1424 cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLU); 1425 } 1426 // EVENT_FALC_ABNORMAL 1427 if (conf->media == IF_IFACE_T1) { 1428 /* Disable this interrupt as it may otherwise interfere with 1429 * other working boards. */ 1430 cpc_writeb(falcbase + F_REG(IMR0, ch), 1431 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN); 1432 } 1433 falc_disable_comm(card, ch); 1434 // EVENT_FALC_ABNORMAL 1435 pfalc->loop_gen = 1; 1436} 1437 1438/*---------------------------------------------------------------------------- 1439 * falc_generate_loop_down_code 1440 *---------------------------------------------------------------------------- 1441 * Description: This routine writes the proper FALC chip register in order 1442 * to generate a LOOP deactivation code over a T1/E1 line. 1443 *---------------------------------------------------------------------------- 1444 */ 1445static void falc_generate_loop_down_code(pc300_t * card, int ch) 1446{ 1447 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 1448 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 1449 falc_t *pfalc = (falc_t *) & chan->falc; 1450 void __iomem *falcbase = card->hw.falcbase; 1451 1452 if (conf->media == IF_IFACE_T1) { 1453 cpc_writeb(falcbase + F_REG(FMR5, ch), 1454 cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLD); 1455 } else { 1456 cpc_writeb(falcbase + F_REG(FMR3, ch), 1457 cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLD); 1458 } 1459 pfalc->sync = 0; 1460 cpc_writeb(falcbase + card->hw.cpld_reg2, 1461 cpc_readb(falcbase + card->hw.cpld_reg2) & 1462 ~(CPLD_REG2_FALC_LED2 << (2 * ch))); 1463 pfalc->active = 0; 1464//? falc_issue_cmd(card, ch, CMDR_XRES); 1465 pfalc->loop_gen = 0; 1466} 1467 1468/*---------------------------------------------------------------------------- 1469 * falc_pattern_test 1470 *---------------------------------------------------------------------------- 1471 * Description: This routine generates a pattern code and checks 1472 * it on the reception side. 1473 *---------------------------------------------------------------------------- 1474 */ 1475static void falc_pattern_test(pc300_t * card, int ch, unsigned int activate) 1476{ 1477 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 1478 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 1479 falc_t *pfalc = (falc_t *) & chan->falc; 1480 void __iomem *falcbase = card->hw.falcbase; 1481 1482 if (activate) { 1483 pfalc->prbs = 1; 1484 pfalc->bec = 0; 1485 if (conf->media == IF_IFACE_T1) { 1486 /* Disable local loop activation/deactivation detect */ 1487 cpc_writeb(falcbase + F_REG(IMR3, ch), 1488 cpc_readb(falcbase + F_REG(IMR3, ch)) | IMR3_LLBSC); 1489 } else { 1490 /* Disable local loop activation/deactivation detect */ 1491 cpc_writeb(falcbase + F_REG(IMR1, ch), 1492 cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_LLBSC); 1493 } 1494 /* Activates generation and monitoring of PRBS 1495 * (Pseudo Random Bit Sequence) */ 1496 cpc_writeb(falcbase + F_REG(LCR1, ch), 1497 cpc_readb(falcbase + F_REG(LCR1, ch)) | LCR1_EPRM | LCR1_XPRBS); 1498 } else { 1499 pfalc->prbs = 0; 1500 /* Deactivates generation and monitoring of PRBS 1501 * (Pseudo Random Bit Sequence) */ 1502 cpc_writeb(falcbase + F_REG(LCR1, ch), 1503 cpc_readb(falcbase+F_REG(LCR1,ch)) & ~(LCR1_EPRM | LCR1_XPRBS)); 1504 if (conf->media == IF_IFACE_T1) { 1505 /* Enable local loop activation/deactivation detect */ 1506 cpc_writeb(falcbase + F_REG(IMR3, ch), 1507 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC); 1508 } else { 1509 /* Enable local loop activation/deactivation detect */ 1510 cpc_writeb(falcbase + F_REG(IMR1, ch), 1511 cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_LLBSC); 1512 } 1513 } 1514} 1515 1516/*---------------------------------------------------------------------------- 1517 * falc_pattern_test_error 1518 *---------------------------------------------------------------------------- 1519 * Description: This routine returns the bit error counter value 1520 *---------------------------------------------------------------------------- 1521 */ 1522static u16 falc_pattern_test_error(pc300_t * card, int ch) 1523{ 1524 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 1525 falc_t *pfalc = (falc_t *) & chan->falc; 1526 1527 return (pfalc->bec); 1528} 1529 1530/**********************************/ 1531/*** Net Interface Routines ***/ 1532/**********************************/ 1533 1534static void 1535cpc_trace(struct net_device *dev, struct sk_buff *skb_main, char rx_tx) 1536{ 1537 struct sk_buff *skb; 1538 1539 if ((skb = dev_alloc_skb(10 + skb_main->len)) == NULL) { 1540 printk("%s: out of memory\n", dev->name); 1541 return; 1542 } 1543 skb_put(skb, 10 + skb_main->len); 1544 1545 skb->dev = dev; 1546 skb->protocol = htons(ETH_P_CUST); 1547 skb_reset_mac_header(skb); 1548 skb->pkt_type = PACKET_HOST; 1549 skb->len = 10 + skb_main->len; 1550 1551 skb_copy_to_linear_data(skb, dev->name, 5); 1552 skb->data[5] = '['; 1553 skb->data[6] = rx_tx; 1554 skb->data[7] = ']'; 1555 skb->data[8] = ':'; 1556 skb->data[9] = ' '; 1557 skb_copy_from_linear_data(skb_main, &skb->data[10], skb_main->len); 1558 1559 netif_rx(skb); 1560} 1561 1562static void cpc_tx_timeout(struct net_device *dev) 1563{ 1564 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv; 1565 pc300ch_t *chan = (pc300ch_t *) d->chan; 1566 pc300_t *card = (pc300_t *) chan->card; 1567 int ch = chan->channel; 1568 unsigned long flags; 1569 u8 ilar; 1570 1571 dev->stats.tx_errors++; 1572 dev->stats.tx_aborted_errors++; 1573 CPC_LOCK(card, flags); 1574 if ((ilar = cpc_readb(card->hw.scabase + ILAR)) != 0) { 1575 printk("%s: ILAR=0x%x\n", dev->name, ilar); 1576 cpc_writeb(card->hw.scabase + ILAR, ilar); 1577 cpc_writeb(card->hw.scabase + DMER, 0x80); 1578 } 1579 if (card->hw.type == PC300_TE) { 1580 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2, 1581 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) & 1582 ~(CPLD_REG2_FALC_LED1 << (2 * ch))); 1583 } 1584 dev->trans_start = jiffies; /* prevent tx timeout */ 1585 CPC_UNLOCK(card, flags); 1586 netif_wake_queue(dev); 1587} 1588 1589static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev) 1590{ 1591 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv; 1592 pc300ch_t *chan = (pc300ch_t *) d->chan; 1593 pc300_t *card = (pc300_t *) chan->card; 1594 int ch = chan->channel; 1595 unsigned long flags; 1596#ifdef PC300_DEBUG_TX 1597 int i; 1598#endif 1599 1600 if (!netif_carrier_ok(dev)) { 1601 /* DCD must be OFF: drop packet */ 1602 dev_kfree_skb(skb); 1603 dev->stats.tx_errors++; 1604 dev->stats.tx_carrier_errors++; 1605 return 0; 1606 } else if (cpc_readb(card->hw.scabase + M_REG(ST3, ch)) & ST3_DCD) { 1607 printk("%s: DCD is OFF. Going administrative down.\n", dev->name); 1608 dev->stats.tx_errors++; 1609 dev->stats.tx_carrier_errors++; 1610 dev_kfree_skb(skb); 1611 netif_carrier_off(dev); 1612 CPC_LOCK(card, flags); 1613 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_BUF_CLR); 1614 if (card->hw.type == PC300_TE) { 1615 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2, 1616 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) & 1617 ~(CPLD_REG2_FALC_LED1 << (2 * ch))); 1618 } 1619 CPC_UNLOCK(card, flags); 1620 netif_wake_queue(dev); 1621 return 0; 1622 } 1623 1624 /* Write buffer to DMA buffers */ 1625 if (dma_buf_write(card, ch, (u8 *)skb->data, skb->len) != 0) { 1626// printk("%s: write error. Dropping TX packet.\n", dev->name); 1627 netif_stop_queue(dev); 1628 dev_kfree_skb(skb); 1629 dev->stats.tx_errors++; 1630 dev->stats.tx_dropped++; 1631 return 0; 1632 } 1633#ifdef PC300_DEBUG_TX 1634 printk("%s T:", dev->name); 1635 for (i = 0; i < skb->len; i++) 1636 printk(" %02x", *(skb->data + i)); 1637 printk("\n"); 1638#endif 1639 1640 if (d->trace_on) { 1641 cpc_trace(dev, skb, 'T'); 1642 } 1643 1644 /* Start transmission */ 1645 CPC_LOCK(card, flags); 1646 /* verify if it has more than one free descriptor */ 1647 if (card->chan[ch].nfree_tx_bd <= 1) { 1648 /* don't have so stop the queue */ 1649 netif_stop_queue(dev); 1650 } 1651 cpc_writel(card->hw.scabase + DTX_REG(EDAL, ch), 1652 TX_BD_ADDR(ch, chan->tx_next_bd)); 1653 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_ENA); 1654 cpc_writeb(card->hw.scabase + DSR_TX(ch), DSR_DE); 1655 if (card->hw.type == PC300_TE) { 1656 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2, 1657 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) | 1658 (CPLD_REG2_FALC_LED1 << (2 * ch))); 1659 } 1660 CPC_UNLOCK(card, flags); 1661 dev_kfree_skb(skb); 1662 1663 return 0; 1664} 1665 1666static void cpc_net_rx(struct net_device *dev) 1667{ 1668 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv; 1669 pc300ch_t *chan = (pc300ch_t *) d->chan; 1670 pc300_t *card = (pc300_t *) chan->card; 1671 int ch = chan->channel; 1672#ifdef PC300_DEBUG_RX 1673 int i; 1674#endif 1675 int rxb; 1676 struct sk_buff *skb; 1677 1678 while (1) { 1679 if ((rxb = dma_get_rx_frame_size(card, ch)) == -1) 1680 return; 1681 1682 if (!netif_carrier_ok(dev)) { 1683 /* DCD must be OFF: drop packet */ 1684 printk("%s : DCD is OFF - drop %d rx bytes\n", dev->name, rxb); 1685 skb = NULL; 1686 } else { 1687 if (rxb > (dev->mtu + 40)) { /* add headers */ 1688 printk("%s : MTU exceeded %d\n", dev->name, rxb); 1689 skb = NULL; 1690 } else { 1691 skb = dev_alloc_skb(rxb); 1692 if (skb == NULL) { 1693 printk("%s: Memory squeeze!!\n", dev->name); 1694 return; 1695 } 1696 skb->dev = dev; 1697 } 1698 } 1699 1700 if (((rxb = dma_buf_read(card, ch, skb)) <= 0) || (skb == NULL)) { 1701#ifdef PC300_DEBUG_RX 1702 printk("%s: rxb = %x\n", dev->name, rxb); 1703#endif 1704 if ((skb == NULL) && (rxb > 0)) { 1705 /* rxb > dev->mtu */ 1706 dev->stats.rx_errors++; 1707 dev->stats.rx_length_errors++; 1708 continue; 1709 } 1710 1711 if (rxb < 0) { /* Invalid frame */ 1712 rxb = -rxb; 1713 if (rxb & DST_OVR) { 1714 dev->stats.rx_errors++; 1715 dev->stats.rx_fifo_errors++; 1716 } 1717 if (rxb & DST_CRC) { 1718 dev->stats.rx_errors++; 1719 dev->stats.rx_crc_errors++; 1720 } 1721 if (rxb & (DST_RBIT | DST_SHRT | DST_ABT)) { 1722 dev->stats.rx_errors++; 1723 dev->stats.rx_frame_errors++; 1724 } 1725 } 1726 if (skb) { 1727 dev_kfree_skb_irq(skb); 1728 } 1729 continue; 1730 } 1731 1732 dev->stats.rx_bytes += rxb; 1733 1734#ifdef PC300_DEBUG_RX 1735 printk("%s R:", dev->name); 1736 for (i = 0; i < skb->len; i++) 1737 printk(" %02x", *(skb->data + i)); 1738 printk("\n"); 1739#endif 1740 if (d->trace_on) { 1741 cpc_trace(dev, skb, 'R'); 1742 } 1743 dev->stats.rx_packets++; 1744 skb->protocol = hdlc_type_trans(skb, dev); 1745 netif_rx(skb); 1746 } 1747} 1748 1749/************************************/ 1750/*** PC300 Interrupt Routines ***/ 1751/************************************/ 1752static void sca_tx_intr(pc300dev_t *dev) 1753{ 1754 pc300ch_t *chan = (pc300ch_t *)dev->chan; 1755 pc300_t *card = (pc300_t *)chan->card; 1756 int ch = chan->channel; 1757 volatile pcsca_bd_t __iomem * ptdescr; 1758 1759 /* Clean up descriptors from previous transmission */ 1760 ptdescr = (card->hw.rambase + 1761 TX_BD_ADDR(ch,chan->tx_first_bd)); 1762 while ((cpc_readl(card->hw.scabase + DTX_REG(CDAL,ch)) != 1763 TX_BD_ADDR(ch,chan->tx_first_bd)) && 1764 (cpc_readb(&ptdescr->status) & DST_OSB)) { 1765 dev->dev->stats.tx_packets++; 1766 dev->dev->stats.tx_bytes += cpc_readw(&ptdescr->len); 1767 cpc_writeb(&ptdescr->status, DST_OSB); 1768 cpc_writew(&ptdescr->len, 0); 1769 chan->nfree_tx_bd++; 1770 chan->tx_first_bd = (chan->tx_first_bd + 1) & (N_DMA_TX_BUF - 1); 1771 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch,chan->tx_first_bd)); 1772 } 1773 1774#ifdef CONFIG_PC300_MLPPP 1775 if (chan->conf.proto == PC300_PROTO_MLPPP) { 1776 cpc_tty_trigger_poll(dev); 1777 } else { 1778#endif 1779 /* Tell the upper layer we are ready to transmit more packets */ 1780 netif_wake_queue(dev->dev); 1781#ifdef CONFIG_PC300_MLPPP 1782 } 1783#endif 1784} 1785 1786static void sca_intr(pc300_t * card) 1787{ 1788 void __iomem *scabase = card->hw.scabase; 1789 volatile u32 status; 1790 int ch; 1791 int intr_count = 0; 1792 unsigned char dsr_rx; 1793 1794 while ((status = cpc_readl(scabase + ISR0)) != 0) { 1795 for (ch = 0; ch < card->hw.nchan; ch++) { 1796 pc300ch_t *chan = &card->chan[ch]; 1797 pc300dev_t *d = &chan->d; 1798 struct net_device *dev = d->dev; 1799 1800 spin_lock(&card->card_lock); 1801 1802 /**** Reception ****/ 1803 if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) { 1804 u8 drx_stat = cpc_readb(scabase + DSR_RX(ch)); 1805 1806 /* Clear RX interrupts */ 1807 cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE); 1808 1809#ifdef PC300_DEBUG_INTR 1810 printk ("sca_intr: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n", 1811 ch, status, drx_stat); 1812#endif 1813 if (status & IR0_DRX(IR0_DMIA, ch)) { 1814 if (drx_stat & DSR_BOF) { 1815#ifdef CONFIG_PC300_MLPPP 1816 if (chan->conf.proto == PC300_PROTO_MLPPP) { 1817 /* verify if driver is TTY */ 1818 if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) { 1819 rx_dma_stop(card, ch); 1820 } 1821 cpc_tty_receive(d); 1822 rx_dma_start(card, ch); 1823 } else 1824#endif 1825 { 1826 if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) { 1827 rx_dma_stop(card, ch); 1828 } 1829 cpc_net_rx(dev); 1830 /* Discard invalid frames */ 1831 dev->stats.rx_errors++; 1832 dev->stats.rx_over_errors++; 1833 chan->rx_first_bd = 0; 1834 chan->rx_last_bd = N_DMA_RX_BUF - 1; 1835 rx_dma_start(card, ch); 1836 } 1837 } 1838 } 1839 if (status & IR0_DRX(IR0_DMIB, ch)) { 1840 if (drx_stat & DSR_EOM) { 1841 if (card->hw.type == PC300_TE) { 1842 cpc_writeb(card->hw.falcbase + 1843 card->hw.cpld_reg2, 1844 cpc_readb (card->hw.falcbase + 1845 card->hw.cpld_reg2) | 1846 (CPLD_REG2_FALC_LED1 << (2 * ch))); 1847 } 1848#ifdef CONFIG_PC300_MLPPP 1849 if (chan->conf.proto == PC300_PROTO_MLPPP) { 1850 /* verify if driver is TTY */ 1851 cpc_tty_receive(d); 1852 } else { 1853 cpc_net_rx(dev); 1854 } 1855#else 1856 cpc_net_rx(dev); 1857#endif 1858 if (card->hw.type == PC300_TE) { 1859 cpc_writeb(card->hw.falcbase + 1860 card->hw.cpld_reg2, 1861 cpc_readb (card->hw.falcbase + 1862 card->hw.cpld_reg2) & 1863 ~ (CPLD_REG2_FALC_LED1 << (2 * ch))); 1864 } 1865 } 1866 } 1867 if (!(dsr_rx = cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) { 1868#ifdef PC300_DEBUG_INTR 1869 printk("%s: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x, dsr2=0x%02x)\n", 1870 dev->name, ch, status, drx_stat, dsr_rx); 1871#endif 1872 cpc_writeb(scabase + DSR_RX(ch), (dsr_rx | DSR_DE) & 0xfe); 1873 } 1874 } 1875 1876 /**** Transmission ****/ 1877 if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) { 1878 u8 dtx_stat = cpc_readb(scabase + DSR_TX(ch)); 1879 1880 /* Clear TX interrupts */ 1881 cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE); 1882 1883#ifdef PC300_DEBUG_INTR 1884 printk ("sca_intr: TX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n", 1885 ch, status, dtx_stat); 1886#endif 1887 if (status & IR0_DTX(IR0_EFT, ch)) { 1888 if (dtx_stat & DSR_UDRF) { 1889 if (cpc_readb (scabase + M_REG(TBN, ch)) != 0) { 1890 cpc_writeb(scabase + M_REG(CMD,ch), CMD_TX_BUF_CLR); 1891 } 1892 if (card->hw.type == PC300_TE) { 1893 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2, 1894 cpc_readb (card->hw.falcbase + 1895 card->hw.cpld_reg2) & 1896 ~ (CPLD_REG2_FALC_LED1 << (2 * ch))); 1897 } 1898 dev->stats.tx_errors++; 1899 dev->stats.tx_fifo_errors++; 1900 sca_tx_intr(d); 1901 } 1902 } 1903 if (status & IR0_DTX(IR0_DMIA, ch)) { 1904 if (dtx_stat & DSR_BOF) { 1905 } 1906 } 1907 if (status & IR0_DTX(IR0_DMIB, ch)) { 1908 if (dtx_stat & DSR_EOM) { 1909 if (card->hw.type == PC300_TE) { 1910 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2, 1911 cpc_readb (card->hw.falcbase + 1912 card->hw.cpld_reg2) & 1913 ~ (CPLD_REG2_FALC_LED1 << (2 * ch))); 1914 } 1915 sca_tx_intr(d); 1916 } 1917 } 1918 } 1919 1920 /**** MSCI ****/ 1921 if (status & IR0_M(IR0_RXINTA, ch)) { 1922 u8 st1 = cpc_readb(scabase + M_REG(ST1, ch)); 1923 1924 /* Clear MSCI interrupts */ 1925 cpc_writeb(scabase + M_REG(ST1, ch), st1); 1926 1927#ifdef PC300_DEBUG_INTR 1928 printk("sca_intr: MSCI intr chan[%d] (st=0x%08lx, st1=0x%02x)\n", 1929 ch, status, st1); 1930#endif 1931 if (st1 & ST1_CDCD) { /* DCD changed */ 1932 if (cpc_readb(scabase + M_REG(ST3, ch)) & ST3_DCD) { 1933 printk ("%s: DCD is OFF. Going administrative down.\n", 1934 dev->name); 1935#ifdef CONFIG_PC300_MLPPP 1936 if (chan->conf.proto != PC300_PROTO_MLPPP) { 1937 netif_carrier_off(dev); 1938 } 1939#else 1940 netif_carrier_off(dev); 1941 1942#endif 1943 card->chan[ch].d.line_off++; 1944 } else { /* DCD = 1 */ 1945 printk ("%s: DCD is ON. Going administrative up.\n", 1946 dev->name); 1947#ifdef CONFIG_PC300_MLPPP 1948 if (chan->conf.proto != PC300_PROTO_MLPPP) 1949 /* verify if driver is not TTY */ 1950#endif 1951 netif_carrier_on(dev); 1952 card->chan[ch].d.line_on++; 1953 } 1954 } 1955 } 1956 spin_unlock(&card->card_lock); 1957 } 1958 if (++intr_count == 10) 1959 /* Too much work at this board. Force exit */ 1960 break; 1961 } 1962} 1963 1964static void falc_t1_loop_detection(pc300_t *card, int ch, u8 frs1) 1965{ 1966 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 1967 falc_t *pfalc = (falc_t *) & chan->falc; 1968 void __iomem *falcbase = card->hw.falcbase; 1969 1970 if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) && 1971 !pfalc->loop_gen) { 1972 if (frs1 & FRS1_LLBDD) { 1973 // A Line Loop Back Deactivation signal detected 1974 if (pfalc->loop_active) { 1975 falc_remote_loop(card, ch, 0); 1976 } 1977 } else { 1978 if ((frs1 & FRS1_LLBAD) && 1979 ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) { 1980 // A Line Loop Back Activation signal detected 1981 if (!pfalc->loop_active) { 1982 falc_remote_loop(card, ch, 1); 1983 } 1984 } 1985 } 1986 } 1987} 1988 1989static void falc_e1_loop_detection(pc300_t *card, int ch, u8 rsp) 1990{ 1991 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 1992 falc_t *pfalc = (falc_t *) & chan->falc; 1993 void __iomem *falcbase = card->hw.falcbase; 1994 1995 if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) && 1996 !pfalc->loop_gen) { 1997 if (rsp & RSP_LLBDD) { 1998 // A Line Loop Back Deactivation signal detected 1999 if (pfalc->loop_active) { 2000 falc_remote_loop(card, ch, 0); 2001 } 2002 } else { 2003 if ((rsp & RSP_LLBAD) && 2004 ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) { 2005 // A Line Loop Back Activation signal detected 2006 if (!pfalc->loop_active) { 2007 falc_remote_loop(card, ch, 1); 2008 } 2009 } 2010 } 2011 } 2012} 2013 2014static void falc_t1_intr(pc300_t * card, int ch) 2015{ 2016 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 2017 falc_t *pfalc = (falc_t *) & chan->falc; 2018 void __iomem *falcbase = card->hw.falcbase; 2019 u8 isr0, isr3, gis; 2020 u8 dummy; 2021 2022 while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) { 2023 if (gis & GIS_ISR0) { 2024 isr0 = cpc_readb(falcbase + F_REG(FISR0, ch)); 2025 if (isr0 & FISR0_PDEN) { 2026 /* Read the bit to clear the situation */ 2027 if (cpc_readb(falcbase + F_REG(FRS1, ch)) & 2028 FRS1_PDEN) { 2029 pfalc->pden++; 2030 } 2031 } 2032 } 2033 2034 if (gis & GIS_ISR1) { 2035 dummy = cpc_readb(falcbase + F_REG(FISR1, ch)); 2036 } 2037 2038 if (gis & GIS_ISR2) { 2039 dummy = cpc_readb(falcbase + F_REG(FISR2, ch)); 2040 } 2041 2042 if (gis & GIS_ISR3) { 2043 isr3 = cpc_readb(falcbase + F_REG(FISR3, ch)); 2044 if (isr3 & FISR3_SEC) { 2045 pfalc->sec++; 2046 falc_update_stats(card, ch); 2047 falc_check_status(card, ch, 2048 cpc_readb(falcbase + F_REG(FRS0, ch))); 2049 } 2050 if (isr3 & FISR3_ES) { 2051 pfalc->es++; 2052 } 2053 if (isr3 & FISR3_LLBSC) { 2054 falc_t1_loop_detection(card, ch, 2055 cpc_readb(falcbase + F_REG(FRS1, ch))); 2056 } 2057 } 2058 } 2059} 2060 2061static void falc_e1_intr(pc300_t * card, int ch) 2062{ 2063 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; 2064 falc_t *pfalc = (falc_t *) & chan->falc; 2065 void __iomem *falcbase = card->hw.falcbase; 2066 u8 isr1, isr2, isr3, gis, rsp; 2067 u8 dummy; 2068 2069 while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) { 2070 rsp = cpc_readb(falcbase + F_REG(RSP, ch)); 2071 2072 if (gis & GIS_ISR0) { 2073 dummy = cpc_readb(falcbase + F_REG(FISR0, ch)); 2074 } 2075 if (gis & GIS_ISR1) { 2076 isr1 = cpc_readb(falcbase + F_REG(FISR1, ch)); 2077 if (isr1 & FISR1_XMB) { 2078 if ((pfalc->xmb_cause & 2) && 2079 pfalc->multiframe_mode) { 2080 if (cpc_readb (falcbase + F_REG(FRS0, ch)) & 2081 (FRS0_LOS | FRS0_AIS | FRS0_LFA)) { 2082 cpc_writeb(falcbase + F_REG(XSP, ch), 2083 cpc_readb(falcbase + F_REG(XSP, ch)) 2084 & ~XSP_AXS); 2085 } else { 2086 cpc_writeb(falcbase + F_REG(XSP, ch), 2087 cpc_readb(falcbase + F_REG(XSP, ch)) 2088 | XSP_AXS); 2089 } 2090 } 2091 pfalc->xmb_cause = 0; 2092 cpc_writeb(falcbase + F_REG(IMR1, ch), 2093 cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_XMB); 2094 } 2095 if (isr1 & FISR1_LLBSC) { 2096 falc_e1_loop_detection(card, ch, rsp); 2097 } 2098 } 2099 if (gis & GIS_ISR2) { 2100 isr2 = cpc_readb(falcbase + F_REG(FISR2, ch)); 2101 if (isr2 & FISR2_T400MS) { 2102 cpc_writeb(falcbase + F_REG(XSW, ch), 2103 cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XRA); 2104 } 2105 if (isr2 & FISR2_MFAR) { 2106 cpc_writeb(falcbase + F_REG(XSW, ch), 2107 cpc_readb(falcbase + F_REG(XSW, ch)) & ~XSW_XRA); 2108 } 2109 if (isr2 & (FISR2_FAR | FISR2_LFA | FISR2_AIS | FISR2_LOS)) { 2110 pfalc->xmb_cause |= 2; 2111 cpc_writeb(falcbase + F_REG(IMR1, ch), 2112 cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_XMB); 2113 } 2114 } 2115 if (gis & GIS_ISR3) { 2116 isr3 = cpc_readb(falcbase + F_REG(FISR3, ch)); 2117 if (isr3 & FISR3_SEC) { 2118 pfalc->sec++; 2119 falc_update_stats(card, ch); 2120 falc_check_status(card, ch, 2121 cpc_readb(falcbase + F_REG(FRS0, ch))); 2122 } 2123 if (isr3 & FISR3_ES) { 2124 pfalc->es++; 2125 } 2126 } 2127 } 2128} 2129 2130static void falc_intr(pc300_t * card) 2131{ 2132 int ch; 2133 2134 for (ch = 0; ch < card->hw.nchan; ch++) { 2135 pc300ch_t *chan = &card->chan[ch]; 2136 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 2137 2138 if (conf->media == IF_IFACE_T1) { 2139 falc_t1_intr(card, ch); 2140 } else { 2141 falc_e1_intr(card, ch); 2142 } 2143 } 2144} 2145 2146static irqreturn_t cpc_intr(int irq, void *dev_id) 2147{ 2148 pc300_t *card = dev_id; 2149 volatile u8 plx_status; 2150 2151 if (!card) { 2152#ifdef PC300_DEBUG_INTR 2153 printk("cpc_intr: spurious intr %d\n", irq); 2154#endif 2155 return IRQ_NONE; /* spurious intr */ 2156 } 2157 2158 if (!card->hw.rambase) { 2159#ifdef PC300_DEBUG_INTR 2160 printk("cpc_intr: spurious intr2 %d\n", irq); 2161#endif 2162 return IRQ_NONE; /* spurious intr */ 2163 } 2164 2165 switch (card->hw.type) { 2166 case PC300_RSV: 2167 case PC300_X21: 2168 sca_intr(card); 2169 break; 2170 2171 case PC300_TE: 2172 while ( (plx_status = (cpc_readb(card->hw.plxbase + card->hw.intctl_reg) & 2173 (PLX_9050_LINT1_STATUS | PLX_9050_LINT2_STATUS))) != 0) { 2174 if (plx_status & PLX_9050_LINT1_STATUS) { /* SCA Interrupt */ 2175 sca_intr(card); 2176 } 2177 if (plx_status & PLX_9050_LINT2_STATUS) { /* FALC Interrupt */ 2178 falc_intr(card); 2179 } 2180 } 2181 break; 2182 } 2183 return IRQ_HANDLED; 2184} 2185 2186static void cpc_sca_status(pc300_t * card, int ch) 2187{ 2188 u8 ilar; 2189 void __iomem *scabase = card->hw.scabase; 2190 unsigned long flags; 2191 2192 tx_dma_buf_check(card, ch); 2193 rx_dma_buf_check(card, ch); 2194 ilar = cpc_readb(scabase + ILAR); 2195 printk ("ILAR=0x%02x, WCRL=0x%02x, PCR=0x%02x, BTCR=0x%02x, BOLR=0x%02x\n", 2196 ilar, cpc_readb(scabase + WCRL), cpc_readb(scabase + PCR), 2197 cpc_readb(scabase + BTCR), cpc_readb(scabase + BOLR)); 2198 printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n", 2199 cpc_readl(scabase + DTX_REG(CDAL, ch)), 2200 cpc_readl(scabase + DTX_REG(EDAL, ch))); 2201 printk("RX_CDA=0x%08x, RX_EDA=0x%08x, BFL=0x%04x\n", 2202 cpc_readl(scabase + DRX_REG(CDAL, ch)), 2203 cpc_readl(scabase + DRX_REG(EDAL, ch)), 2204 cpc_readw(scabase + DRX_REG(BFLL, ch))); 2205 printk("DMER=0x%02x, DSR_TX=0x%02x, DSR_RX=0x%02x\n", 2206 cpc_readb(scabase + DMER), cpc_readb(scabase + DSR_TX(ch)), 2207 cpc_readb(scabase + DSR_RX(ch))); 2208 printk("DMR_TX=0x%02x, DMR_RX=0x%02x, DIR_TX=0x%02x, DIR_RX=0x%02x\n", 2209 cpc_readb(scabase + DMR_TX(ch)), cpc_readb(scabase + DMR_RX(ch)), 2210 cpc_readb(scabase + DIR_TX(ch)), 2211 cpc_readb(scabase + DIR_RX(ch))); 2212 printk("DCR_TX=0x%02x, DCR_RX=0x%02x, FCT_TX=0x%02x, FCT_RX=0x%02x\n", 2213 cpc_readb(scabase + DCR_TX(ch)), cpc_readb(scabase + DCR_RX(ch)), 2214 cpc_readb(scabase + FCT_TX(ch)), 2215 cpc_readb(scabase + FCT_RX(ch))); 2216 printk("MD0=0x%02x, MD1=0x%02x, MD2=0x%02x, MD3=0x%02x, IDL=0x%02x\n", 2217 cpc_readb(scabase + M_REG(MD0, ch)), 2218 cpc_readb(scabase + M_REG(MD1, ch)), 2219 cpc_readb(scabase + M_REG(MD2, ch)), 2220 cpc_readb(scabase + M_REG(MD3, ch)), 2221 cpc_readb(scabase + M_REG(IDL, ch))); 2222 printk("CMD=0x%02x, SA0=0x%02x, SA1=0x%02x, TFN=0x%02x, CTL=0x%02x\n", 2223 cpc_readb(scabase + M_REG(CMD, ch)), 2224 cpc_readb(scabase + M_REG(SA0, ch)), 2225 cpc_readb(scabase + M_REG(SA1, ch)), 2226 cpc_readb(scabase + M_REG(TFN, ch)), 2227 cpc_readb(scabase + M_REG(CTL, ch))); 2228 printk("ST0=0x%02x, ST1=0x%02x, ST2=0x%02x, ST3=0x%02x, ST4=0x%02x\n", 2229 cpc_readb(scabase + M_REG(ST0, ch)), 2230 cpc_readb(scabase + M_REG(ST1, ch)), 2231 cpc_readb(scabase + M_REG(ST2, ch)), 2232 cpc_readb(scabase + M_REG(ST3, ch)), 2233 cpc_readb(scabase + M_REG(ST4, ch))); 2234 printk ("CST0=0x%02x, CST1=0x%02x, CST2=0x%02x, CST3=0x%02x, FST=0x%02x\n", 2235 cpc_readb(scabase + M_REG(CST0, ch)), 2236 cpc_readb(scabase + M_REG(CST1, ch)), 2237 cpc_readb(scabase + M_REG(CST2, ch)), 2238 cpc_readb(scabase + M_REG(CST3, ch)), 2239 cpc_readb(scabase + M_REG(FST, ch))); 2240 printk("TRC0=0x%02x, TRC1=0x%02x, RRC=0x%02x, TBN=0x%02x, RBN=0x%02x\n", 2241 cpc_readb(scabase + M_REG(TRC0, ch)), 2242 cpc_readb(scabase + M_REG(TRC1, ch)), 2243 cpc_readb(scabase + M_REG(RRC, ch)), 2244 cpc_readb(scabase + M_REG(TBN, ch)), 2245 cpc_readb(scabase + M_REG(RBN, ch))); 2246 printk("TFS=0x%02x, TNR0=0x%02x, TNR1=0x%02x, RNR=0x%02x\n", 2247 cpc_readb(scabase + M_REG(TFS, ch)), 2248 cpc_readb(scabase + M_REG(TNR0, ch)), 2249 cpc_readb(scabase + M_REG(TNR1, ch)), 2250 cpc_readb(scabase + M_REG(RNR, ch))); 2251 printk("TCR=0x%02x, RCR=0x%02x, TNR1=0x%02x, RNR=0x%02x\n", 2252 cpc_readb(scabase + M_REG(TCR, ch)), 2253 cpc_readb(scabase + M_REG(RCR, ch)), 2254 cpc_readb(scabase + M_REG(TNR1, ch)), 2255 cpc_readb(scabase + M_REG(RNR, ch))); 2256 printk("TXS=0x%02x, RXS=0x%02x, EXS=0x%02x, TMCT=0x%02x, TMCR=0x%02x\n", 2257 cpc_readb(scabase + M_REG(TXS, ch)), 2258 cpc_readb(scabase + M_REG(RXS, ch)), 2259 cpc_readb(scabase + M_REG(EXS, ch)), 2260 cpc_readb(scabase + M_REG(TMCT, ch)), 2261 cpc_readb(scabase + M_REG(TMCR, ch))); 2262 printk("IE0=0x%02x, IE1=0x%02x, IE2=0x%02x, IE4=0x%02x, FIE=0x%02x\n", 2263 cpc_readb(scabase + M_REG(IE0, ch)), 2264 cpc_readb(scabase + M_REG(IE1, ch)), 2265 cpc_readb(scabase + M_REG(IE2, ch)), 2266 cpc_readb(scabase + M_REG(IE4, ch)), 2267 cpc_readb(scabase + M_REG(FIE, ch))); 2268 printk("IER0=0x%08x\n", cpc_readl(scabase + IER0)); 2269 2270 if (ilar != 0) { 2271 CPC_LOCK(card, flags); 2272 cpc_writeb(scabase + ILAR, ilar); 2273 cpc_writeb(scabase + DMER, 0x80); 2274 CPC_UNLOCK(card, flags); 2275 } 2276} 2277 2278static void cpc_falc_status(pc300_t * card, int ch) 2279{ 2280 pc300ch_t *chan = &card->chan[ch]; 2281 falc_t *pfalc = (falc_t *) & chan->falc; 2282 unsigned long flags; 2283 2284 CPC_LOCK(card, flags); 2285 printk("CH%d: %s %s %d channels\n", 2286 ch, (pfalc->sync ? "SYNC" : ""), (pfalc->active ? "ACTIVE" : ""), 2287 pfalc->num_channels); 2288 2289 printk(" pden=%d, los=%d, losr=%d, lfa=%d, farec=%d\n", 2290 pfalc->pden, pfalc->los, pfalc->losr, pfalc->lfa, pfalc->farec); 2291 printk(" lmfa=%d, ais=%d, sec=%d, es=%d, rai=%d\n", 2292 pfalc->lmfa, pfalc->ais, pfalc->sec, pfalc->es, pfalc->rai); 2293 printk(" bec=%d, fec=%d, cvc=%d, cec=%d, ebc=%d\n", 2294 pfalc->bec, pfalc->fec, pfalc->cvc, pfalc->cec, pfalc->ebc); 2295 2296 printk("\n"); 2297 printk(" STATUS: %s %s %s %s %s %s\n", 2298 (pfalc->red_alarm ? "RED" : ""), 2299 (pfalc->blue_alarm ? "BLU" : ""), 2300 (pfalc->yellow_alarm ? "YEL" : ""), 2301 (pfalc->loss_fa ? "LFA" : ""), 2302 (pfalc->loss_mfa ? "LMF" : ""), (pfalc->prbs ? "PRB" : "")); 2303 CPC_UNLOCK(card, flags); 2304} 2305 2306static int cpc_change_mtu(struct net_device *dev, int new_mtu) 2307{ 2308 if ((new_mtu < 128) || (new_mtu > PC300_DEF_MTU)) 2309 return -EINVAL; 2310 dev->mtu = new_mtu; 2311 return 0; 2312} 2313 2314static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2315{ 2316 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv; 2317 pc300ch_t *chan = (pc300ch_t *) d->chan; 2318 pc300_t *card = (pc300_t *) chan->card; 2319 pc300conf_t conf_aux; 2320 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 2321 int ch = chan->channel; 2322 void __user *arg = ifr->ifr_data; 2323 struct if_settings *settings = &ifr->ifr_settings; 2324 void __iomem *scabase = card->hw.scabase; 2325 2326 if (!capable(CAP_NET_ADMIN)) 2327 return -EPERM; 2328 2329 switch (cmd) { 2330 case SIOCGPC300CONF: 2331#ifdef CONFIG_PC300_MLPPP 2332 if (conf->proto != PC300_PROTO_MLPPP) { 2333 conf->proto = 0; 2334 } 2335#else 2336 conf->proto = 0; 2337#endif 2338 memcpy(&conf_aux.conf, conf, sizeof(pc300chconf_t)); 2339 memcpy(&conf_aux.hw, &card->hw, sizeof(pc300hw_t)); 2340 if (!arg || 2341 copy_to_user(arg, &conf_aux, sizeof(pc300conf_t))) 2342 return -EINVAL; 2343 return 0; 2344 case SIOCSPC300CONF: 2345 if (!capable(CAP_NET_ADMIN)) 2346 return -EPERM; 2347 if (!arg || 2348 copy_from_user(&conf_aux.conf, arg, sizeof(pc300chconf_t))) 2349 return -EINVAL; 2350 if (card->hw.cpld_id < 0x02 && 2351 conf_aux.conf.fr_mode == PC300_FR_UNFRAMED) { 2352 /* CPLD_ID < 0x02 doesn't support Unframed E1 */ 2353 return -EINVAL; 2354 } 2355#ifdef CONFIG_PC300_MLPPP 2356 if (conf_aux.conf.proto == PC300_PROTO_MLPPP) { 2357 if (conf->proto != PC300_PROTO_MLPPP) { 2358 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t)); 2359 cpc_tty_init(d); /* init TTY driver */ 2360 } 2361 } else { 2362 if (conf_aux.conf.proto == 0xffff) { 2363 if (conf->proto == PC300_PROTO_MLPPP){ 2364 /* ifdown interface */ 2365 cpc_close(dev); 2366 } 2367 } else { 2368 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t)); 2369 } 2370 } 2371#else 2372 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t)); 2373#endif 2374 return 0; 2375 case SIOCGPC300STATUS: 2376 cpc_sca_status(card, ch); 2377 return 0; 2378 case SIOCGPC300FALCSTATUS: 2379 cpc_falc_status(card, ch); 2380 return 0; 2381 2382 case SIOCGPC300UTILSTATS: 2383 { 2384 if (!arg) { /* clear statistics */ 2385 memset(&dev->stats, 0, sizeof(dev->stats)); 2386 if (card->hw.type == PC300_TE) { 2387 memset(&chan->falc, 0, sizeof(falc_t)); 2388 } 2389 } else { 2390 pc300stats_t pc300stats; 2391 2392 memset(&pc300stats, 0, sizeof(pc300stats_t)); 2393 pc300stats.hw_type = card->hw.type; 2394 pc300stats.line_on = card->chan[ch].d.line_on; 2395 pc300stats.line_off = card->chan[ch].d.line_off; 2396 memcpy(&pc300stats.gen_stats, &dev->stats, 2397 sizeof(dev->stats)); 2398 if (card->hw.type == PC300_TE) 2399 memcpy(&pc300stats.te_stats,&chan->falc,sizeof(falc_t)); 2400 if (copy_to_user(arg, &pc300stats, sizeof(pc300stats_t))) 2401 return -EFAULT; 2402 } 2403 return 0; 2404 } 2405 2406 case SIOCGPC300UTILSTATUS: 2407 { 2408 struct pc300status pc300status; 2409 2410 pc300status.hw_type = card->hw.type; 2411 if (card->hw.type == PC300_TE) { 2412 pc300status.te_status.sync = chan->falc.sync; 2413 pc300status.te_status.red_alarm = chan->falc.red_alarm; 2414 pc300status.te_status.blue_alarm = chan->falc.blue_alarm; 2415 pc300status.te_status.loss_fa = chan->falc.loss_fa; 2416 pc300status.te_status.yellow_alarm =chan->falc.yellow_alarm; 2417 pc300status.te_status.loss_mfa = chan->falc.loss_mfa; 2418 pc300status.te_status.prbs = chan->falc.prbs; 2419 } else { 2420 pc300status.gen_status.dcd = 2421 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_DCD); 2422 pc300status.gen_status.cts = 2423 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_CTS); 2424 pc300status.gen_status.rts = 2425 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_RTS); 2426 pc300status.gen_status.dtr = 2427 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_DTR); 2428 /* There is no DSR in HD64572 */ 2429 } 2430 if (!arg || 2431 copy_to_user(arg, &pc300status, sizeof(pc300status_t))) 2432 return -EINVAL; 2433 return 0; 2434 } 2435 2436 case SIOCSPC300TRACE: 2437 /* Sets/resets a trace_flag for the respective device */ 2438 if (!arg || copy_from_user(&d->trace_on, arg,sizeof(unsigned char))) 2439 return -EINVAL; 2440 return 0; 2441 2442 case SIOCSPC300LOOPBACK: 2443 { 2444 struct pc300loopback pc300loop; 2445 2446 /* TE boards only */ 2447 if (card->hw.type != PC300_TE) 2448 return -EINVAL; 2449 2450 if (!arg || 2451 copy_from_user(&pc300loop, arg, sizeof(pc300loopback_t))) 2452 return -EINVAL; 2453 switch (pc300loop.loop_type) { 2454 case PC300LOCLOOP: /* Turn the local loop on/off */ 2455 falc_local_loop(card, ch, pc300loop.loop_on); 2456 return 0; 2457 2458 case PC300REMLOOP: /* Turn the remote loop on/off */ 2459 falc_remote_loop(card, ch, pc300loop.loop_on); 2460 return 0; 2461 2462 case PC300PAYLOADLOOP: /* Turn the payload loop on/off */ 2463 falc_payload_loop(card, ch, pc300loop.loop_on); 2464 return 0; 2465 2466 case PC300GENLOOPUP: /* Generate loop UP */ 2467 if (pc300loop.loop_on) { 2468 falc_generate_loop_up_code (card, ch); 2469 } else { 2470 turn_off_xlu(card, ch); 2471 } 2472 return 0; 2473 2474 case PC300GENLOOPDOWN: /* Generate loop DOWN */ 2475 if (pc300loop.loop_on) { 2476 falc_generate_loop_down_code (card, ch); 2477 } else { 2478 turn_off_xld(card, ch); 2479 } 2480 return 0; 2481 2482 default: 2483 return -EINVAL; 2484 } 2485 } 2486 2487 case SIOCSPC300PATTERNTEST: 2488 /* Turn the pattern test on/off and show the errors counter */ 2489 { 2490 struct pc300patterntst pc300patrntst; 2491 2492 /* TE boards only */ 2493 if (card->hw.type != PC300_TE) 2494 return -EINVAL; 2495 2496 if (card->hw.cpld_id < 0x02) { 2497 /* CPLD_ID < 0x02 doesn't support pattern test */ 2498 return -EINVAL; 2499 } 2500 2501 if (!arg || 2502 copy_from_user(&pc300patrntst,arg,sizeof(pc300patterntst_t))) 2503 return -EINVAL; 2504 if (pc300patrntst.patrntst_on == 2) { 2505 if (chan->falc.prbs == 0) { 2506 falc_pattern_test(card, ch, 1); 2507 } 2508 pc300patrntst.num_errors = 2509 falc_pattern_test_error(card, ch); 2510 if (copy_to_user(arg, &pc300patrntst, 2511 sizeof(pc300patterntst_t))) 2512 return -EINVAL; 2513 } else { 2514 falc_pattern_test(card, ch, pc300patrntst.patrntst_on); 2515 } 2516 return 0; 2517 } 2518 2519 case SIOCWANDEV: 2520 switch (ifr->ifr_settings.type) { 2521 case IF_GET_IFACE: 2522 { 2523 const size_t size = sizeof(sync_serial_settings); 2524 ifr->ifr_settings.type = conf->media; 2525 if (ifr->ifr_settings.size < size) { 2526 /* data size wanted */ 2527 ifr->ifr_settings.size = size; 2528 return -ENOBUFS; 2529 } 2530 2531 if (copy_to_user(settings->ifs_ifsu.sync, 2532 &conf->phys_settings, size)) { 2533 return -EFAULT; 2534 } 2535 return 0; 2536 } 2537 2538 case IF_IFACE_V35: 2539 case IF_IFACE_V24: 2540 case IF_IFACE_X21: 2541 { 2542 const size_t size = sizeof(sync_serial_settings); 2543 2544 if (!capable(CAP_NET_ADMIN)) { 2545 return -EPERM; 2546 } 2547 /* incorrect data len? */ 2548 if (ifr->ifr_settings.size != size) { 2549 return -ENOBUFS; 2550 } 2551 2552 if (copy_from_user(&conf->phys_settings, 2553 settings->ifs_ifsu.sync, size)) { 2554 return -EFAULT; 2555 } 2556 2557 if (conf->phys_settings.loopback) { 2558 cpc_writeb(card->hw.scabase + M_REG(MD2, ch), 2559 cpc_readb(card->hw.scabase + M_REG(MD2, ch)) | 2560 MD2_LOOP_MIR); 2561 } 2562 conf->media = ifr->ifr_settings.type; 2563 return 0; 2564 } 2565 2566 case IF_IFACE_T1: 2567 case IF_IFACE_E1: 2568 { 2569 const size_t te_size = sizeof(te1_settings); 2570 const size_t size = sizeof(sync_serial_settings); 2571 2572 if (!capable(CAP_NET_ADMIN)) { 2573 return -EPERM; 2574 } 2575 2576 /* incorrect data len? */ 2577 if (ifr->ifr_settings.size != te_size) { 2578 return -ENOBUFS; 2579 } 2580 2581 if (copy_from_user(&conf->phys_settings, 2582 settings->ifs_ifsu.te1, size)) { 2583 return -EFAULT; 2584 }/* Ignoring HDLC slot_map for a while */ 2585 2586 if (conf->phys_settings.loopback) { 2587 cpc_writeb(card->hw.scabase + M_REG(MD2, ch), 2588 cpc_readb(card->hw.scabase + M_REG(MD2, ch)) | 2589 MD2_LOOP_MIR); 2590 } 2591 conf->media = ifr->ifr_settings.type; 2592 return 0; 2593 } 2594 default: 2595 return hdlc_ioctl(dev, ifr, cmd); 2596 } 2597 2598 default: 2599 return hdlc_ioctl(dev, ifr, cmd); 2600 } 2601} 2602 2603static int clock_rate_calc(u32 rate, u32 clock, int *br_io) 2604{ 2605 int br, tc; 2606 int br_pwr, error; 2607 2608 *br_io = 0; 2609 2610 if (rate == 0) 2611 return (0); 2612 2613 for (br = 0, br_pwr = 1; br <= 9; br++, br_pwr <<= 1) { 2614 if ((tc = clock / br_pwr / rate) <= 0xff) { 2615 *br_io = br; 2616 break; 2617 } 2618 } 2619 2620 if (tc <= 0xff) { 2621 error = ((rate - (clock / br_pwr / rate)) / rate) * 1000; 2622 /* Errors bigger than +/- 1% won't be tolerated */ 2623 if (error < -10 || error > 10) 2624 return (-1); 2625 else 2626 return (tc); 2627 } else { 2628 return (-1); 2629 } 2630} 2631 2632static int ch_config(pc300dev_t * d) 2633{ 2634 pc300ch_t *chan = (pc300ch_t *) d->chan; 2635 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; 2636 pc300_t *card = (pc300_t *) chan->card; 2637 void __iomem *scabase = card->hw.scabase; 2638 void __iomem *plxbase = card->hw.plxbase; 2639 int ch = chan->channel; 2640 u32 clkrate = chan->conf.phys_settings.clock_rate; 2641 u32 clktype = chan->conf.phys_settings.clock_type; 2642 u16 encoding = chan->conf.proto_settings.encoding; 2643 u16 parity = chan->conf.proto_settings.parity; 2644 u8 md0, md2; 2645 2646 /* Reset the channel */ 2647 cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST); 2648 2649 /* Configure the SCA registers */ 2650 switch (parity) { 2651 case PARITY_NONE: 2652 md0 = MD0_BIT_SYNC; 2653 break; 2654 case PARITY_CRC16_PR0: 2655 md0 = MD0_CRC16_0|MD0_CRCC0|MD0_BIT_SYNC; 2656 break; 2657 case PARITY_CRC16_PR1: 2658 md0 = MD0_CRC16_1|MD0_CRCC0|MD0_BIT_SYNC; 2659 break; 2660 case PARITY_CRC32_PR1_CCITT: 2661 md0 = MD0_CRC32|MD0_CRCC0|MD0_BIT_SYNC; 2662 break; 2663 case PARITY_CRC16_PR1_CCITT: 2664 default: 2665 md0 = MD0_CRC_CCITT|MD0_CRCC0|MD0_BIT_SYNC; 2666 break; 2667 } 2668 switch (encoding) { 2669 case ENCODING_NRZI: 2670 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZI; 2671 break; 2672 case ENCODING_FM_MARK: /* FM1 */ 2673 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM1; 2674 break; 2675 case ENCODING_FM_SPACE: /* FM0 */ 2676 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM0; 2677 break; 2678 case ENCODING_MANCHESTER: /* It's not working... */ 2679 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_MANCH; 2680 break; 2681 case ENCODING_NRZ: 2682 default: 2683 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZ; 2684 break; 2685 } 2686 cpc_writeb(scabase + M_REG(MD0, ch), md0); 2687 cpc_writeb(scabase + M_REG(MD1, ch), 0); 2688 cpc_writeb(scabase + M_REG(MD2, ch), md2); 2689 cpc_writeb(scabase + M_REG(IDL, ch), 0x7e); 2690 cpc_writeb(scabase + M_REG(CTL, ch), CTL_URSKP | CTL_IDLC); 2691 2692 /* Configure HW media */ 2693 switch (card->hw.type) { 2694 case PC300_RSV: 2695 if (conf->media == IF_IFACE_V35) { 2696 cpc_writel((plxbase + card->hw.gpioc_reg), 2697 cpc_readl(plxbase + card->hw.gpioc_reg) | PC300_CHMEDIA_MASK(ch)); 2698 } else { 2699 cpc_writel((plxbase + card->hw.gpioc_reg), 2700 cpc_readl(plxbase + card->hw.gpioc_reg) & ~PC300_CHMEDIA_MASK(ch)); 2701 } 2702 break; 2703 2704 case PC300_X21: 2705 break; 2706 2707 case PC300_TE: 2708 te_config(card, ch); 2709 break; 2710 } 2711 2712 switch (card->hw.type) { 2713 case PC300_RSV: 2714 case PC300_X21: 2715 if (clktype == CLOCK_INT || clktype == CLOCK_TXINT) { 2716 int tmc, br; 2717 2718 /* Calculate the clkrate parameters */ 2719 tmc = clock_rate_calc(clkrate, card->hw.clock, &br); 2720 if (tmc < 0) 2721 return -EIO; 2722 cpc_writeb(scabase + M_REG(TMCT, ch), tmc); 2723 cpc_writeb(scabase + M_REG(TXS, ch), 2724 (TXS_DTRXC | TXS_IBRG | br)); 2725 if (clktype == CLOCK_INT) { 2726 cpc_writeb(scabase + M_REG(TMCR, ch), tmc); 2727 cpc_writeb(scabase + M_REG(RXS, ch), 2728 (RXS_IBRG | br)); 2729 } else { 2730 cpc_writeb(scabase + M_REG(TMCR, ch), 1); 2731 cpc_writeb(scabase + M_REG(RXS, ch), 0); 2732 } 2733 if (card->hw.type == PC300_X21) { 2734 cpc_writeb(scabase + M_REG(GPO, ch), 1); 2735 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1); 2736 } else { 2737 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1); 2738 } 2739 } else { 2740 cpc_writeb(scabase + M_REG(TMCT, ch), 1); 2741 if (clktype == CLOCK_EXT) { 2742 cpc_writeb(scabase + M_REG(TXS, ch), 2743 TXS_DTRXC); 2744 } else { 2745 cpc_writeb(scabase + M_REG(TXS, ch), 2746 TXS_DTRXC|TXS_RCLK); 2747 } 2748 cpc_writeb(scabase + M_REG(TMCR, ch), 1); 2749 cpc_writeb(scabase + M_REG(RXS, ch), 0); 2750 if (card->hw.type == PC300_X21) { 2751 cpc_writeb(scabase + M_REG(GPO, ch), 0); 2752 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1); 2753 } else { 2754 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1); 2755 } 2756 } 2757 break; 2758 2759 case PC300_TE: 2760 /* SCA always receives clock from the FALC chip */ 2761 cpc_writeb(scabase + M_REG(TMCT, ch), 1); 2762 cpc_writeb(scabase + M_REG(TXS, ch), 0); 2763 cpc_writeb(scabase + M_REG(TMCR, ch), 1); 2764 cpc_writeb(scabase + M_REG(RXS, ch), 0); 2765 cpc_writeb(scabase + M_REG(EXS, ch), 0); 2766 break; 2767 } 2768 2769 /* Enable Interrupts */ 2770 cpc_writel(scabase + IER0, 2771 cpc_readl(scabase + IER0) | 2772 IR0_M(IR0_RXINTA, ch) | 2773 IR0_DRX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch) | 2774 IR0_DTX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch)); 2775 cpc_writeb(scabase + M_REG(IE0, ch), 2776 cpc_readl(scabase + M_REG(IE0, ch)) | IE0_RXINTA); 2777 cpc_writeb(scabase + M_REG(IE1, ch), 2778 cpc_readl(scabase + M_REG(IE1, ch)) | IE1_CDCD); 2779 2780 return 0; 2781} 2782 2783static int rx_config(pc300dev_t * d) 2784{ 2785 pc300ch_t *chan = (pc300ch_t *) d->chan; 2786 pc300_t *card = (pc300_t *) chan->card; 2787 void __iomem *scabase = card->hw.scabase; 2788 int ch = chan->channel; 2789 2790 cpc_writeb(scabase + DSR_RX(ch), 0); 2791 2792 /* General RX settings */ 2793 cpc_writeb(scabase + M_REG(RRC, ch), 0); 2794 cpc_writeb(scabase + M_REG(RNR, ch), 16); 2795 2796 /* Enable reception */ 2797 cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_CRC_INIT); 2798 cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_ENA); 2799 2800 /* Initialize DMA stuff */ 2801 chan->rx_first_bd = 0; 2802 chan->rx_last_bd = N_DMA_RX_BUF - 1; 2803 rx_dma_buf_init(card, ch); 2804 cpc_writeb(scabase + DCR_RX(ch), DCR_FCT_CLR); 2805 cpc_writeb(scabase + DMR_RX(ch), (DMR_TMOD | DMR_NF)); 2806 cpc_writeb(scabase + DIR_RX(ch), (DIR_EOM | DIR_BOF)); 2807 2808 /* Start DMA */ 2809 rx_dma_start(card, ch); 2810 2811 return 0; 2812} 2813 2814static int tx_config(pc300dev_t * d) 2815{ 2816 pc300ch_t *chan = (pc300ch_t *) d->chan; 2817 pc300_t *card = (pc300_t *) chan->card; 2818 void __iomem *scabase = card->hw.scabase; 2819 int ch = chan->channel; 2820 2821 cpc_writeb(scabase + DSR_TX(ch), 0); 2822 2823 /* General TX settings */ 2824 cpc_writeb(scabase + M_REG(TRC0, ch), 0); 2825 cpc_writeb(scabase + M_REG(TFS, ch), 32); 2826 cpc_writeb(scabase + M_REG(TNR0, ch), 20); 2827 cpc_writeb(scabase + M_REG(TNR1, ch), 48); 2828 cpc_writeb(scabase + M_REG(TCR, ch), 8); 2829 2830 /* Enable transmission */ 2831 cpc_writeb(scabase + M_REG(CMD, ch), CMD_TX_CRC_INIT); 2832 2833 /* Initialize DMA stuff */ 2834 chan->tx_first_bd = 0; 2835 chan->tx_next_bd = 0; 2836 tx_dma_buf_init(card, ch); 2837 cpc_writeb(scabase + DCR_TX(ch), DCR_FCT_CLR); 2838 cpc_writeb(scabase + DMR_TX(ch), (DMR_TMOD | DMR_NF)); 2839 cpc_writeb(scabase + DIR_TX(ch), (DIR_EOM | DIR_BOF | DIR_UDRF)); 2840 cpc_writel(scabase + DTX_REG(CDAL, ch), TX_BD_ADDR(ch, chan->tx_first_bd)); 2841 cpc_writel(scabase + DTX_REG(EDAL, ch), TX_BD_ADDR(ch, chan->tx_next_bd)); 2842 2843 return 0; 2844} 2845 2846static int cpc_attach(struct net_device *dev, unsigned short encoding, 2847 unsigned short parity) 2848{ 2849 pc300dev_t *d = (pc300dev_t *)dev_to_hdlc(dev)->priv; 2850 pc300ch_t *chan = (pc300ch_t *)d->chan; 2851 pc300_t *card = (pc300_t *)chan->card; 2852 pc300chconf_t *conf = (pc300chconf_t *)&chan->conf; 2853 2854 if (card->hw.type == PC300_TE) { 2855 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI) { 2856 return -EINVAL; 2857 } 2858 } else { 2859 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI && 2860 encoding != ENCODING_FM_MARK && encoding != ENCODING_FM_SPACE) { 2861 /* Driver doesn't support ENCODING_MANCHESTER yet */ 2862 return -EINVAL; 2863 } 2864 } 2865 2866 if (parity != PARITY_NONE && parity != PARITY_CRC16_PR0 && 2867 parity != PARITY_CRC16_PR1 && parity != PARITY_CRC32_PR1_CCITT && 2868 parity != PARITY_CRC16_PR1_CCITT) { 2869 return -EINVAL; 2870 } 2871 2872 conf->proto_settings.encoding = encoding; 2873 conf->proto_settings.parity = parity; 2874 return 0; 2875} 2876 2877static int cpc_opench(pc300dev_t * d) 2878{ 2879 pc300ch_t *chan = (pc300ch_t *) d->chan; 2880 pc300_t *card = (pc300_t *) chan->card; 2881 int ch = chan->channel, rc; 2882 void __iomem *scabase = card->hw.scabase; 2883 2884 rc = ch_config(d); 2885 if (rc) 2886 return rc; 2887 2888 rx_config(d); 2889 2890 tx_config(d); 2891 2892 /* Assert RTS and DTR */ 2893 cpc_writeb(scabase + M_REG(CTL, ch), 2894 cpc_readb(scabase + M_REG(CTL, ch)) & ~(CTL_RTS | CTL_DTR)); 2895 2896 return 0; 2897} 2898 2899static void cpc_closech(pc300dev_t * d) 2900{ 2901 pc300ch_t *chan = (pc300ch_t *) d->chan; 2902 pc300_t *card = (pc300_t *) chan->card; 2903 falc_t *pfalc = (falc_t *) & chan->falc; 2904 int ch = chan->channel; 2905 2906 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_CH_RST); 2907 rx_dma_stop(card, ch); 2908 tx_dma_stop(card, ch); 2909 2910 if (card->hw.type == PC300_TE) { 2911 memset(pfalc, 0, sizeof(falc_t)); 2912 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2, 2913 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) & 2914 ~((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK | 2915 CPLD_REG2_FALC_LED2) << (2 * ch))); 2916 /* Reset the FALC chip */ 2917 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1, 2918 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) | 2919 (CPLD_REG1_FALC_RESET << (2 * ch))); 2920 udelay(10000); 2921 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1, 2922 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) & 2923 ~(CPLD_REG1_FALC_RESET << (2 * ch))); 2924 } 2925} 2926 2927int cpc_open(struct net_device *dev) 2928{ 2929 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv; 2930 struct ifreq ifr; 2931 int result; 2932 2933#ifdef PC300_DEBUG_OTHER 2934 printk("pc300: cpc_open"); 2935#endif 2936 2937 result = hdlc_open(dev); 2938 2939 if (result) 2940 return result; 2941 2942 sprintf(ifr.ifr_name, "%s", dev->name); 2943 result = cpc_opench(d); 2944 if (result) 2945 goto err_out; 2946 2947 netif_start_queue(dev); 2948 return 0; 2949 2950err_out: 2951 hdlc_close(dev); 2952 return result; 2953} 2954 2955static int cpc_close(struct net_device *dev) 2956{ 2957 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv; 2958 pc300ch_t *chan = (pc300ch_t *) d->chan; 2959 pc300_t *card = (pc300_t *) chan->card; 2960 unsigned long flags; 2961 2962#ifdef PC300_DEBUG_OTHER 2963 printk("pc300: cpc_close"); 2964#endif 2965 2966 netif_stop_queue(dev); 2967 2968 CPC_LOCK(card, flags); 2969 cpc_closech(d); 2970 CPC_UNLOCK(card, flags); 2971 2972 hdlc_close(dev); 2973 2974#ifdef CONFIG_PC300_MLPPP 2975 if (chan->conf.proto == PC300_PROTO_MLPPP) { 2976 cpc_tty_unregister_service(d); 2977 chan->conf.proto = 0xffff; 2978 } 2979#endif 2980 2981 return 0; 2982} 2983 2984static u32 detect_ram(pc300_t * card) 2985{ 2986 u32 i; 2987 u8 data; 2988 void __iomem *rambase = card->hw.rambase; 2989 2990 card->hw.ramsize = PC300_RAMSIZE; 2991 /* Let's find out how much RAM is present on this board */ 2992 for (i = 0; i < card->hw.ramsize; i++) { 2993 data = (u8)(i & 0xff); 2994 cpc_writeb(rambase + i, data); 2995 if (cpc_readb(rambase + i) != data) { 2996 break; 2997 } 2998 } 2999 return (i); 3000} 3001 3002static void plx_init(pc300_t * card) 3003{ 3004 struct RUNTIME_9050 __iomem *plx_ctl = card->hw.plxbase; 3005 3006 /* Reset PLX */ 3007 cpc_writel(&plx_ctl->init_ctrl, 3008 cpc_readl(&plx_ctl->init_ctrl) | 0x40000000); 3009 udelay(10000L); 3010 cpc_writel(&plx_ctl->init_ctrl, 3011 cpc_readl(&plx_ctl->init_ctrl) & ~0x40000000); 3012 3013 /* Reload Config. Registers from EEPROM */ 3014 cpc_writel(&plx_ctl->init_ctrl, 3015 cpc_readl(&plx_ctl->init_ctrl) | 0x20000000); 3016 udelay(10000L); 3017 cpc_writel(&plx_ctl->init_ctrl, 3018 cpc_readl(&plx_ctl->init_ctrl) & ~0x20000000); 3019 3020} 3021 3022static inline void show_version(void) 3023{ 3024 char *rcsvers, *rcsdate, *tmp; 3025 3026 rcsvers = strchr(rcsid, ' '); 3027 rcsvers++; 3028 tmp = strchr(rcsvers, ' '); 3029 *tmp++ = '\0'; 3030 rcsdate = strchr(tmp, ' '); 3031 rcsdate++; 3032 tmp = strrchr(rcsdate, ' '); 3033 *tmp = '\0'; 3034 printk(KERN_INFO "Cyclades-PC300 driver %s %s (built %s %s)\n", 3035 rcsvers, rcsdate, __DATE__, __TIME__); 3036} /* show_version */ 3037 3038static const struct net_device_ops cpc_netdev_ops = { 3039 .ndo_open = cpc_open, 3040 .ndo_stop = cpc_close, 3041 .ndo_tx_timeout = cpc_tx_timeout, 3042 .ndo_set_mac_address = NULL, 3043 .ndo_change_mtu = cpc_change_mtu, 3044 .ndo_do_ioctl = cpc_ioctl, 3045 .ndo_validate_addr = eth_validate_addr, 3046}; 3047 3048static void cpc_init_card(pc300_t * card) 3049{ 3050 int i, devcount = 0; 3051 static int board_nbr = 1; 3052 3053 /* Enable interrupts on the PCI bridge */ 3054 plx_init(card); 3055 cpc_writew(card->hw.plxbase + card->hw.intctl_reg, 3056 cpc_readw(card->hw.plxbase + card->hw.intctl_reg) | 0x0040); 3057 3058#ifdef USE_PCI_CLOCK 3059 /* Set board clock to PCI clock */ 3060 cpc_writel(card->hw.plxbase + card->hw.gpioc_reg, 3061 cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) | 0x00000004UL); 3062 card->hw.clock = PC300_PCI_CLOCK; 3063#else 3064 /* Set board clock to internal oscillator clock */ 3065 cpc_writel(card->hw.plxbase + card->hw.gpioc_reg, 3066 cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & ~0x00000004UL); 3067 card->hw.clock = PC300_OSC_CLOCK; 3068#endif 3069 3070 /* Detect actual on-board RAM size */ 3071 card->hw.ramsize = detect_ram(card); 3072 3073 /* Set Global SCA-II registers */ 3074 cpc_writeb(card->hw.scabase + PCR, PCR_PR2); 3075 cpc_writeb(card->hw.scabase + BTCR, 0x10); 3076 cpc_writeb(card->hw.scabase + WCRL, 0); 3077 cpc_writeb(card->hw.scabase + DMER, 0x80); 3078 3079 if (card->hw.type == PC300_TE) { 3080 u8 reg1; 3081 3082 /* Check CPLD version */ 3083 reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1); 3084 cpc_writeb(card->hw.falcbase + CPLD_REG1, (reg1 + 0x5a)); 3085 if (cpc_readb(card->hw.falcbase + CPLD_REG1) == reg1) { 3086 /* New CPLD */ 3087 card->hw.cpld_id = cpc_readb(card->hw.falcbase + CPLD_ID_REG); 3088 card->hw.cpld_reg1 = CPLD_V2_REG1; 3089 card->hw.cpld_reg2 = CPLD_V2_REG2; 3090 } else { 3091 /* old CPLD */ 3092 card->hw.cpld_id = 0; 3093 card->hw.cpld_reg1 = CPLD_REG1; 3094 card->hw.cpld_reg2 = CPLD_REG2; 3095 cpc_writeb(card->hw.falcbase + CPLD_REG1, reg1); 3096 } 3097 3098 /* Enable the board's global clock */ 3099 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1, 3100 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) | 3101 CPLD_REG1_GLOBAL_CLK); 3102 3103 } 3104 3105 for (i = 0; i < card->hw.nchan; i++) { 3106 pc300ch_t *chan = &card->chan[i]; 3107 pc300dev_t *d = &chan->d; 3108 hdlc_device *hdlc; 3109 struct net_device *dev; 3110 3111 chan->card = card; 3112 chan->channel = i; 3113 chan->conf.phys_settings.clock_rate = 0; 3114 chan->conf.phys_settings.clock_type = CLOCK_EXT; 3115 chan->conf.proto_settings.encoding = ENCODING_NRZ; 3116 chan->conf.proto_settings.parity = PARITY_CRC16_PR1_CCITT; 3117 switch (card->hw.type) { 3118 case PC300_TE: 3119 chan->conf.media = IF_IFACE_T1; 3120 chan->conf.lcode = PC300_LC_B8ZS; 3121 chan->conf.fr_mode = PC300_FR_ESF; 3122 chan->conf.lbo = PC300_LBO_0_DB; 3123 chan->conf.rx_sens = PC300_RX_SENS_SH; 3124 chan->conf.tslot_bitmap = 0xffffffffUL; 3125 break; 3126 3127 case PC300_X21: 3128 chan->conf.media = IF_IFACE_X21; 3129 break; 3130 3131 case PC300_RSV: 3132 default: 3133 chan->conf.media = IF_IFACE_V35; 3134 break; 3135 } 3136 chan->conf.proto = IF_PROTO_PPP; 3137 chan->tx_first_bd = 0; 3138 chan->tx_next_bd = 0; 3139 chan->rx_first_bd = 0; 3140 chan->rx_last_bd = N_DMA_RX_BUF - 1; 3141 chan->nfree_tx_bd = N_DMA_TX_BUF; 3142 3143 d->chan = chan; 3144 d->trace_on = 0; 3145 d->line_on = 0; 3146 d->line_off = 0; 3147 3148 dev = alloc_hdlcdev(d); 3149 if (dev == NULL) 3150 continue; 3151 3152 hdlc = dev_to_hdlc(dev); 3153 hdlc->xmit = cpc_queue_xmit; 3154 hdlc->attach = cpc_attach; 3155 d->dev = dev; 3156 dev->mem_start = card->hw.ramphys; 3157 dev->mem_end = card->hw.ramphys + card->hw.ramsize - 1; 3158 dev->irq = card->hw.irq; 3159 dev->tx_queue_len = PC300_TX_QUEUE_LEN; 3160 dev->mtu = PC300_DEF_MTU; 3161 3162 dev->netdev_ops = &cpc_netdev_ops; 3163 dev->watchdog_timeo = PC300_TX_TIMEOUT; 3164 3165 if (register_hdlc_device(dev) == 0) { 3166 printk("%s: Cyclades-PC300/", dev->name); 3167 switch (card->hw.type) { 3168 case PC300_TE: 3169 if (card->hw.bus == PC300_PMC) { 3170 printk("TE-M"); 3171 } else { 3172 printk("TE "); 3173 } 3174 break; 3175 3176 case PC300_X21: 3177 printk("X21 "); 3178 break; 3179 3180 case PC300_RSV: 3181 default: 3182 printk("RSV "); 3183 break; 3184 } 3185 printk (" #%d, %dKB of RAM at 0x%08x, IRQ%d, channel %d.\n", 3186 board_nbr, card->hw.ramsize / 1024, 3187 card->hw.ramphys, card->hw.irq, i + 1); 3188 devcount++; 3189 } else { 3190 printk ("Dev%d on card(0x%08x): unable to allocate i/f name.\n", 3191 i + 1, card->hw.ramphys); 3192 free_netdev(dev); 3193 continue; 3194 } 3195 } 3196 spin_lock_init(&card->card_lock); 3197 3198 board_nbr++; 3199} 3200 3201static int __devinit 3202cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 3203{ 3204 static int first_time = 1; 3205 int err, eeprom_outdated = 0; 3206 u16 device_id; 3207 pc300_t *card; 3208 3209 if (first_time) { 3210 first_time = 0; 3211 show_version(); 3212#ifdef CONFIG_PC300_MLPPP 3213 cpc_tty_reset_var(); 3214#endif 3215 } 3216 3217 if ((err = pci_enable_device(pdev)) < 0) 3218 return err; 3219 3220 card = kzalloc(sizeof(pc300_t), GFP_KERNEL); 3221 if (card == NULL) { 3222 printk("PC300 found at RAM 0x%016llx, " 3223 "but could not allocate card structure.\n", 3224 (unsigned long long)pci_resource_start(pdev, 3)); 3225 err = -ENOMEM; 3226 goto err_disable_dev; 3227 } 3228 3229 err = -ENODEV; 3230 3231 /* read PCI configuration area */ 3232 device_id = ent->device; 3233 card->hw.irq = pdev->irq; 3234 card->hw.iophys = pci_resource_start(pdev, 1); 3235 card->hw.iosize = pci_resource_len(pdev, 1); 3236 card->hw.scaphys = pci_resource_start(pdev, 2); 3237 card->hw.scasize = pci_resource_len(pdev, 2); 3238 card->hw.ramphys = pci_resource_start(pdev, 3); 3239 card->hw.alloc_ramsize = pci_resource_len(pdev, 3); 3240 card->hw.falcphys = pci_resource_start(pdev, 4); 3241 card->hw.falcsize = pci_resource_len(pdev, 4); 3242 card->hw.plxphys = pci_resource_start(pdev, 5); 3243 card->hw.plxsize = pci_resource_len(pdev, 5); 3244 3245 switch (device_id) { 3246 case PCI_DEVICE_ID_PC300_RX_1: 3247 case PCI_DEVICE_ID_PC300_TE_1: 3248 case PCI_DEVICE_ID_PC300_TE_M_1: 3249 card->hw.nchan = 1; 3250 break; 3251 3252 case PCI_DEVICE_ID_PC300_RX_2: 3253 case PCI_DEVICE_ID_PC300_TE_2: 3254 case PCI_DEVICE_ID_PC300_TE_M_2: 3255 default: 3256 card->hw.nchan = PC300_MAXCHAN; 3257 break; 3258 } 3259#ifdef PC300_DEBUG_PCI 3260 printk("cpc (bus=0x0%x,pci_id=0x%x,", pdev->bus->number, pdev->devfn); 3261 printk("rev_id=%d) IRQ%d\n", pdev->revision, card->hw.irq); 3262 printk("cpc:found ramaddr=0x%08lx plxaddr=0x%08lx " 3263 "ctladdr=0x%08lx falcaddr=0x%08lx\n", 3264 card->hw.ramphys, card->hw.plxphys, card->hw.scaphys, 3265 card->hw.falcphys); 3266#endif 3267 /* Although we don't use this I/O region, we should 3268 * request it from the kernel anyway, to avoid problems 3269 * with other drivers accessing it. */ 3270 if (!request_region(card->hw.iophys, card->hw.iosize, "PLX Registers")) { 3271 /* In case we can't allocate it, warn user */ 3272 printk("WARNING: couldn't allocate I/O region for PC300 board " 3273 "at 0x%08x!\n", card->hw.ramphys); 3274 } 3275 3276 if (card->hw.plxphys) { 3277 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, card->hw.plxphys); 3278 } else { 3279 eeprom_outdated = 1; 3280 card->hw.plxphys = pci_resource_start(pdev, 0); 3281 card->hw.plxsize = pci_resource_len(pdev, 0); 3282 } 3283 3284 if (!request_mem_region(card->hw.plxphys, card->hw.plxsize, 3285 "PLX Registers")) { 3286 printk("PC300 found at RAM 0x%08x, " 3287 "but could not allocate PLX mem region.\n", 3288 card->hw.ramphys); 3289 goto err_release_io; 3290 } 3291 if (!request_mem_region(card->hw.ramphys, card->hw.alloc_ramsize, 3292 "On-board RAM")) { 3293 printk("PC300 found at RAM 0x%08x, " 3294 "but could not allocate RAM mem region.\n", 3295 card->hw.ramphys); 3296 goto err_release_plx; 3297 } 3298 if (!request_mem_region(card->hw.scaphys, card->hw.scasize, 3299 "SCA-II Registers")) { 3300 printk("PC300 found at RAM 0x%08x, " 3301 "but could not allocate SCA mem region.\n", 3302 card->hw.ramphys); 3303 goto err_release_ram; 3304 } 3305 3306 card->hw.plxbase = ioremap(card->hw.plxphys, card->hw.plxsize); 3307 card->hw.rambase = ioremap(card->hw.ramphys, card->hw.alloc_ramsize); 3308 card->hw.scabase = ioremap(card->hw.scaphys, card->hw.scasize); 3309 switch (device_id) { 3310 case PCI_DEVICE_ID_PC300_TE_1: 3311 case PCI_DEVICE_ID_PC300_TE_2: 3312 case PCI_DEVICE_ID_PC300_TE_M_1: 3313 case PCI_DEVICE_ID_PC300_TE_M_2: 3314 request_mem_region(card->hw.falcphys, card->hw.falcsize, 3315 "FALC Registers"); 3316 card->hw.falcbase = ioremap(card->hw.falcphys, card->hw.falcsize); 3317 break; 3318 3319 case PCI_DEVICE_ID_PC300_RX_1: 3320 case PCI_DEVICE_ID_PC300_RX_2: 3321 default: 3322 card->hw.falcbase = NULL; 3323 break; 3324 } 3325 3326#ifdef PC300_DEBUG_PCI 3327 printk("cpc: relocate ramaddr=0x%08lx plxaddr=0x%08lx " 3328 "ctladdr=0x%08lx falcaddr=0x%08lx\n", 3329 card->hw.rambase, card->hw.plxbase, card->hw.scabase, 3330 card->hw.falcbase); 3331#endif 3332 3333 /* Set PCI drv pointer to the card structure */ 3334 pci_set_drvdata(pdev, card); 3335 3336 /* Set board type */ 3337 switch (device_id) { 3338 case PCI_DEVICE_ID_PC300_TE_1: 3339 case PCI_DEVICE_ID_PC300_TE_2: 3340 case PCI_DEVICE_ID_PC300_TE_M_1: 3341 case PCI_DEVICE_ID_PC300_TE_M_2: 3342 card->hw.type = PC300_TE; 3343 3344 if ((device_id == PCI_DEVICE_ID_PC300_TE_M_1) || 3345 (device_id == PCI_DEVICE_ID_PC300_TE_M_2)) { 3346 card->hw.bus = PC300_PMC; 3347 /* Set PLX register offsets */ 3348 card->hw.gpioc_reg = 0x54; 3349 card->hw.intctl_reg = 0x4c; 3350 } else { 3351 card->hw.bus = PC300_PCI; 3352 /* Set PLX register offsets */ 3353 card->hw.gpioc_reg = 0x50; 3354 card->hw.intctl_reg = 0x4c; 3355 } 3356 break; 3357 3358 case PCI_DEVICE_ID_PC300_RX_1: 3359 case PCI_DEVICE_ID_PC300_RX_2: 3360 default: 3361 card->hw.bus = PC300_PCI; 3362 /* Set PLX register offsets */ 3363 card->hw.gpioc_reg = 0x50; 3364 card->hw.intctl_reg = 0x4c; 3365 3366 if ((cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & PC300_CTYPE_MASK)) { 3367 card->hw.type = PC300_X21; 3368 } else { 3369 card->hw.type = PC300_RSV; 3370 } 3371 break; 3372 } 3373 3374 /* Allocate IRQ */ 3375 if (request_irq(card->hw.irq, cpc_intr, IRQF_SHARED, "Cyclades-PC300", card)) { 3376 printk ("PC300 found at RAM 0x%08x, but could not allocate IRQ%d.\n", 3377 card->hw.ramphys, card->hw.irq); 3378 goto err_io_unmap; 3379 } 3380 3381 cpc_init_card(card); 3382 3383 if (eeprom_outdated) 3384 printk("WARNING: PC300 with outdated EEPROM.\n"); 3385 return 0; 3386 3387err_io_unmap: 3388 iounmap(card->hw.plxbase); 3389 iounmap(card->hw.scabase); 3390 iounmap(card->hw.rambase); 3391 if (card->hw.type == PC300_TE) { 3392 iounmap(card->hw.falcbase); 3393 release_mem_region(card->hw.falcphys, card->hw.falcsize); 3394 } 3395 release_mem_region(card->hw.scaphys, card->hw.scasize); 3396err_release_ram: 3397 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize); 3398err_release_plx: 3399 release_mem_region(card->hw.plxphys, card->hw.plxsize); 3400err_release_io: 3401 release_region(card->hw.iophys, card->hw.iosize); 3402 kfree(card); 3403err_disable_dev: 3404 pci_disable_device(pdev); 3405 return err; 3406} 3407 3408static void __devexit cpc_remove_one(struct pci_dev *pdev) 3409{ 3410 pc300_t *card = pci_get_drvdata(pdev); 3411 3412 if (card->hw.rambase) { 3413 int i; 3414 3415 /* Disable interrupts on the PCI bridge */ 3416 cpc_writew(card->hw.plxbase + card->hw.intctl_reg, 3417 cpc_readw(card->hw.plxbase + card->hw.intctl_reg) & ~(0x0040)); 3418 3419 for (i = 0; i < card->hw.nchan; i++) { 3420 unregister_hdlc_device(card->chan[i].d.dev); 3421 } 3422 iounmap(card->hw.plxbase); 3423 iounmap(card->hw.scabase); 3424 iounmap(card->hw.rambase); 3425 release_mem_region(card->hw.plxphys, card->hw.plxsize); 3426 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize); 3427 release_mem_region(card->hw.scaphys, card->hw.scasize); 3428 release_region(card->hw.iophys, card->hw.iosize); 3429 if (card->hw.type == PC300_TE) { 3430 iounmap(card->hw.falcbase); 3431 release_mem_region(card->hw.falcphys, card->hw.falcsize); 3432 } 3433 for (i = 0; i < card->hw.nchan; i++) 3434 if (card->chan[i].d.dev) 3435 free_netdev(card->chan[i].d.dev); 3436 if (card->hw.irq) 3437 free_irq(card->hw.irq, card); 3438 kfree(card); 3439 pci_disable_device(pdev); 3440 } 3441} 3442 3443static struct pci_driver cpc_driver = { 3444 .name = "pc300", 3445 .id_table = cpc_pci_dev_id, 3446 .probe = cpc_init_one, 3447 .remove = __devexit_p(cpc_remove_one), 3448}; 3449 3450static int __init cpc_init(void) 3451{ 3452 return pci_register_driver(&cpc_driver); 3453} 3454 3455static void __exit cpc_cleanup_module(void) 3456{ 3457 pci_unregister_driver(&cpc_driver); 3458} 3459 3460module_init(cpc_init); 3461module_exit(cpc_cleanup_module); 3462 3463MODULE_DESCRIPTION("Cyclades-PC300 cards driver"); 3464MODULE_AUTHOR( "Author: Ivan Passos <ivan@cyclades.com>\r\n" 3465 "Maintainer: PC300 Maintainer <pc300@cyclades.com"); 3466MODULE_LICENSE("GPL"); 3467