1/* 2 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for 3 * CPU modes 0 & 2. 4 * 5 * Author: Ivan Passos <ivan@cyclades.com> 6 * 7 * Copyright: (c) 2000-2001 Cyclades Corp. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * $Log: hd64572.h,v $ 15 * Revision 3.1 2001/06/15 12:41:10 regina 16 * upping major version number 17 * 18 * Revision 1.1.1.1 2001/06/13 20:24:49 daniela 19 * PC300 initial CVS version (3.4.0-pre1) 20 * 21 * Revision 1.0 2000/01/25 ivan 22 * Initial version. 23 * 24 */ 25 26#ifndef __HD64572_H 27#define __HD64572_H 28 29/* Illegal Access Register */ 30#define ILAR 0x00 31 32/* Wait Controller Registers */ 33#define PABR0L 0x20 /* Physical Addr Boundary Register 0 L */ 34#define PABR0H 0x21 /* Physical Addr Boundary Register 0 H */ 35#define PABR1L 0x22 /* Physical Addr Boundary Register 1 L */ 36#define PABR1H 0x23 /* Physical Addr Boundary Register 1 H */ 37#define WCRL 0x24 /* Wait Control Register L */ 38#define WCRM 0x25 /* Wait Control Register M */ 39#define WCRH 0x26 /* Wait Control Register H */ 40 41/* Interrupt Registers */ 42#define IVR 0x60 /* Interrupt Vector Register */ 43#define IMVR 0x64 /* Interrupt Modified Vector Register */ 44#define ITCR 0x68 /* Interrupt Control Register */ 45#define ISR0 0x6c /* Interrupt Status Register 0 */ 46#define ISR1 0x70 /* Interrupt Status Register 1 */ 47#define IER0 0x74 /* Interrupt Enable Register 0 */ 48#define IER1 0x78 /* Interrupt Enable Register 1 */ 49 50/* Register Access Macros (chan is 0 or 1 in _any_ case) */ 51#define M_REG(reg, chan) (reg + 0x80*chan) /* MSCI */ 52#define DRX_REG(reg, chan) (reg + 0x40*chan) /* DMA Rx */ 53#define DTX_REG(reg, chan) (reg + 0x20*(2*chan + 1)) /* DMA Tx */ 54#define TRX_REG(reg, chan) (reg + 0x20*chan) /* Timer Rx */ 55#define TTX_REG(reg, chan) (reg + 0x10*(2*chan + 1)) /* Timer Tx */ 56#define ST_REG(reg, chan) (reg + 0x80*chan) /* Status Cnt */ 57#define IR0_DRX(val, chan) ((val)<<(8*(chan))) /* Int DMA Rx */ 58#define IR0_DTX(val, chan) ((val)<<(4*(2*chan + 1))) /* Int DMA Tx */ 59#define IR0_M(val, chan) ((val)<<(8*(chan))) /* Int MSCI */ 60 61/* MSCI Channel Registers */ 62#define MSCI0_OFFSET 0x00 63#define MSCI1_OFFSET 0x80 64 65#define MD0 0x138 /* Mode reg 0 */ 66#define MD1 0x139 /* Mode reg 1 */ 67#define MD2 0x13a /* Mode reg 2 */ 68#define MD3 0x13b /* Mode reg 3 */ 69#define CTL 0x130 /* Control reg */ 70#define RXS 0x13c /* RX clock source */ 71#define TXS 0x13d /* TX clock source */ 72#define EXS 0x13e /* External clock input selection */ 73#define TMCT 0x144 /* Time constant (Tx) */ 74#define TMCR 0x145 /* Time constant (Rx) */ 75#define CMD 0x128 /* Command reg */ 76#define ST0 0x118 /* Status reg 0 */ 77#define ST1 0x119 /* Status reg 1 */ 78#define ST2 0x11a /* Status reg 2 */ 79#define ST3 0x11b /* Status reg 3 */ 80#define ST4 0x11c /* Status reg 4 */ 81#define FST 0x11d /* frame Status reg */ 82#define IE0 0x120 /* Interrupt enable reg 0 */ 83#define IE1 0x121 /* Interrupt enable reg 1 */ 84#define IE2 0x122 /* Interrupt enable reg 2 */ 85#define IE4 0x124 /* Interrupt enable reg 4 */ 86#define FIE 0x125 /* Frame Interrupt enable reg */ 87#define SA0 0x140 /* Syn Address reg 0 */ 88#define SA1 0x141 /* Syn Address reg 1 */ 89#define IDL 0x142 /* Idle register */ 90#define TRBL 0x100 /* TX/RX buffer reg L */ 91#define TRBK 0x101 /* TX/RX buffer reg K */ 92#define TRBJ 0x102 /* TX/RX buffer reg J */ 93#define TRBH 0x103 /* TX/RX buffer reg H */ 94#define TRC0 0x148 /* TX Ready control reg 0 */ 95#define TRC1 0x149 /* TX Ready control reg 1 */ 96#define RRC 0x14a /* RX Ready control reg */ 97#define CST0 0x108 /* Current Status Register 0 */ 98#define CST1 0x109 /* Current Status Register 1 */ 99#define CST2 0x10a /* Current Status Register 2 */ 100#define CST3 0x10b /* Current Status Register 3 */ 101#define GPO 0x131 /* General Purpose Output Pin Ctl Reg */ 102#define TFS 0x14b /* Tx Start Threshold Ctl Reg */ 103#define TFN 0x143 /* Inter-transmit-frame Time Fill Ctl Reg */ 104#define TBN 0x110 /* Tx Buffer Number Reg */ 105#define RBN 0x111 /* Rx Buffer Number Reg */ 106#define TNR0 0x150 /* Tx DMA Request Ctl Reg 0 */ 107#define TNR1 0x151 /* Tx DMA Request Ctl Reg 1 */ 108#define TCR 0x152 /* Tx DMA Critical Request Reg */ 109#define RNR 0x154 /* Rx DMA Request Ctl Reg */ 110#define RCR 0x156 /* Rx DMA Critical Request Reg */ 111 112/* Timer Registers */ 113#define TIMER0RX_OFFSET 0x00 114#define TIMER0TX_OFFSET 0x10 115#define TIMER1RX_OFFSET 0x20 116#define TIMER1TX_OFFSET 0x30 117 118#define TCNTL 0x200 /* Timer Upcounter L */ 119#define TCNTH 0x201 /* Timer Upcounter H */ 120#define TCONRL 0x204 /* Timer Constant Register L */ 121#define TCONRH 0x205 /* Timer Constant Register H */ 122#define TCSR 0x206 /* Timer Control/Status Register */ 123#define TEPR 0x207 /* Timer Expand Prescale Register */ 124 125/* DMA registers */ 126#define PCR 0x40 /* DMA priority control reg */ 127#define DRR 0x44 /* DMA reset reg */ 128#define DMER 0x07 /* DMA Master Enable reg */ 129#define BTCR 0x08 /* Burst Tx Ctl Reg */ 130#define BOLR 0x0c /* Back-off Length Reg */ 131#define DSR_RX(chan) (0x48 + 2*chan) /* DMA Status Reg (Rx) */ 132#define DSR_TX(chan) (0x49 + 2*chan) /* DMA Status Reg (Tx) */ 133#define DIR_RX(chan) (0x4c + 2*chan) /* DMA Interrupt Enable Reg (Rx) */ 134#define DIR_TX(chan) (0x4d + 2*chan) /* DMA Interrupt Enable Reg (Tx) */ 135#define FCT_RX(chan) (0x50 + 2*chan) /* Frame End Interrupt Counter (Rx) */ 136#define FCT_TX(chan) (0x51 + 2*chan) /* Frame End Interrupt Counter (Tx) */ 137#define DMR_RX(chan) (0x54 + 2*chan) /* DMA Mode Reg (Rx) */ 138#define DMR_TX(chan) (0x55 + 2*chan) /* DMA Mode Reg (Tx) */ 139#define DCR_RX(chan) (0x58 + 2*chan) /* DMA Command Reg (Rx) */ 140#define DCR_TX(chan) (0x59 + 2*chan) /* DMA Command Reg (Tx) */ 141 142/* DMA Channel Registers */ 143#define DMAC0RX_OFFSET 0x00 144#define DMAC0TX_OFFSET 0x20 145#define DMAC1RX_OFFSET 0x40 146#define DMAC1TX_OFFSET 0x60 147 148#define DARL 0x80 /* Dest Addr Register L (single-block, RX only) */ 149#define DARH 0x81 /* Dest Addr Register H (single-block, RX only) */ 150#define DARB 0x82 /* Dest Addr Register B (single-block, RX only) */ 151#define DARBH 0x83 /* Dest Addr Register BH (single-block, RX only) */ 152#define SARL 0x80 /* Source Addr Register L (single-block, TX only) */ 153#define SARH 0x81 /* Source Addr Register H (single-block, TX only) */ 154#define SARB 0x82 /* Source Addr Register B (single-block, TX only) */ 155#define DARBH 0x83 /* Source Addr Register BH (single-block, TX only) */ 156#define BARL 0x80 /* Buffer Addr Register L (chained-block) */ 157#define BARH 0x81 /* Buffer Addr Register H (chained-block) */ 158#define BARB 0x82 /* Buffer Addr Register B (chained-block) */ 159#define BARBH 0x83 /* Buffer Addr Register BH (chained-block) */ 160#define CDAL 0x84 /* Current Descriptor Addr Register L */ 161#define CDAH 0x85 /* Current Descriptor Addr Register H */ 162#define CDAB 0x86 /* Current Descriptor Addr Register B */ 163#define CDABH 0x87 /* Current Descriptor Addr Register BH */ 164#define EDAL 0x88 /* Error Descriptor Addr Register L */ 165#define EDAH 0x89 /* Error Descriptor Addr Register H */ 166#define EDAB 0x8a /* Error Descriptor Addr Register B */ 167#define EDABH 0x8b /* Error Descriptor Addr Register BH */ 168#define BFLL 0x90 /* RX Buffer Length L (only RX) */ 169#define BFLH 0x91 /* RX Buffer Length H (only RX) */ 170#define BCRL 0x8c /* Byte Count Register L */ 171#define BCRH 0x8d /* Byte Count Register H */ 172 173/* Block Descriptor Structure */ 174typedef struct { 175 unsigned long next; /* pointer to next block descriptor */ 176 unsigned long ptbuf; /* buffer pointer */ 177 unsigned short len; /* data length */ 178 unsigned char status; /* status */ 179 unsigned char filler[5]; /* alignment filler (16 bytes) */ 180} pcsca_bd_t; 181 182/* Block Descriptor Structure */ 183typedef struct { 184 u32 cp; /* pointer to next block descriptor */ 185 u32 bp; /* buffer pointer */ 186 u16 len; /* data length */ 187 u8 stat; /* status */ 188 u8 unused; /* pads to 4-byte boundary */ 189}pkt_desc; 190 191 192/* 193 Descriptor Status definitions: 194 195 Bit Transmission Reception 196 197 7 EOM EOM 198 6 - Short Frame 199 5 - Abort 200 4 - Residual bit 201 3 Underrun Overrun 202 2 - CRC 203 1 Ownership Ownership 204 0 EOT - 205*/ 206#define DST_EOT 0x01 /* End of transmit command */ 207#define DST_OSB 0x02 /* Ownership bit */ 208#define DST_CRC 0x04 /* CRC Error */ 209#define DST_OVR 0x08 /* Overrun */ 210#define DST_UDR 0x08 /* Underrun */ 211#define DST_RBIT 0x10 /* Residual bit */ 212#define DST_ABT 0x20 /* Abort */ 213#define DST_SHRT 0x40 /* Short Frame */ 214#define DST_EOM 0x80 /* End of Message */ 215 216/* Packet Descriptor Status bits */ 217 218#define ST_TX_EOM 0x80 /* End of frame */ 219#define ST_TX_UNDRRUN 0x08 220#define ST_TX_OWNRSHP 0x02 221#define ST_TX_EOT 0x01 /* End of transmition */ 222 223#define ST_RX_EOM 0x80 /* End of frame */ 224#define ST_RX_SHORT 0x40 /* Short frame */ 225#define ST_RX_ABORT 0x20 /* Abort */ 226#define ST_RX_RESBIT 0x10 /* Residual bit */ 227#define ST_RX_OVERRUN 0x08 /* Overrun */ 228#define ST_RX_CRC 0x04 /* CRC */ 229#define ST_RX_OWNRSHP 0x02 230 231#define ST_ERROR_MASK 0x7C 232 233/* Status Counter Registers */ 234#define CMCR 0x158 /* Counter Master Ctl Reg */ 235#define TECNTL 0x160 /* Tx EOM Counter L */ 236#define TECNTM 0x161 /* Tx EOM Counter M */ 237#define TECNTH 0x162 /* Tx EOM Counter H */ 238#define TECCR 0x163 /* Tx EOM Counter Ctl Reg */ 239#define URCNTL 0x164 /* Underrun Counter L */ 240#define URCNTH 0x165 /* Underrun Counter H */ 241#define URCCR 0x167 /* Underrun Counter Ctl Reg */ 242#define RECNTL 0x168 /* Rx EOM Counter L */ 243#define RECNTM 0x169 /* Rx EOM Counter M */ 244#define RECNTH 0x16a /* Rx EOM Counter H */ 245#define RECCR 0x16b /* Rx EOM Counter Ctl Reg */ 246#define ORCNTL 0x16c /* Overrun Counter L */ 247#define ORCNTH 0x16d /* Overrun Counter H */ 248#define ORCCR 0x16f /* Overrun Counter Ctl Reg */ 249#define CECNTL 0x170 /* CRC Counter L */ 250#define CECNTH 0x171 /* CRC Counter H */ 251#define CECCR 0x173 /* CRC Counter Ctl Reg */ 252#define ABCNTL 0x174 /* Abort frame Counter L */ 253#define ABCNTH 0x175 /* Abort frame Counter H */ 254#define ABCCR 0x177 /* Abort frame Counter Ctl Reg */ 255#define SHCNTL 0x178 /* Short frame Counter L */ 256#define SHCNTH 0x179 /* Short frame Counter H */ 257#define SHCCR 0x17b /* Short frame Counter Ctl Reg */ 258#define RSCNTL 0x17c /* Residual bit Counter L */ 259#define RSCNTH 0x17d /* Residual bit Counter H */ 260#define RSCCR 0x17f /* Residual bit Counter Ctl Reg */ 261 262/* Register Programming Constants */ 263 264#define IR0_DMIC 0x00000001 265#define IR0_DMIB 0x00000002 266#define IR0_DMIA 0x00000004 267#define IR0_EFT 0x00000008 268#define IR0_DMAREQ 0x00010000 269#define IR0_TXINT 0x00020000 270#define IR0_RXINTB 0x00040000 271#define IR0_RXINTA 0x00080000 272#define IR0_TXRDY 0x00100000 273#define IR0_RXRDY 0x00200000 274 275#define MD0_CRC16_0 0x00 276#define MD0_CRC16_1 0x01 277#define MD0_CRC32 0x02 278#define MD0_CRC_CCITT 0x03 279#define MD0_CRCC0 0x04 280#define MD0_CRCC1 0x08 281#define MD0_AUTO_ENA 0x10 282#define MD0_ASYNC 0x00 283#define MD0_BY_MSYNC 0x20 284#define MD0_BY_BISYNC 0x40 285#define MD0_BY_EXT 0x60 286#define MD0_BIT_SYNC 0x80 287#define MD0_TRANSP 0xc0 288 289#define MD0_HDLC 0x80 /* Bit-sync HDLC mode */ 290 291#define MD0_CRC_NONE 0x00 292#define MD0_CRC_16_0 0x04 293#define MD0_CRC_16 0x05 294#define MD0_CRC_ITU32 0x06 295#define MD0_CRC_ITU 0x07 296 297#define MD1_NOADDR 0x00 298#define MD1_SADDR1 0x40 299#define MD1_SADDR2 0x80 300#define MD1_DADDR 0xc0 301 302#define MD2_NRZI_IEEE 0x40 303#define MD2_MANCHESTER 0x80 304#define MD2_FM_MARK 0xA0 305#define MD2_FM_SPACE 0xC0 306#define MD2_LOOPBACK 0x03 /* Local data Loopback */ 307 308#define MD2_F_DUPLEX 0x00 309#define MD2_AUTO_ECHO 0x01 310#define MD2_LOOP_HI_Z 0x02 311#define MD2_LOOP_MIR 0x03 312#define MD2_ADPLL_X8 0x00 313#define MD2_ADPLL_X16 0x08 314#define MD2_ADPLL_X32 0x10 315#define MD2_NRZ 0x00 316#define MD2_NRZI 0x20 317#define MD2_NRZ_IEEE 0x40 318#define MD2_MANCH 0x00 319#define MD2_FM1 0x20 320#define MD2_FM0 0x40 321#define MD2_FM 0x80 322 323#define CTL_RTS 0x01 324#define CTL_DTR 0x02 325#define CTL_SYN 0x04 326#define CTL_IDLC 0x10 327#define CTL_UDRNC 0x20 328#define CTL_URSKP 0x40 329#define CTL_URCT 0x80 330 331#define CTL_NORTS 0x01 332#define CTL_NODTR 0x02 333#define CTL_IDLE 0x10 334 335#define RXS_BR0 0x01 336#define RXS_BR1 0x02 337#define RXS_BR2 0x04 338#define RXS_BR3 0x08 339#define RXS_ECLK 0x00 340#define RXS_ECLK_NS 0x20 341#define RXS_IBRG 0x40 342#define RXS_PLL1 0x50 343#define RXS_PLL2 0x60 344#define RXS_PLL3 0x70 345#define RXS_DRTXC 0x80 346 347#define TXS_BR0 0x01 348#define TXS_BR1 0x02 349#define TXS_BR2 0x04 350#define TXS_BR3 0x08 351#define TXS_ECLK 0x00 352#define TXS_IBRG 0x40 353#define TXS_RCLK 0x60 354#define TXS_DTRXC 0x80 355 356#define EXS_RES0 0x01 357#define EXS_RES1 0x02 358#define EXS_RES2 0x04 359#define EXS_TES0 0x10 360#define EXS_TES1 0x20 361#define EXS_TES2 0x40 362 363#define CLK_BRG_MASK 0x0F 364#define CLK_PIN_OUT 0x80 365#define CLK_LINE 0x00 /* clock line input */ 366#define CLK_BRG 0x40 /* internal baud rate generator */ 367#define CLK_TX_RXCLK 0x60 /* TX clock from RX clock */ 368 369#define CMD_RX_RST 0x11 370#define CMD_RX_ENA 0x12 371#define CMD_RX_DIS 0x13 372#define CMD_RX_CRC_INIT 0x14 373#define CMD_RX_MSG_REJ 0x15 374#define CMD_RX_MP_SRCH 0x16 375#define CMD_RX_CRC_EXC 0x17 376#define CMD_RX_CRC_FRC 0x18 377#define CMD_TX_RST 0x01 378#define CMD_TX_ENA 0x02 379#define CMD_TX_DISA 0x03 380#define CMD_TX_CRC_INIT 0x04 381#define CMD_TX_CRC_EXC 0x05 382#define CMD_TX_EOM 0x06 383#define CMD_TX_ABORT 0x07 384#define CMD_TX_MP_ON 0x08 385#define CMD_TX_BUF_CLR 0x09 386#define CMD_TX_DISB 0x0b 387#define CMD_CH_RST 0x21 388#define CMD_SRCH_MODE 0x31 389#define CMD_NOP 0x00 390 391#define CMD_RESET 0x21 392#define CMD_TX_ENABLE 0x02 393#define CMD_RX_ENABLE 0x12 394 395#define ST0_RXRDY 0x01 396#define ST0_TXRDY 0x02 397#define ST0_RXINTB 0x20 398#define ST0_RXINTA 0x40 399#define ST0_TXINT 0x80 400 401#define ST1_IDLE 0x01 402#define ST1_ABORT 0x02 403#define ST1_CDCD 0x04 404#define ST1_CCTS 0x08 405#define ST1_SYN_FLAG 0x10 406#define ST1_CLMD 0x20 407#define ST1_TXIDLE 0x40 408#define ST1_UDRN 0x80 409 410#define ST2_CRCE 0x04 411#define ST2_ONRN 0x08 412#define ST2_RBIT 0x10 413#define ST2_ABORT 0x20 414#define ST2_SHORT 0x40 415#define ST2_EOM 0x80 416 417#define ST3_RX_ENA 0x01 418#define ST3_TX_ENA 0x02 419#define ST3_DCD 0x04 420#define ST3_CTS 0x08 421#define ST3_SRCH_MODE 0x10 422#define ST3_SLOOP 0x20 423#define ST3_GPI 0x80 424 425#define ST4_RDNR 0x01 426#define ST4_RDCR 0x02 427#define ST4_TDNR 0x04 428#define ST4_TDCR 0x08 429#define ST4_OCLM 0x20 430#define ST4_CFT 0x40 431#define ST4_CGPI 0x80 432 433#define FST_CRCEF 0x04 434#define FST_OVRNF 0x08 435#define FST_RBIF 0x10 436#define FST_ABTF 0x20 437#define FST_SHRTF 0x40 438#define FST_EOMF 0x80 439 440#define IE0_RXRDY 0x01 441#define IE0_TXRDY 0x02 442#define IE0_RXINTB 0x20 443#define IE0_RXINTA 0x40 444#define IE0_TXINT 0x80 445#define IE0_UDRN 0x00008000 /* TX underrun MSCI interrupt enable */ 446#define IE0_CDCD 0x00000400 /* CD level change interrupt enable */ 447 448#define IE1_IDLD 0x01 449#define IE1_ABTD 0x02 450#define IE1_CDCD 0x04 451#define IE1_CCTS 0x08 452#define IE1_SYNCD 0x10 453#define IE1_CLMD 0x20 454#define IE1_IDL 0x40 455#define IE1_UDRN 0x80 456 457#define IE2_CRCE 0x04 458#define IE2_OVRN 0x08 459#define IE2_RBIT 0x10 460#define IE2_ABT 0x20 461#define IE2_SHRT 0x40 462#define IE2_EOM 0x80 463 464#define IE4_RDNR 0x01 465#define IE4_RDCR 0x02 466#define IE4_TDNR 0x04 467#define IE4_TDCR 0x08 468#define IE4_OCLM 0x20 469#define IE4_CFT 0x40 470#define IE4_CGPI 0x80 471 472#define FIE_CRCEF 0x04 473#define FIE_OVRNF 0x08 474#define FIE_RBIF 0x10 475#define FIE_ABTF 0x20 476#define FIE_SHRTF 0x40 477#define FIE_EOMF 0x80 478 479#define DSR_DWE 0x01 480#define DSR_DE 0x02 481#define DSR_REF 0x04 482#define DSR_UDRF 0x04 483#define DSR_COA 0x08 484#define DSR_COF 0x10 485#define DSR_BOF 0x20 486#define DSR_EOM 0x40 487#define DSR_EOT 0x80 488 489#define DIR_REF 0x04 490#define DIR_UDRF 0x04 491#define DIR_COA 0x08 492#define DIR_COF 0x10 493#define DIR_BOF 0x20 494#define DIR_EOM 0x40 495#define DIR_EOT 0x80 496 497#define DIR_REFE 0x04 498#define DIR_UDRFE 0x04 499#define DIR_COAE 0x08 500#define DIR_COFE 0x10 501#define DIR_BOFE 0x20 502#define DIR_EOME 0x40 503#define DIR_EOTE 0x80 504 505#define DMR_CNTE 0x02 506#define DMR_NF 0x04 507#define DMR_SEOME 0x08 508#define DMR_TMOD 0x10 509 510#define DMER_DME 0x80 /* DMA Master Enable */ 511 512#define DCR_SW_ABT 0x01 513#define DCR_FCT_CLR 0x02 514 515#define DCR_ABORT 0x01 516#define DCR_CLEAR_EOF 0x02 517 518#define PCR_COTE 0x80 519#define PCR_PR0 0x01 520#define PCR_PR1 0x02 521#define PCR_PR2 0x04 522#define PCR_CCC 0x08 523#define PCR_BRC 0x10 524#define PCR_OSB 0x40 525#define PCR_BURST 0x80 526 527#endif /* (__HD64572_H) */ 528