1/* 2 * FarSync WAN driver for Linux (2.6.x kernel version) 3 * 4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards 5 * 6 * Copyright (C) 2001-2004 FarSite Communications Ltd. 7 * www.farsite.co.uk 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk> 15 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk> 16 */ 17 18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19 20#include <linux/module.h> 21#include <linux/kernel.h> 22#include <linux/version.h> 23#include <linux/pci.h> 24#include <linux/sched.h> 25#include <linux/slab.h> 26#include <linux/ioport.h> 27#include <linux/init.h> 28#include <linux/if.h> 29#include <linux/hdlc.h> 30#include <asm/io.h> 31#include <asm/uaccess.h> 32 33#include "farsync.h" 34 35/* 36 * Module info 37 */ 38MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>"); 39MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd."); 40MODULE_LICENSE("GPL"); 41 42/* Driver configuration and global parameters 43 * ========================================== 44 */ 45 46/* Number of ports (per card) and cards supported 47 */ 48#define FST_MAX_PORTS 4 49#define FST_MAX_CARDS 32 50 51/* Default parameters for the link 52 */ 53#define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is 54 * useful */ 55#define FST_TXQ_DEPTH 16 /* This one is for the buffering 56 * of frames on the way down to the card 57 * so that we can keep the card busy 58 * and maximise throughput 59 */ 60#define FST_HIGH_WATER_MARK 12 /* Point at which we flow control 61 * network layer */ 62#define FST_LOW_WATER_MARK 8 /* Point at which we remove flow 63 * control from network layer */ 64#define FST_MAX_MTU 8000 /* Huge but possible */ 65#define FST_DEF_MTU 1500 /* Common sane value */ 66 67#define FST_TX_TIMEOUT (2*HZ) 68 69#ifdef ARPHRD_RAWHDLC 70#define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */ 71#else 72#define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */ 73#endif 74 75/* 76 * Modules parameters and associated variables 77 */ 78static int fst_txq_low = FST_LOW_WATER_MARK; 79static int fst_txq_high = FST_HIGH_WATER_MARK; 80static int fst_max_reads = 7; 81static int fst_excluded_cards = 0; 82static int fst_excluded_list[FST_MAX_CARDS]; 83 84module_param(fst_txq_low, int, 0); 85module_param(fst_txq_high, int, 0); 86module_param(fst_max_reads, int, 0); 87module_param(fst_excluded_cards, int, 0); 88module_param_array(fst_excluded_list, int, NULL, 0); 89 90/* Card shared memory layout 91 * ========================= 92 */ 93#pragma pack(1) 94 95/* This information is derived in part from the FarSite FarSync Smc.h 96 * file. Unfortunately various name clashes and the non-portability of the 97 * bit field declarations in that file have meant that I have chosen to 98 * recreate the information here. 99 * 100 * The SMC (Shared Memory Configuration) has a version number that is 101 * incremented every time there is a significant change. This number can 102 * be used to check that we have not got out of step with the firmware 103 * contained in the .CDE files. 104 */ 105#define SMC_VERSION 24 106 107#define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */ 108 109#define SMC_BASE 0x00002000L /* Base offset of the shared memory window main 110 * configuration structure */ 111#define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA 112 * buffers */ 113 114#define LEN_TX_BUFFER 8192 /* Size of packet buffers */ 115#define LEN_RX_BUFFER 8192 116 117#define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */ 118#define LEN_SMALL_RX_BUFFER 256 119 120#define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */ 121#define NUM_RX_BUFFER 8 122 123/* Interrupt retry time in milliseconds */ 124#define INT_RETRY_TIME 2 125 126/* The Am186CH/CC processors support a SmartDMA mode using circular pools 127 * of buffer descriptors. The structure is almost identical to that used 128 * in the LANCE Ethernet controllers. Details available as PDF from the 129 * AMD web site: http://www.amd.com/products/epd/processors/\ 130 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf 131 */ 132struct txdesc { /* Transmit descriptor */ 133 volatile u16 ladr; /* Low order address of packet. This is a 134 * linear address in the Am186 memory space 135 */ 136 volatile u8 hadr; /* High order address. Low 4 bits only, high 4 137 * bits must be zero 138 */ 139 volatile u8 bits; /* Status and config */ 140 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits. 141 * Transmit terminal count interrupt enable in 142 * top bit. 143 */ 144 u16 unused; /* Not used in Tx */ 145}; 146 147struct rxdesc { /* Receive descriptor */ 148 volatile u16 ladr; /* Low order address of packet */ 149 volatile u8 hadr; /* High order address */ 150 volatile u8 bits; /* Status and config */ 151 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits. 152 * Receive terminal count interrupt enable in 153 * top bit. 154 */ 155 volatile u16 mcnt; /* Message byte count (15 bits) */ 156}; 157 158/* Convert a length into the 15 bit 2's complement */ 159/* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */ 160/* Since we need to set the high bit to enable the completion interrupt this 161 * can be made a lot simpler 162 */ 163#define cnv_bcnt(len) (-(len)) 164 165/* Status and config bits for the above */ 166#define DMA_OWN 0x80 /* SmartDMA owns the descriptor */ 167#define TX_STP 0x02 /* Tx: start of packet */ 168#define TX_ENP 0x01 /* Tx: end of packet */ 169#define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */ 170#define RX_FRAM 0x20 /* Rx: framing error */ 171#define RX_OFLO 0x10 /* Rx: overflow error */ 172#define RX_CRC 0x08 /* Rx: CRC error */ 173#define RX_HBUF 0x04 /* Rx: buffer error */ 174#define RX_STP 0x02 /* Rx: start of packet */ 175#define RX_ENP 0x01 /* Rx: end of packet */ 176 177/* Interrupts from the card are caused by various events which are presented 178 * in a circular buffer as several events may be processed on one physical int 179 */ 180#define MAX_CIRBUFF 32 181 182struct cirbuff { 183 u8 rdindex; /* read, then increment and wrap */ 184 u8 wrindex; /* write, then increment and wrap */ 185 u8 evntbuff[MAX_CIRBUFF]; 186}; 187 188/* Interrupt event codes. 189 * Where appropriate the two low order bits indicate the port number 190 */ 191#define CTLA_CHG 0x18 /* Control signal changed */ 192#define CTLB_CHG 0x19 193#define CTLC_CHG 0x1A 194#define CTLD_CHG 0x1B 195 196#define INIT_CPLT 0x20 /* Initialisation complete */ 197#define INIT_FAIL 0x21 /* Initialisation failed */ 198 199#define ABTA_SENT 0x24 /* Abort sent */ 200#define ABTB_SENT 0x25 201#define ABTC_SENT 0x26 202#define ABTD_SENT 0x27 203 204#define TXA_UNDF 0x28 /* Transmission underflow */ 205#define TXB_UNDF 0x29 206#define TXC_UNDF 0x2A 207#define TXD_UNDF 0x2B 208 209#define F56_INT 0x2C 210#define M32_INT 0x2D 211 212#define TE1_ALMA 0x30 213 214/* Port physical configuration. See farsync.h for field values */ 215struct port_cfg { 216 u16 lineInterface; /* Physical interface type */ 217 u8 x25op; /* Unused at present */ 218 u8 internalClock; /* 1 => internal clock, 0 => external */ 219 u8 transparentMode; /* 1 => on, 0 => off */ 220 u8 invertClock; /* 0 => normal, 1 => inverted */ 221 u8 padBytes[6]; /* Padding */ 222 u32 lineSpeed; /* Speed in bps */ 223}; 224 225/* TE1 port physical configuration */ 226struct su_config { 227 u32 dataRate; 228 u8 clocking; 229 u8 framing; 230 u8 structure; 231 u8 interface; 232 u8 coding; 233 u8 lineBuildOut; 234 u8 equalizer; 235 u8 transparentMode; 236 u8 loopMode; 237 u8 range; 238 u8 txBufferMode; 239 u8 rxBufferMode; 240 u8 startingSlot; 241 u8 losThreshold; 242 u8 enableIdleCode; 243 u8 idleCode; 244 u8 spare[44]; 245}; 246 247/* TE1 Status */ 248struct su_status { 249 u32 receiveBufferDelay; 250 u32 framingErrorCount; 251 u32 codeViolationCount; 252 u32 crcErrorCount; 253 u32 lineAttenuation; 254 u8 portStarted; 255 u8 lossOfSignal; 256 u8 receiveRemoteAlarm; 257 u8 alarmIndicationSignal; 258 u8 spare[40]; 259}; 260 261/* Finally sling all the above together into the shared memory structure. 262 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been 263 * evolving under NT for some time so I guess we're stuck with it. 264 * The structure starts at offset SMC_BASE. 265 * See farsync.h for some field values. 266 */ 267struct fst_shared { 268 /* DMA descriptor rings */ 269 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER]; 270 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER]; 271 272 /* Obsolete small buffers */ 273 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER]; 274 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER]; 275 276 u8 taskStatus; /* 0x00 => initialising, 0x01 => running, 277 * 0xFF => halted 278 */ 279 280 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt, 281 * set to 0xEE by host to acknowledge interrupt 282 */ 283 284 u16 smcVersion; /* Must match SMC_VERSION */ 285 286 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major 287 * version, RR = revision and BB = build 288 */ 289 290 u16 txa_done; /* Obsolete completion flags */ 291 u16 rxa_done; 292 u16 txb_done; 293 u16 rxb_done; 294 u16 txc_done; 295 u16 rxc_done; 296 u16 txd_done; 297 u16 rxd_done; 298 299 u16 mailbox[4]; /* Diagnostics mailbox. Not used */ 300 301 struct cirbuff interruptEvent; /* interrupt causes */ 302 303 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */ 304 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */ 305 306 struct port_cfg portConfig[FST_MAX_PORTS]; 307 308 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */ 309 310 u16 cableStatus; /* lsb: 0=> present, 1=> absent */ 311 312 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */ 313 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */ 314 315 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */ 316 u16 cardMailbox[4]; /* Not used */ 317 318 /* Number of times the card thinks the host has 319 * missed an interrupt by not acknowledging 320 * within 2mS (I guess NT has problems) 321 */ 322 u32 interruptRetryCount; 323 324 /* Driver private data used as an ID. We'll not 325 * use this as I'd rather keep such things 326 * in main memory rather than on the PCI bus 327 */ 328 u32 portHandle[FST_MAX_PORTS]; 329 330 /* Count of Tx underflows for stats */ 331 u32 transmitBufferUnderflow[FST_MAX_PORTS]; 332 333 /* Debounced V.24 control input status */ 334 u32 v24DebouncedSts[FST_MAX_PORTS]; 335 336 /* Adapter debounce timers. Don't touch */ 337 u32 ctsTimer[FST_MAX_PORTS]; 338 u32 ctsTimerRun[FST_MAX_PORTS]; 339 u32 dcdTimer[FST_MAX_PORTS]; 340 u32 dcdTimerRun[FST_MAX_PORTS]; 341 342 u32 numberOfPorts; /* Number of ports detected at startup */ 343 344 u16 _reserved[64]; 345 346 u16 cardMode; /* Bit-mask to enable features: 347 * Bit 0: 1 enables LED identify mode 348 */ 349 350 u16 portScheduleOffset; 351 352 struct su_config suConfig; /* TE1 Bits */ 353 struct su_status suStatus; 354 355 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of 356 * the structure and marks the end of shared 357 * memory. Adapter code initializes it as 358 * END_SIG. 359 */ 360}; 361 362/* endOfSmcSignature value */ 363#define END_SIG 0x12345678 364 365/* Mailbox values. (portMailbox) */ 366#define NOP 0 /* No operation */ 367#define ACK 1 /* Positive acknowledgement to PC driver */ 368#define NAK 2 /* Negative acknowledgement to PC driver */ 369#define STARTPORT 3 /* Start an HDLC port */ 370#define STOPPORT 4 /* Stop an HDLC port */ 371#define ABORTTX 5 /* Abort the transmitter for a port */ 372#define SETV24O 6 /* Set V24 outputs */ 373 374/* PLX Chip Register Offsets */ 375#define CNTRL_9052 0x50 /* Control Register */ 376#define CNTRL_9054 0x6c /* Control Register */ 377 378#define INTCSR_9052 0x4c /* Interrupt control/status register */ 379#define INTCSR_9054 0x68 /* Interrupt control/status register */ 380 381/* 9054 DMA Registers */ 382/* 383 * Note that we will be using DMA Channel 0 for copying rx data 384 * and Channel 1 for copying tx data 385 */ 386#define DMAMODE0 0x80 387#define DMAPADR0 0x84 388#define DMALADR0 0x88 389#define DMASIZ0 0x8c 390#define DMADPR0 0x90 391#define DMAMODE1 0x94 392#define DMAPADR1 0x98 393#define DMALADR1 0x9c 394#define DMASIZ1 0xa0 395#define DMADPR1 0xa4 396#define DMACSR0 0xa8 397#define DMACSR1 0xa9 398#define DMAARB 0xac 399#define DMATHR 0xb0 400#define DMADAC0 0xb4 401#define DMADAC1 0xb8 402#define DMAMARBR 0xac 403 404#define FST_MIN_DMA_LEN 64 405#define FST_RX_DMA_INT 0x01 406#define FST_TX_DMA_INT 0x02 407#define FST_CARD_INT 0x04 408 409/* Larger buffers are positioned in memory at offset BFM_BASE */ 410struct buf_window { 411 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER]; 412 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER]; 413}; 414 415/* Calculate offset of a buffer object within the shared memory window */ 416#define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X)) 417 418#pragma pack() 419 420/* Device driver private information 421 * ================================= 422 */ 423/* Per port (line or channel) information 424 */ 425struct fst_port_info { 426 struct net_device *dev; /* Device struct - must be first */ 427 struct fst_card_info *card; /* Card we're associated with */ 428 int index; /* Port index on the card */ 429 int hwif; /* Line hardware (lineInterface copy) */ 430 int run; /* Port is running */ 431 int mode; /* Normal or FarSync raw */ 432 int rxpos; /* Next Rx buffer to use */ 433 int txpos; /* Next Tx buffer to use */ 434 int txipos; /* Next Tx buffer to check for free */ 435 int start; /* Indication of start/stop to network */ 436 /* 437 * A sixteen entry transmit queue 438 */ 439 int txqs; /* index to get next buffer to tx */ 440 int txqe; /* index to queue next packet */ 441 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */ 442 int rxqdepth; 443}; 444 445/* Per card information 446 */ 447struct fst_card_info { 448 char __iomem *mem; /* Card memory mapped to kernel space */ 449 char __iomem *ctlmem; /* Control memory for PCI cards */ 450 unsigned int phys_mem; /* Physical memory window address */ 451 unsigned int phys_ctlmem; /* Physical control memory address */ 452 unsigned int irq; /* Interrupt request line number */ 453 unsigned int nports; /* Number of serial ports */ 454 unsigned int type; /* Type index of card */ 455 unsigned int state; /* State of card */ 456 spinlock_t card_lock; /* Lock for SMP access */ 457 unsigned short pci_conf; /* PCI card config in I/O space */ 458 /* Per port info */ 459 struct fst_port_info ports[FST_MAX_PORTS]; 460 struct pci_dev *device; /* Information about the pci device */ 461 int card_no; /* Inst of the card on the system */ 462 int family; /* TxP or TxU */ 463 int dmarx_in_progress; 464 int dmatx_in_progress; 465 unsigned long int_count; 466 unsigned long int_time_ave; 467 void *rx_dma_handle_host; 468 dma_addr_t rx_dma_handle_card; 469 void *tx_dma_handle_host; 470 dma_addr_t tx_dma_handle_card; 471 struct sk_buff *dma_skb_rx; 472 struct fst_port_info *dma_port_rx; 473 struct fst_port_info *dma_port_tx; 474 int dma_len_rx; 475 int dma_len_tx; 476 int dma_txpos; 477 int dma_rxpos; 478}; 479 480/* Convert an HDLC device pointer into a port info pointer and similar */ 481#define dev_to_port(D) (dev_to_hdlc(D)->priv) 482#define port_to_dev(P) ((P)->dev) 483 484 485/* 486 * Shared memory window access macros 487 * 488 * We have a nice memory based structure above, which could be directly 489 * mapped on i386 but might not work on other architectures unless we use 490 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take 491 * physical offsets so we have to convert. The only saving grace is that 492 * this should all collapse back to a simple indirection eventually. 493 */ 494#define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X)) 495 496#define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E)) 497#define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E)) 498#define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E)) 499 500#define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E)) 501#define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E)) 502#define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E)) 503 504/* 505 * Debug support 506 */ 507#if FST_DEBUG 508 509static int fst_debug_mask = { FST_DEBUG }; 510 511/* Most common debug activity is to print something if the corresponding bit 512 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to 513 * support variable numbers of macro parameters. The inverted if prevents us 514 * eating someone else's else clause. 515 */ 516#define dbg(F, fmt, args...) \ 517do { \ 518 if (fst_debug_mask & (F)) \ 519 printk(KERN_DEBUG pr_fmt(fmt), ##args); \ 520} while (0) 521#else 522#define dbg(F, fmt, args...) \ 523do { \ 524 if (0) \ 525 printk(KERN_DEBUG pr_fmt(fmt), ##args); \ 526} while (0) 527#endif 528 529/* 530 * PCI ID lookup table 531 */ 532static DEFINE_PCI_DEVICE_TABLE(fst_pci_dev_id) = { 533 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID, 534 PCI_ANY_ID, 0, 0, FST_TYPE_T2P}, 535 536 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID, 537 PCI_ANY_ID, 0, 0, FST_TYPE_T4P}, 538 539 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID, 540 PCI_ANY_ID, 0, 0, FST_TYPE_T1U}, 541 542 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID, 543 PCI_ANY_ID, 0, 0, FST_TYPE_T2U}, 544 545 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID, 546 PCI_ANY_ID, 0, 0, FST_TYPE_T4U}, 547 548 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID, 549 PCI_ANY_ID, 0, 0, FST_TYPE_TE1}, 550 551 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID, 552 PCI_ANY_ID, 0, 0, FST_TYPE_TE1}, 553 {0,} /* End */ 554}; 555 556MODULE_DEVICE_TABLE(pci, fst_pci_dev_id); 557 558/* 559 * Device Driver Work Queues 560 * 561 * So that we don't spend too much time processing events in the 562 * Interrupt Service routine, we will declare a work queue per Card 563 * and make the ISR schedule a task in the queue for later execution. 564 * In the 2.4 Kernel we used to use the immediate queue for BH's 565 * Now that they are gone, tasklets seem to be much better than work 566 * queues. 567 */ 568 569static void do_bottom_half_tx(struct fst_card_info *card); 570static void do_bottom_half_rx(struct fst_card_info *card); 571static void fst_process_tx_work_q(unsigned long work_q); 572static void fst_process_int_work_q(unsigned long work_q); 573 574static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0); 575static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0); 576 577static struct fst_card_info *fst_card_array[FST_MAX_CARDS]; 578static spinlock_t fst_work_q_lock; 579static u64 fst_work_txq; 580static u64 fst_work_intq; 581 582static void 583fst_q_work_item(u64 * queue, int card_index) 584{ 585 unsigned long flags; 586 u64 mask; 587 588 /* 589 * Grab the queue exclusively 590 */ 591 spin_lock_irqsave(&fst_work_q_lock, flags); 592 593 /* 594 * Making an entry in the queue is simply a matter of setting 595 * a bit for the card indicating that there is work to do in the 596 * bottom half for the card. Note the limitation of 64 cards. 597 * That ought to be enough 598 */ 599 mask = 1 << card_index; 600 *queue |= mask; 601 spin_unlock_irqrestore(&fst_work_q_lock, flags); 602} 603 604static void 605fst_process_tx_work_q(unsigned long /*void **/work_q) 606{ 607 unsigned long flags; 608 u64 work_txq; 609 int i; 610 611 /* 612 * Grab the queue exclusively 613 */ 614 dbg(DBG_TX, "fst_process_tx_work_q\n"); 615 spin_lock_irqsave(&fst_work_q_lock, flags); 616 work_txq = fst_work_txq; 617 fst_work_txq = 0; 618 spin_unlock_irqrestore(&fst_work_q_lock, flags); 619 620 /* 621 * Call the bottom half for each card with work waiting 622 */ 623 for (i = 0; i < FST_MAX_CARDS; i++) { 624 if (work_txq & 0x01) { 625 if (fst_card_array[i] != NULL) { 626 dbg(DBG_TX, "Calling tx bh for card %d\n", i); 627 do_bottom_half_tx(fst_card_array[i]); 628 } 629 } 630 work_txq = work_txq >> 1; 631 } 632} 633 634static void 635fst_process_int_work_q(unsigned long /*void **/work_q) 636{ 637 unsigned long flags; 638 u64 work_intq; 639 int i; 640 641 /* 642 * Grab the queue exclusively 643 */ 644 dbg(DBG_INTR, "fst_process_int_work_q\n"); 645 spin_lock_irqsave(&fst_work_q_lock, flags); 646 work_intq = fst_work_intq; 647 fst_work_intq = 0; 648 spin_unlock_irqrestore(&fst_work_q_lock, flags); 649 650 /* 651 * Call the bottom half for each card with work waiting 652 */ 653 for (i = 0; i < FST_MAX_CARDS; i++) { 654 if (work_intq & 0x01) { 655 if (fst_card_array[i] != NULL) { 656 dbg(DBG_INTR, 657 "Calling rx & tx bh for card %d\n", i); 658 do_bottom_half_rx(fst_card_array[i]); 659 do_bottom_half_tx(fst_card_array[i]); 660 } 661 } 662 work_intq = work_intq >> 1; 663 } 664} 665 666/* Card control functions 667 * ====================== 668 */ 669/* Place the processor in reset state 670 * 671 * Used to be a simple write to card control space but a glitch in the latest 672 * AMD Am186CH processor means that we now have to do it by asserting and de- 673 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register 674 * at offset 9052_CNTRL. Note the updates for the TXU. 675 */ 676static inline void 677fst_cpureset(struct fst_card_info *card) 678{ 679 unsigned char interrupt_line_register; 680 unsigned long j = jiffies + 1; 681 unsigned int regval; 682 683 if (card->family == FST_FAMILY_TXU) { 684 if (pci_read_config_byte 685 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) { 686 dbg(DBG_ASS, 687 "Error in reading interrupt line register\n"); 688 } 689 /* 690 * Assert PLX software reset and Am186 hardware reset 691 * and then deassert the PLX software reset but 186 still in reset 692 */ 693 outw(0x440f, card->pci_conf + CNTRL_9054 + 2); 694 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); 695 /* 696 * We are delaying here to allow the 9054 to reset itself 697 */ 698 j = jiffies + 1; 699 while (jiffies < j) 700 /* Do nothing */ ; 701 outw(0x240f, card->pci_conf + CNTRL_9054 + 2); 702 /* 703 * We are delaying here to allow the 9054 to reload its eeprom 704 */ 705 j = jiffies + 1; 706 while (jiffies < j) 707 /* Do nothing */ ; 708 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); 709 710 if (pci_write_config_byte 711 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) { 712 dbg(DBG_ASS, 713 "Error in writing interrupt line register\n"); 714 } 715 716 } else { 717 regval = inl(card->pci_conf + CNTRL_9052); 718 719 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052); 720 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052); 721 } 722} 723 724/* Release the processor from reset 725 */ 726static inline void 727fst_cpurelease(struct fst_card_info *card) 728{ 729 if (card->family == FST_FAMILY_TXU) { 730 /* 731 * Force posted writes to complete 732 */ 733 (void) readb(card->mem); 734 735 /* 736 * Release LRESET DO = 1 737 * Then release Local Hold, DO = 1 738 */ 739 outw(0x040e, card->pci_conf + CNTRL_9054 + 2); 740 outw(0x040f, card->pci_conf + CNTRL_9054 + 2); 741 } else { 742 (void) readb(card->ctlmem); 743 } 744} 745 746/* Clear the cards interrupt flag 747 */ 748static inline void 749fst_clear_intr(struct fst_card_info *card) 750{ 751 if (card->family == FST_FAMILY_TXU) { 752 (void) readb(card->ctlmem); 753 } else { 754 /* Poke the appropriate PLX chip register (same as enabling interrupts) 755 */ 756 outw(0x0543, card->pci_conf + INTCSR_9052); 757 } 758} 759 760/* Enable card interrupts 761 */ 762static inline void 763fst_enable_intr(struct fst_card_info *card) 764{ 765 if (card->family == FST_FAMILY_TXU) { 766 outl(0x0f0c0900, card->pci_conf + INTCSR_9054); 767 } else { 768 outw(0x0543, card->pci_conf + INTCSR_9052); 769 } 770} 771 772/* Disable card interrupts 773 */ 774static inline void 775fst_disable_intr(struct fst_card_info *card) 776{ 777 if (card->family == FST_FAMILY_TXU) { 778 outl(0x00000000, card->pci_conf + INTCSR_9054); 779 } else { 780 outw(0x0000, card->pci_conf + INTCSR_9052); 781 } 782} 783 784/* Process the result of trying to pass a received frame up the stack 785 */ 786static void 787fst_process_rx_status(int rx_status, char *name) 788{ 789 switch (rx_status) { 790 case NET_RX_SUCCESS: 791 { 792 /* 793 * Nothing to do here 794 */ 795 break; 796 } 797 case NET_RX_DROP: 798 { 799 dbg(DBG_ASS, "%s: Received packet dropped\n", name); 800 break; 801 } 802 } 803} 804 805/* Initilaise DMA for PLX 9054 806 */ 807static inline void 808fst_init_dma(struct fst_card_info *card) 809{ 810 /* 811 * This is only required for the PLX 9054 812 */ 813 if (card->family == FST_FAMILY_TXU) { 814 pci_set_master(card->device); 815 outl(0x00020441, card->pci_conf + DMAMODE0); 816 outl(0x00020441, card->pci_conf + DMAMODE1); 817 outl(0x0, card->pci_conf + DMATHR); 818 } 819} 820 821/* Tx dma complete interrupt 822 */ 823static void 824fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port, 825 int len, int txpos) 826{ 827 struct net_device *dev = port_to_dev(port); 828 829 /* 830 * Everything is now set, just tell the card to go 831 */ 832 dbg(DBG_TX, "fst_tx_dma_complete\n"); 833 FST_WRB(card, txDescrRing[port->index][txpos].bits, 834 DMA_OWN | TX_STP | TX_ENP); 835 dev->stats.tx_packets++; 836 dev->stats.tx_bytes += len; 837 dev->trans_start = jiffies; 838} 839 840/* 841 * Mark it for our own raw sockets interface 842 */ 843static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev) 844{ 845 skb->dev = dev; 846 skb_reset_mac_header(skb); 847 skb->pkt_type = PACKET_HOST; 848 return htons(ETH_P_CUST); 849} 850 851/* Rx dma complete interrupt 852 */ 853static void 854fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port, 855 int len, struct sk_buff *skb, int rxp) 856{ 857 struct net_device *dev = port_to_dev(port); 858 int pi; 859 int rx_status; 860 861 dbg(DBG_TX, "fst_rx_dma_complete\n"); 862 pi = port->index; 863 memcpy(skb_put(skb, len), card->rx_dma_handle_host, len); 864 865 /* Reset buffer descriptor */ 866 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 867 868 /* Update stats */ 869 dev->stats.rx_packets++; 870 dev->stats.rx_bytes += len; 871 872 /* Push upstream */ 873 dbg(DBG_RX, "Pushing the frame up the stack\n"); 874 if (port->mode == FST_RAW) 875 skb->protocol = farsync_type_trans(skb, dev); 876 else 877 skb->protocol = hdlc_type_trans(skb, dev); 878 rx_status = netif_rx(skb); 879 fst_process_rx_status(rx_status, port_to_dev(port)->name); 880 if (rx_status == NET_RX_DROP) 881 dev->stats.rx_dropped++; 882} 883 884/* 885 * Receive a frame through the DMA 886 */ 887static inline void 888fst_rx_dma(struct fst_card_info *card, dma_addr_t skb, 889 dma_addr_t mem, int len) 890{ 891 /* 892 * This routine will setup the DMA and start it 893 */ 894 895 dbg(DBG_RX, "In fst_rx_dma %lx %lx %d\n", 896 (unsigned long) skb, (unsigned long) mem, len); 897 if (card->dmarx_in_progress) { 898 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n"); 899 } 900 901 outl(skb, card->pci_conf + DMAPADR0); /* Copy to here */ 902 outl(mem, card->pci_conf + DMALADR0); /* from here */ 903 outl(len, card->pci_conf + DMASIZ0); /* for this length */ 904 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */ 905 906 /* 907 * We use the dmarx_in_progress flag to flag the channel as busy 908 */ 909 card->dmarx_in_progress = 1; 910 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */ 911} 912 913/* 914 * Send a frame through the DMA 915 */ 916static inline void 917fst_tx_dma(struct fst_card_info *card, unsigned char *skb, 918 unsigned char *mem, int len) 919{ 920 /* 921 * This routine will setup the DMA and start it. 922 */ 923 924 dbg(DBG_TX, "In fst_tx_dma %p %p %d\n", skb, mem, len); 925 if (card->dmatx_in_progress) { 926 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n"); 927 } 928 929 outl((unsigned long) skb, card->pci_conf + DMAPADR1); /* Copy from here */ 930 outl((unsigned long) mem, card->pci_conf + DMALADR1); /* to here */ 931 outl(len, card->pci_conf + DMASIZ1); /* for this length */ 932 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */ 933 934 /* 935 * We use the dmatx_in_progress to flag the channel as busy 936 */ 937 card->dmatx_in_progress = 1; 938 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */ 939} 940 941/* Issue a Mailbox command for a port. 942 * Note we issue them on a fire and forget basis, not expecting to see an 943 * error and not waiting for completion. 944 */ 945static void 946fst_issue_cmd(struct fst_port_info *port, unsigned short cmd) 947{ 948 struct fst_card_info *card; 949 unsigned short mbval; 950 unsigned long flags; 951 int safety; 952 953 card = port->card; 954 spin_lock_irqsave(&card->card_lock, flags); 955 mbval = FST_RDW(card, portMailbox[port->index][0]); 956 957 safety = 0; 958 /* Wait for any previous command to complete */ 959 while (mbval > NAK) { 960 spin_unlock_irqrestore(&card->card_lock, flags); 961 schedule_timeout_uninterruptible(1); 962 spin_lock_irqsave(&card->card_lock, flags); 963 964 if (++safety > 2000) { 965 pr_err("Mailbox safety timeout\n"); 966 break; 967 } 968 969 mbval = FST_RDW(card, portMailbox[port->index][0]); 970 } 971 if (safety > 0) { 972 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety); 973 } 974 if (mbval == NAK) { 975 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n"); 976 } 977 978 FST_WRW(card, portMailbox[port->index][0], cmd); 979 980 if (cmd == ABORTTX || cmd == STARTPORT) { 981 port->txpos = 0; 982 port->txipos = 0; 983 port->start = 0; 984 } 985 986 spin_unlock_irqrestore(&card->card_lock, flags); 987} 988 989/* Port output signals control 990 */ 991static inline void 992fst_op_raise(struct fst_port_info *port, unsigned int outputs) 993{ 994 outputs |= FST_RDL(port->card, v24OpSts[port->index]); 995 FST_WRL(port->card, v24OpSts[port->index], outputs); 996 997 if (port->run) 998 fst_issue_cmd(port, SETV24O); 999} 1000 1001static inline void 1002fst_op_lower(struct fst_port_info *port, unsigned int outputs) 1003{ 1004 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]); 1005 FST_WRL(port->card, v24OpSts[port->index], outputs); 1006 1007 if (port->run) 1008 fst_issue_cmd(port, SETV24O); 1009} 1010 1011/* 1012 * Setup port Rx buffers 1013 */ 1014static void 1015fst_rx_config(struct fst_port_info *port) 1016{ 1017 int i; 1018 int pi; 1019 unsigned int offset; 1020 unsigned long flags; 1021 struct fst_card_info *card; 1022 1023 pi = port->index; 1024 card = port->card; 1025 spin_lock_irqsave(&card->card_lock, flags); 1026 for (i = 0; i < NUM_RX_BUFFER; i++) { 1027 offset = BUF_OFFSET(rxBuffer[pi][i][0]); 1028 1029 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset); 1030 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16)); 1031 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER)); 1032 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER); 1033 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN); 1034 } 1035 port->rxpos = 0; 1036 spin_unlock_irqrestore(&card->card_lock, flags); 1037} 1038 1039/* 1040 * Setup port Tx buffers 1041 */ 1042static void 1043fst_tx_config(struct fst_port_info *port) 1044{ 1045 int i; 1046 int pi; 1047 unsigned int offset; 1048 unsigned long flags; 1049 struct fst_card_info *card; 1050 1051 pi = port->index; 1052 card = port->card; 1053 spin_lock_irqsave(&card->card_lock, flags); 1054 for (i = 0; i < NUM_TX_BUFFER; i++) { 1055 offset = BUF_OFFSET(txBuffer[pi][i][0]); 1056 1057 FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset); 1058 FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16)); 1059 FST_WRW(card, txDescrRing[pi][i].bcnt, 0); 1060 FST_WRB(card, txDescrRing[pi][i].bits, 0); 1061 } 1062 port->txpos = 0; 1063 port->txipos = 0; 1064 port->start = 0; 1065 spin_unlock_irqrestore(&card->card_lock, flags); 1066} 1067 1068/* TE1 Alarm change interrupt event 1069 */ 1070static void 1071fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port) 1072{ 1073 u8 los; 1074 u8 rra; 1075 u8 ais; 1076 1077 los = FST_RDB(card, suStatus.lossOfSignal); 1078 rra = FST_RDB(card, suStatus.receiveRemoteAlarm); 1079 ais = FST_RDB(card, suStatus.alarmIndicationSignal); 1080 1081 if (los) { 1082 /* 1083 * Lost the link 1084 */ 1085 if (netif_carrier_ok(port_to_dev(port))) { 1086 dbg(DBG_INTR, "Net carrier off\n"); 1087 netif_carrier_off(port_to_dev(port)); 1088 } 1089 } else { 1090 /* 1091 * Link available 1092 */ 1093 if (!netif_carrier_ok(port_to_dev(port))) { 1094 dbg(DBG_INTR, "Net carrier on\n"); 1095 netif_carrier_on(port_to_dev(port)); 1096 } 1097 } 1098 1099 if (los) 1100 dbg(DBG_INTR, "Assert LOS Alarm\n"); 1101 else 1102 dbg(DBG_INTR, "De-assert LOS Alarm\n"); 1103 if (rra) 1104 dbg(DBG_INTR, "Assert RRA Alarm\n"); 1105 else 1106 dbg(DBG_INTR, "De-assert RRA Alarm\n"); 1107 1108 if (ais) 1109 dbg(DBG_INTR, "Assert AIS Alarm\n"); 1110 else 1111 dbg(DBG_INTR, "De-assert AIS Alarm\n"); 1112} 1113 1114/* Control signal change interrupt event 1115 */ 1116static void 1117fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port) 1118{ 1119 int signals; 1120 1121 signals = FST_RDL(card, v24DebouncedSts[port->index]); 1122 1123 if (signals & (((port->hwif == X21) || (port->hwif == X21D)) 1124 ? IPSTS_INDICATE : IPSTS_DCD)) { 1125 if (!netif_carrier_ok(port_to_dev(port))) { 1126 dbg(DBG_INTR, "DCD active\n"); 1127 netif_carrier_on(port_to_dev(port)); 1128 } 1129 } else { 1130 if (netif_carrier_ok(port_to_dev(port))) { 1131 dbg(DBG_INTR, "DCD lost\n"); 1132 netif_carrier_off(port_to_dev(port)); 1133 } 1134 } 1135} 1136 1137/* Log Rx Errors 1138 */ 1139static void 1140fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port, 1141 unsigned char dmabits, int rxp, unsigned short len) 1142{ 1143 struct net_device *dev = port_to_dev(port); 1144 1145 /* 1146 * Increment the appropriate error counter 1147 */ 1148 dev->stats.rx_errors++; 1149 if (dmabits & RX_OFLO) { 1150 dev->stats.rx_fifo_errors++; 1151 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n", 1152 card->card_no, port->index, rxp); 1153 } 1154 if (dmabits & RX_CRC) { 1155 dev->stats.rx_crc_errors++; 1156 dbg(DBG_ASS, "Rx crc error on card %d port %d\n", 1157 card->card_no, port->index); 1158 } 1159 if (dmabits & RX_FRAM) { 1160 dev->stats.rx_frame_errors++; 1161 dbg(DBG_ASS, "Rx frame error on card %d port %d\n", 1162 card->card_no, port->index); 1163 } 1164 if (dmabits == (RX_STP | RX_ENP)) { 1165 dev->stats.rx_length_errors++; 1166 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n", 1167 len, card->card_no, port->index); 1168 } 1169} 1170 1171/* Rx Error Recovery 1172 */ 1173static void 1174fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port, 1175 unsigned char dmabits, int rxp, unsigned short len) 1176{ 1177 int i; 1178 int pi; 1179 1180 pi = port->index; 1181 /* 1182 * Discard buffer descriptors until we see the start of the 1183 * next frame. Note that for long frames this could be in 1184 * a subsequent interrupt. 1185 */ 1186 i = 0; 1187 while ((dmabits & (DMA_OWN | RX_STP)) == 0) { 1188 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1189 rxp = (rxp+1) % NUM_RX_BUFFER; 1190 if (++i > NUM_RX_BUFFER) { 1191 dbg(DBG_ASS, "intr_rx: Discarding more bufs" 1192 " than we have\n"); 1193 break; 1194 } 1195 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits); 1196 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits); 1197 } 1198 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i); 1199 1200 /* Discard the terminal buffer */ 1201 if (!(dmabits & DMA_OWN)) { 1202 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1203 rxp = (rxp+1) % NUM_RX_BUFFER; 1204 } 1205 port->rxpos = rxp; 1206 return; 1207 1208} 1209 1210/* Rx complete interrupt 1211 */ 1212static void 1213fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port) 1214{ 1215 unsigned char dmabits; 1216 int pi; 1217 int rxp; 1218 int rx_status; 1219 unsigned short len; 1220 struct sk_buff *skb; 1221 struct net_device *dev = port_to_dev(port); 1222 1223 /* Check we have a buffer to process */ 1224 pi = port->index; 1225 rxp = port->rxpos; 1226 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits); 1227 if (dmabits & DMA_OWN) { 1228 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n", 1229 pi, rxp); 1230 return; 1231 } 1232 if (card->dmarx_in_progress) { 1233 return; 1234 } 1235 1236 /* Get buffer length */ 1237 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt); 1238 /* Discard the CRC */ 1239 len -= 2; 1240 if (len == 0) { 1241 /* 1242 * This seems to happen on the TE1 interface sometimes 1243 * so throw the frame away and log the event. 1244 */ 1245 pr_err("Frame received with 0 length. Card %d Port %d\n", 1246 card->card_no, port->index); 1247 /* Return descriptor to card */ 1248 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1249 1250 rxp = (rxp+1) % NUM_RX_BUFFER; 1251 port->rxpos = rxp; 1252 return; 1253 } 1254 1255 /* Check buffer length and for other errors. We insist on one packet 1256 * in one buffer. This simplifies things greatly and since we've 1257 * allocated 8K it shouldn't be a real world limitation 1258 */ 1259 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len); 1260 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) { 1261 fst_log_rx_error(card, port, dmabits, rxp, len); 1262 fst_recover_rx_error(card, port, dmabits, rxp, len); 1263 return; 1264 } 1265 1266 /* Allocate SKB */ 1267 if ((skb = dev_alloc_skb(len)) == NULL) { 1268 dbg(DBG_RX, "intr_rx: can't allocate buffer\n"); 1269 1270 dev->stats.rx_dropped++; 1271 1272 /* Return descriptor to card */ 1273 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1274 1275 rxp = (rxp+1) % NUM_RX_BUFFER; 1276 port->rxpos = rxp; 1277 return; 1278 } 1279 1280 /* 1281 * We know the length we need to receive, len. 1282 * It's not worth using the DMA for reads of less than 1283 * FST_MIN_DMA_LEN 1284 */ 1285 1286 if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) { 1287 memcpy_fromio(skb_put(skb, len), 1288 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]), 1289 len); 1290 1291 /* Reset buffer descriptor */ 1292 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); 1293 1294 /* Update stats */ 1295 dev->stats.rx_packets++; 1296 dev->stats.rx_bytes += len; 1297 1298 /* Push upstream */ 1299 dbg(DBG_RX, "Pushing frame up the stack\n"); 1300 if (port->mode == FST_RAW) 1301 skb->protocol = farsync_type_trans(skb, dev); 1302 else 1303 skb->protocol = hdlc_type_trans(skb, dev); 1304 rx_status = netif_rx(skb); 1305 fst_process_rx_status(rx_status, port_to_dev(port)->name); 1306 if (rx_status == NET_RX_DROP) 1307 dev->stats.rx_dropped++; 1308 } else { 1309 card->dma_skb_rx = skb; 1310 card->dma_port_rx = port; 1311 card->dma_len_rx = len; 1312 card->dma_rxpos = rxp; 1313 fst_rx_dma(card, card->rx_dma_handle_card, 1314 BUF_OFFSET(rxBuffer[pi][rxp][0]), len); 1315 } 1316 if (rxp != port->rxpos) { 1317 dbg(DBG_ASS, "About to increment rxpos by more than 1\n"); 1318 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos); 1319 } 1320 rxp = (rxp+1) % NUM_RX_BUFFER; 1321 port->rxpos = rxp; 1322} 1323 1324/* 1325 * The bottom halfs to the ISR 1326 * 1327 */ 1328 1329static void 1330do_bottom_half_tx(struct fst_card_info *card) 1331{ 1332 struct fst_port_info *port; 1333 int pi; 1334 int txq_length; 1335 struct sk_buff *skb; 1336 unsigned long flags; 1337 struct net_device *dev; 1338 1339 /* 1340 * Find a free buffer for the transmit 1341 * Step through each port on this card 1342 */ 1343 1344 dbg(DBG_TX, "do_bottom_half_tx\n"); 1345 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { 1346 if (!port->run) 1347 continue; 1348 1349 dev = port_to_dev(port); 1350 while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) & 1351 DMA_OWN) && 1352 !(card->dmatx_in_progress)) { 1353 /* 1354 * There doesn't seem to be a txdone event per-se 1355 * We seem to have to deduce it, by checking the DMA_OWN 1356 * bit on the next buffer we think we can use 1357 */ 1358 spin_lock_irqsave(&card->card_lock, flags); 1359 if ((txq_length = port->txqe - port->txqs) < 0) { 1360 /* 1361 * This is the case where one has wrapped and the 1362 * maths gives us a negative number 1363 */ 1364 txq_length = txq_length + FST_TXQ_DEPTH; 1365 } 1366 spin_unlock_irqrestore(&card->card_lock, flags); 1367 if (txq_length > 0) { 1368 /* 1369 * There is something to send 1370 */ 1371 spin_lock_irqsave(&card->card_lock, flags); 1372 skb = port->txq[port->txqs]; 1373 port->txqs++; 1374 if (port->txqs == FST_TXQ_DEPTH) { 1375 port->txqs = 0; 1376 } 1377 spin_unlock_irqrestore(&card->card_lock, flags); 1378 /* 1379 * copy the data and set the required indicators on the 1380 * card. 1381 */ 1382 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt, 1383 cnv_bcnt(skb->len)); 1384 if ((skb->len < FST_MIN_DMA_LEN) || 1385 (card->family == FST_FAMILY_TXP)) { 1386 /* Enqueue the packet with normal io */ 1387 memcpy_toio(card->mem + 1388 BUF_OFFSET(txBuffer[pi] 1389 [port-> 1390 txpos][0]), 1391 skb->data, skb->len); 1392 FST_WRB(card, 1393 txDescrRing[pi][port->txpos]. 1394 bits, 1395 DMA_OWN | TX_STP | TX_ENP); 1396 dev->stats.tx_packets++; 1397 dev->stats.tx_bytes += skb->len; 1398 dev->trans_start = jiffies; 1399 } else { 1400 /* Or do it through dma */ 1401 memcpy(card->tx_dma_handle_host, 1402 skb->data, skb->len); 1403 card->dma_port_tx = port; 1404 card->dma_len_tx = skb->len; 1405 card->dma_txpos = port->txpos; 1406 fst_tx_dma(card, 1407 (char *) card-> 1408 tx_dma_handle_card, 1409 (char *) 1410 BUF_OFFSET(txBuffer[pi] 1411 [port->txpos][0]), 1412 skb->len); 1413 } 1414 if (++port->txpos >= NUM_TX_BUFFER) 1415 port->txpos = 0; 1416 /* 1417 * If we have flow control on, can we now release it? 1418 */ 1419 if (port->start) { 1420 if (txq_length < fst_txq_low) { 1421 netif_wake_queue(port_to_dev 1422 (port)); 1423 port->start = 0; 1424 } 1425 } 1426 dev_kfree_skb(skb); 1427 } else { 1428 /* 1429 * Nothing to send so break out of the while loop 1430 */ 1431 break; 1432 } 1433 } 1434 } 1435} 1436 1437static void 1438do_bottom_half_rx(struct fst_card_info *card) 1439{ 1440 struct fst_port_info *port; 1441 int pi; 1442 int rx_count = 0; 1443 1444 /* Check for rx completions on all ports on this card */ 1445 dbg(DBG_RX, "do_bottom_half_rx\n"); 1446 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { 1447 if (!port->run) 1448 continue; 1449 1450 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits) 1451 & DMA_OWN) && !(card->dmarx_in_progress)) { 1452 if (rx_count > fst_max_reads) { 1453 /* 1454 * Don't spend forever in receive processing 1455 * Schedule another event 1456 */ 1457 fst_q_work_item(&fst_work_intq, card->card_no); 1458 tasklet_schedule(&fst_int_task); 1459 break; /* Leave the loop */ 1460 } 1461 fst_intr_rx(card, port); 1462 rx_count++; 1463 } 1464 } 1465} 1466 1467/* 1468 * The interrupt service routine 1469 * Dev_id is our fst_card_info pointer 1470 */ 1471static irqreturn_t 1472fst_intr(int dummy, void *dev_id) 1473{ 1474 struct fst_card_info *card = dev_id; 1475 struct fst_port_info *port; 1476 int rdidx; /* Event buffer indices */ 1477 int wridx; 1478 int event; /* Actual event for processing */ 1479 unsigned int dma_intcsr = 0; 1480 unsigned int do_card_interrupt; 1481 unsigned int int_retry_count; 1482 1483 /* 1484 * Check to see if the interrupt was for this card 1485 * return if not 1486 * Note that the call to clear the interrupt is important 1487 */ 1488 dbg(DBG_INTR, "intr: %d %p\n", card->irq, card); 1489 if (card->state != FST_RUNNING) { 1490 pr_err("Interrupt received for card %d in a non running state (%d)\n", 1491 card->card_no, card->state); 1492 1493 /* 1494 * It is possible to really be running, i.e. we have re-loaded 1495 * a running card 1496 * Clear and reprime the interrupt source 1497 */ 1498 fst_clear_intr(card); 1499 return IRQ_HANDLED; 1500 } 1501 1502 /* Clear and reprime the interrupt source */ 1503 fst_clear_intr(card); 1504 1505 /* 1506 * Is the interrupt for this card (handshake == 1) 1507 */ 1508 do_card_interrupt = 0; 1509 if (FST_RDB(card, interruptHandshake) == 1) { 1510 do_card_interrupt += FST_CARD_INT; 1511 /* Set the software acknowledge */ 1512 FST_WRB(card, interruptHandshake, 0xEE); 1513 } 1514 if (card->family == FST_FAMILY_TXU) { 1515 /* 1516 * Is it a DMA Interrupt 1517 */ 1518 dma_intcsr = inl(card->pci_conf + INTCSR_9054); 1519 if (dma_intcsr & 0x00200000) { 1520 /* 1521 * DMA Channel 0 (Rx transfer complete) 1522 */ 1523 dbg(DBG_RX, "DMA Rx xfer complete\n"); 1524 outb(0x8, card->pci_conf + DMACSR0); 1525 fst_rx_dma_complete(card, card->dma_port_rx, 1526 card->dma_len_rx, card->dma_skb_rx, 1527 card->dma_rxpos); 1528 card->dmarx_in_progress = 0; 1529 do_card_interrupt += FST_RX_DMA_INT; 1530 } 1531 if (dma_intcsr & 0x00400000) { 1532 /* 1533 * DMA Channel 1 (Tx transfer complete) 1534 */ 1535 dbg(DBG_TX, "DMA Tx xfer complete\n"); 1536 outb(0x8, card->pci_conf + DMACSR1); 1537 fst_tx_dma_complete(card, card->dma_port_tx, 1538 card->dma_len_tx, card->dma_txpos); 1539 card->dmatx_in_progress = 0; 1540 do_card_interrupt += FST_TX_DMA_INT; 1541 } 1542 } 1543 1544 /* 1545 * Have we been missing Interrupts 1546 */ 1547 int_retry_count = FST_RDL(card, interruptRetryCount); 1548 if (int_retry_count) { 1549 dbg(DBG_ASS, "Card %d int_retry_count is %d\n", 1550 card->card_no, int_retry_count); 1551 FST_WRL(card, interruptRetryCount, 0); 1552 } 1553 1554 if (!do_card_interrupt) { 1555 return IRQ_HANDLED; 1556 } 1557 1558 /* Scehdule the bottom half of the ISR */ 1559 fst_q_work_item(&fst_work_intq, card->card_no); 1560 tasklet_schedule(&fst_int_task); 1561 1562 /* Drain the event queue */ 1563 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f; 1564 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f; 1565 while (rdidx != wridx) { 1566 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]); 1567 port = &card->ports[event & 0x03]; 1568 1569 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event); 1570 1571 switch (event) { 1572 case TE1_ALMA: 1573 dbg(DBG_INTR, "TE1 Alarm intr\n"); 1574 if (port->run) 1575 fst_intr_te1_alarm(card, port); 1576 break; 1577 1578 case CTLA_CHG: 1579 case CTLB_CHG: 1580 case CTLC_CHG: 1581 case CTLD_CHG: 1582 if (port->run) 1583 fst_intr_ctlchg(card, port); 1584 break; 1585 1586 case ABTA_SENT: 1587 case ABTB_SENT: 1588 case ABTC_SENT: 1589 case ABTD_SENT: 1590 dbg(DBG_TX, "Abort complete port %d\n", port->index); 1591 break; 1592 1593 case TXA_UNDF: 1594 case TXB_UNDF: 1595 case TXC_UNDF: 1596 case TXD_UNDF: 1597 /* Difficult to see how we'd get this given that we 1598 * always load up the entire packet for DMA. 1599 */ 1600 dbg(DBG_TX, "Tx underflow port %d\n", port->index); 1601 port_to_dev(port)->stats.tx_errors++; 1602 port_to_dev(port)->stats.tx_fifo_errors++; 1603 dbg(DBG_ASS, "Tx underflow on card %d port %d\n", 1604 card->card_no, port->index); 1605 break; 1606 1607 case INIT_CPLT: 1608 dbg(DBG_INIT, "Card init OK intr\n"); 1609 break; 1610 1611 case INIT_FAIL: 1612 dbg(DBG_INIT, "Card init FAILED intr\n"); 1613 card->state = FST_IFAILED; 1614 break; 1615 1616 default: 1617 pr_err("intr: unknown card event %d. ignored\n", event); 1618 break; 1619 } 1620 1621 /* Bump and wrap the index */ 1622 if (++rdidx >= MAX_CIRBUFF) 1623 rdidx = 0; 1624 } 1625 FST_WRB(card, interruptEvent.rdindex, rdidx); 1626 return IRQ_HANDLED; 1627} 1628 1629/* Check that the shared memory configuration is one that we can handle 1630 * and that some basic parameters are correct 1631 */ 1632static void 1633check_started_ok(struct fst_card_info *card) 1634{ 1635 int i; 1636 1637 /* Check structure version and end marker */ 1638 if (FST_RDW(card, smcVersion) != SMC_VERSION) { 1639 pr_err("Bad shared memory version %d expected %d\n", 1640 FST_RDW(card, smcVersion), SMC_VERSION); 1641 card->state = FST_BADVERSION; 1642 return; 1643 } 1644 if (FST_RDL(card, endOfSmcSignature) != END_SIG) { 1645 pr_err("Missing shared memory signature\n"); 1646 card->state = FST_BADVERSION; 1647 return; 1648 } 1649 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */ 1650 if ((i = FST_RDB(card, taskStatus)) == 0x01) { 1651 card->state = FST_RUNNING; 1652 } else if (i == 0xFF) { 1653 pr_err("Firmware initialisation failed. Card halted\n"); 1654 card->state = FST_HALTED; 1655 return; 1656 } else if (i != 0x00) { 1657 pr_err("Unknown firmware status 0x%x\n", i); 1658 card->state = FST_HALTED; 1659 return; 1660 } 1661 1662 /* Finally check the number of ports reported by firmware against the 1663 * number we assumed at card detection. Should never happen with 1664 * existing firmware etc so we just report it for the moment. 1665 */ 1666 if (FST_RDL(card, numberOfPorts) != card->nports) { 1667 pr_warning("Port count mismatch on card %d. " 1668 "Firmware thinks %d we say %d\n", 1669 card->card_no, 1670 FST_RDL(card, numberOfPorts), card->nports); 1671 } 1672} 1673 1674static int 1675set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port, 1676 struct fstioc_info *info) 1677{ 1678 int err; 1679 unsigned char my_framing; 1680 1681 /* Set things according to the user set valid flags 1682 * Several of the old options have been invalidated/replaced by the 1683 * generic hdlc package. 1684 */ 1685 err = 0; 1686 if (info->valid & FSTVAL_PROTO) { 1687 if (info->proto == FST_RAW) 1688 port->mode = FST_RAW; 1689 else 1690 port->mode = FST_GEN_HDLC; 1691 } 1692 1693 if (info->valid & FSTVAL_CABLE) 1694 err = -EINVAL; 1695 1696 if (info->valid & FSTVAL_SPEED) 1697 err = -EINVAL; 1698 1699 if (info->valid & FSTVAL_PHASE) 1700 FST_WRB(card, portConfig[port->index].invertClock, 1701 info->invertClock); 1702 if (info->valid & FSTVAL_MODE) 1703 FST_WRW(card, cardMode, info->cardMode); 1704 if (info->valid & FSTVAL_TE1) { 1705 FST_WRL(card, suConfig.dataRate, info->lineSpeed); 1706 FST_WRB(card, suConfig.clocking, info->clockSource); 1707 my_framing = FRAMING_E1; 1708 if (info->framing == E1) 1709 my_framing = FRAMING_E1; 1710 if (info->framing == T1) 1711 my_framing = FRAMING_T1; 1712 if (info->framing == J1) 1713 my_framing = FRAMING_J1; 1714 FST_WRB(card, suConfig.framing, my_framing); 1715 FST_WRB(card, suConfig.structure, info->structure); 1716 FST_WRB(card, suConfig.interface, info->interface); 1717 FST_WRB(card, suConfig.coding, info->coding); 1718 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut); 1719 FST_WRB(card, suConfig.equalizer, info->equalizer); 1720 FST_WRB(card, suConfig.transparentMode, info->transparentMode); 1721 FST_WRB(card, suConfig.loopMode, info->loopMode); 1722 FST_WRB(card, suConfig.range, info->range); 1723 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode); 1724 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode); 1725 FST_WRB(card, suConfig.startingSlot, info->startingSlot); 1726 FST_WRB(card, suConfig.losThreshold, info->losThreshold); 1727 if (info->idleCode) 1728 FST_WRB(card, suConfig.enableIdleCode, 1); 1729 else 1730 FST_WRB(card, suConfig.enableIdleCode, 0); 1731 FST_WRB(card, suConfig.idleCode, info->idleCode); 1732#if FST_DEBUG 1733 if (info->valid & FSTVAL_TE1) { 1734 printk("Setting TE1 data\n"); 1735 printk("Line Speed = %d\n", info->lineSpeed); 1736 printk("Start slot = %d\n", info->startingSlot); 1737 printk("Clock source = %d\n", info->clockSource); 1738 printk("Framing = %d\n", my_framing); 1739 printk("Structure = %d\n", info->structure); 1740 printk("interface = %d\n", info->interface); 1741 printk("Coding = %d\n", info->coding); 1742 printk("Line build out = %d\n", info->lineBuildOut); 1743 printk("Equaliser = %d\n", info->equalizer); 1744 printk("Transparent mode = %d\n", 1745 info->transparentMode); 1746 printk("Loop mode = %d\n", info->loopMode); 1747 printk("Range = %d\n", info->range); 1748 printk("Tx Buffer mode = %d\n", info->txBufferMode); 1749 printk("Rx Buffer mode = %d\n", info->rxBufferMode); 1750 printk("LOS Threshold = %d\n", info->losThreshold); 1751 printk("Idle Code = %d\n", info->idleCode); 1752 } 1753#endif 1754 } 1755#if FST_DEBUG 1756 if (info->valid & FSTVAL_DEBUG) { 1757 fst_debug_mask = info->debug; 1758 } 1759#endif 1760 1761 return err; 1762} 1763 1764static void 1765gather_conf_info(struct fst_card_info *card, struct fst_port_info *port, 1766 struct fstioc_info *info) 1767{ 1768 int i; 1769 1770 memset(info, 0, sizeof (struct fstioc_info)); 1771 1772 i = port->index; 1773 info->kernelVersion = LINUX_VERSION_CODE; 1774 info->nports = card->nports; 1775 info->type = card->type; 1776 info->state = card->state; 1777 info->proto = FST_GEN_HDLC; 1778 info->index = i; 1779#if FST_DEBUG 1780 info->debug = fst_debug_mask; 1781#endif 1782 1783 /* Only mark information as valid if card is running. 1784 * Copy the data anyway in case it is useful for diagnostics 1785 */ 1786 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD) 1787#if FST_DEBUG 1788 | FSTVAL_DEBUG 1789#endif 1790 ; 1791 1792 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface); 1793 info->internalClock = FST_RDB(card, portConfig[i].internalClock); 1794 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed); 1795 info->invertClock = FST_RDB(card, portConfig[i].invertClock); 1796 info->v24IpSts = FST_RDL(card, v24IpSts[i]); 1797 info->v24OpSts = FST_RDL(card, v24OpSts[i]); 1798 info->clockStatus = FST_RDW(card, clockStatus[i]); 1799 info->cableStatus = FST_RDW(card, cableStatus); 1800 info->cardMode = FST_RDW(card, cardMode); 1801 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion); 1802 1803 /* 1804 * The T2U can report cable presence for both A or B 1805 * in bits 0 and 1 of cableStatus. See which port we are and 1806 * do the mapping. 1807 */ 1808 if (card->family == FST_FAMILY_TXU) { 1809 if (port->index == 0) { 1810 /* 1811 * Port A 1812 */ 1813 info->cableStatus = info->cableStatus & 1; 1814 } else { 1815 /* 1816 * Port B 1817 */ 1818 info->cableStatus = info->cableStatus >> 1; 1819 info->cableStatus = info->cableStatus & 1; 1820 } 1821 } 1822 /* 1823 * Some additional bits if we are TE1 1824 */ 1825 if (card->type == FST_TYPE_TE1) { 1826 info->lineSpeed = FST_RDL(card, suConfig.dataRate); 1827 info->clockSource = FST_RDB(card, suConfig.clocking); 1828 info->framing = FST_RDB(card, suConfig.framing); 1829 info->structure = FST_RDB(card, suConfig.structure); 1830 info->interface = FST_RDB(card, suConfig.interface); 1831 info->coding = FST_RDB(card, suConfig.coding); 1832 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut); 1833 info->equalizer = FST_RDB(card, suConfig.equalizer); 1834 info->loopMode = FST_RDB(card, suConfig.loopMode); 1835 info->range = FST_RDB(card, suConfig.range); 1836 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode); 1837 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode); 1838 info->startingSlot = FST_RDB(card, suConfig.startingSlot); 1839 info->losThreshold = FST_RDB(card, suConfig.losThreshold); 1840 if (FST_RDB(card, suConfig.enableIdleCode)) 1841 info->idleCode = FST_RDB(card, suConfig.idleCode); 1842 else 1843 info->idleCode = 0; 1844 info->receiveBufferDelay = 1845 FST_RDL(card, suStatus.receiveBufferDelay); 1846 info->framingErrorCount = 1847 FST_RDL(card, suStatus.framingErrorCount); 1848 info->codeViolationCount = 1849 FST_RDL(card, suStatus.codeViolationCount); 1850 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount); 1851 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation); 1852 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal); 1853 info->receiveRemoteAlarm = 1854 FST_RDB(card, suStatus.receiveRemoteAlarm); 1855 info->alarmIndicationSignal = 1856 FST_RDB(card, suStatus.alarmIndicationSignal); 1857 } 1858} 1859 1860static int 1861fst_set_iface(struct fst_card_info *card, struct fst_port_info *port, 1862 struct ifreq *ifr) 1863{ 1864 sync_serial_settings sync; 1865 int i; 1866 1867 if (ifr->ifr_settings.size != sizeof (sync)) { 1868 return -ENOMEM; 1869 } 1870 1871 if (copy_from_user 1872 (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) { 1873 return -EFAULT; 1874 } 1875 1876 if (sync.loopback) 1877 return -EINVAL; 1878 1879 i = port->index; 1880 1881 switch (ifr->ifr_settings.type) { 1882 case IF_IFACE_V35: 1883 FST_WRW(card, portConfig[i].lineInterface, V35); 1884 port->hwif = V35; 1885 break; 1886 1887 case IF_IFACE_V24: 1888 FST_WRW(card, portConfig[i].lineInterface, V24); 1889 port->hwif = V24; 1890 break; 1891 1892 case IF_IFACE_X21: 1893 FST_WRW(card, portConfig[i].lineInterface, X21); 1894 port->hwif = X21; 1895 break; 1896 1897 case IF_IFACE_X21D: 1898 FST_WRW(card, portConfig[i].lineInterface, X21D); 1899 port->hwif = X21D; 1900 break; 1901 1902 case IF_IFACE_T1: 1903 FST_WRW(card, portConfig[i].lineInterface, T1); 1904 port->hwif = T1; 1905 break; 1906 1907 case IF_IFACE_E1: 1908 FST_WRW(card, portConfig[i].lineInterface, E1); 1909 port->hwif = E1; 1910 break; 1911 1912 case IF_IFACE_SYNC_SERIAL: 1913 break; 1914 1915 default: 1916 return -EINVAL; 1917 } 1918 1919 switch (sync.clock_type) { 1920 case CLOCK_EXT: 1921 FST_WRB(card, portConfig[i].internalClock, EXTCLK); 1922 break; 1923 1924 case CLOCK_INT: 1925 FST_WRB(card, portConfig[i].internalClock, INTCLK); 1926 break; 1927 1928 default: 1929 return -EINVAL; 1930 } 1931 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate); 1932 return 0; 1933} 1934 1935static int 1936fst_get_iface(struct fst_card_info *card, struct fst_port_info *port, 1937 struct ifreq *ifr) 1938{ 1939 sync_serial_settings sync; 1940 int i; 1941 1942 /* First check what line type is set, we'll default to reporting X.21 1943 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be 1944 * changed 1945 */ 1946 switch (port->hwif) { 1947 case E1: 1948 ifr->ifr_settings.type = IF_IFACE_E1; 1949 break; 1950 case T1: 1951 ifr->ifr_settings.type = IF_IFACE_T1; 1952 break; 1953 case V35: 1954 ifr->ifr_settings.type = IF_IFACE_V35; 1955 break; 1956 case V24: 1957 ifr->ifr_settings.type = IF_IFACE_V24; 1958 break; 1959 case X21D: 1960 ifr->ifr_settings.type = IF_IFACE_X21D; 1961 break; 1962 case X21: 1963 default: 1964 ifr->ifr_settings.type = IF_IFACE_X21; 1965 break; 1966 } 1967 if (ifr->ifr_settings.size == 0) { 1968 return 0; /* only type requested */ 1969 } 1970 if (ifr->ifr_settings.size < sizeof (sync)) { 1971 return -ENOMEM; 1972 } 1973 1974 i = port->index; 1975 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed); 1976 /* Lucky card and linux use same encoding here */ 1977 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) == 1978 INTCLK ? CLOCK_INT : CLOCK_EXT; 1979 sync.loopback = 0; 1980 1981 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) { 1982 return -EFAULT; 1983 } 1984 1985 ifr->ifr_settings.size = sizeof (sync); 1986 return 0; 1987} 1988 1989static int 1990fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1991{ 1992 struct fst_card_info *card; 1993 struct fst_port_info *port; 1994 struct fstioc_write wrthdr; 1995 struct fstioc_info info; 1996 unsigned long flags; 1997 void *buf; 1998 1999 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data); 2000 2001 port = dev_to_port(dev); 2002 card = port->card; 2003 2004 if (!capable(CAP_NET_ADMIN)) 2005 return -EPERM; 2006 2007 switch (cmd) { 2008 case FSTCPURESET: 2009 fst_cpureset(card); 2010 card->state = FST_RESET; 2011 return 0; 2012 2013 case FSTCPURELEASE: 2014 fst_cpurelease(card); 2015 card->state = FST_STARTING; 2016 return 0; 2017 2018 case FSTWRITE: /* Code write (download) */ 2019 2020 /* First copy in the header with the length and offset of data 2021 * to write 2022 */ 2023 if (ifr->ifr_data == NULL) { 2024 return -EINVAL; 2025 } 2026 if (copy_from_user(&wrthdr, ifr->ifr_data, 2027 sizeof (struct fstioc_write))) { 2028 return -EFAULT; 2029 } 2030 2031 /* Sanity check the parameters. We don't support partial writes 2032 * when going over the top 2033 */ 2034 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE || 2035 wrthdr.size + wrthdr.offset > FST_MEMSIZE) { 2036 return -ENXIO; 2037 } 2038 2039 /* Now copy the data to the card. */ 2040 2041 buf = memdup_user(ifr->ifr_data + sizeof(struct fstioc_write), 2042 wrthdr.size); 2043 if (IS_ERR(buf)) 2044 return PTR_ERR(buf); 2045 2046 memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size); 2047 kfree(buf); 2048 2049 /* Writes to the memory of a card in the reset state constitute 2050 * a download 2051 */ 2052 if (card->state == FST_RESET) { 2053 card->state = FST_DOWNLOAD; 2054 } 2055 return 0; 2056 2057 case FSTGETCONF: 2058 2059 /* If card has just been started check the shared memory config 2060 * version and marker 2061 */ 2062 if (card->state == FST_STARTING) { 2063 check_started_ok(card); 2064 2065 /* If everything checked out enable card interrupts */ 2066 if (card->state == FST_RUNNING) { 2067 spin_lock_irqsave(&card->card_lock, flags); 2068 fst_enable_intr(card); 2069 FST_WRB(card, interruptHandshake, 0xEE); 2070 spin_unlock_irqrestore(&card->card_lock, flags); 2071 } 2072 } 2073 2074 if (ifr->ifr_data == NULL) { 2075 return -EINVAL; 2076 } 2077 2078 gather_conf_info(card, port, &info); 2079 2080 if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) { 2081 return -EFAULT; 2082 } 2083 return 0; 2084 2085 case FSTSETCONF: 2086 2087 /* 2088 * Most of the settings have been moved to the generic ioctls 2089 * this just covers debug and board ident now 2090 */ 2091 2092 if (card->state != FST_RUNNING) { 2093 pr_err("Attempt to configure card %d in non-running state (%d)\n", 2094 card->card_no, card->state); 2095 return -EIO; 2096 } 2097 if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) { 2098 return -EFAULT; 2099 } 2100 2101 return set_conf_from_info(card, port, &info); 2102 2103 case SIOCWANDEV: 2104 switch (ifr->ifr_settings.type) { 2105 case IF_GET_IFACE: 2106 return fst_get_iface(card, port, ifr); 2107 2108 case IF_IFACE_SYNC_SERIAL: 2109 case IF_IFACE_V35: 2110 case IF_IFACE_V24: 2111 case IF_IFACE_X21: 2112 case IF_IFACE_X21D: 2113 case IF_IFACE_T1: 2114 case IF_IFACE_E1: 2115 return fst_set_iface(card, port, ifr); 2116 2117 case IF_PROTO_RAW: 2118 port->mode = FST_RAW; 2119 return 0; 2120 2121 case IF_GET_PROTO: 2122 if (port->mode == FST_RAW) { 2123 ifr->ifr_settings.type = IF_PROTO_RAW; 2124 return 0; 2125 } 2126 return hdlc_ioctl(dev, ifr, cmd); 2127 2128 default: 2129 port->mode = FST_GEN_HDLC; 2130 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n", 2131 ifr->ifr_settings.type); 2132 return hdlc_ioctl(dev, ifr, cmd); 2133 } 2134 2135 default: 2136 /* Not one of ours. Pass through to HDLC package */ 2137 return hdlc_ioctl(dev, ifr, cmd); 2138 } 2139} 2140 2141static void 2142fst_openport(struct fst_port_info *port) 2143{ 2144 int signals; 2145 int txq_length; 2146 2147 /* Only init things if card is actually running. This allows open to 2148 * succeed for downloads etc. 2149 */ 2150 if (port->card->state == FST_RUNNING) { 2151 if (port->run) { 2152 dbg(DBG_OPEN, "open: found port already running\n"); 2153 2154 fst_issue_cmd(port, STOPPORT); 2155 port->run = 0; 2156 } 2157 2158 fst_rx_config(port); 2159 fst_tx_config(port); 2160 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR); 2161 2162 fst_issue_cmd(port, STARTPORT); 2163 port->run = 1; 2164 2165 signals = FST_RDL(port->card, v24DebouncedSts[port->index]); 2166 if (signals & (((port->hwif == X21) || (port->hwif == X21D)) 2167 ? IPSTS_INDICATE : IPSTS_DCD)) 2168 netif_carrier_on(port_to_dev(port)); 2169 else 2170 netif_carrier_off(port_to_dev(port)); 2171 2172 txq_length = port->txqe - port->txqs; 2173 port->txqe = 0; 2174 port->txqs = 0; 2175 } 2176 2177} 2178 2179static void 2180fst_closeport(struct fst_port_info *port) 2181{ 2182 if (port->card->state == FST_RUNNING) { 2183 if (port->run) { 2184 port->run = 0; 2185 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR); 2186 2187 fst_issue_cmd(port, STOPPORT); 2188 } else { 2189 dbg(DBG_OPEN, "close: port not running\n"); 2190 } 2191 } 2192} 2193 2194static int 2195fst_open(struct net_device *dev) 2196{ 2197 int err; 2198 struct fst_port_info *port; 2199 2200 port = dev_to_port(dev); 2201 if (!try_module_get(THIS_MODULE)) 2202 return -EBUSY; 2203 2204 if (port->mode != FST_RAW) { 2205 err = hdlc_open(dev); 2206 if (err) 2207 return err; 2208 } 2209 2210 fst_openport(port); 2211 netif_wake_queue(dev); 2212 return 0; 2213} 2214 2215static int 2216fst_close(struct net_device *dev) 2217{ 2218 struct fst_port_info *port; 2219 struct fst_card_info *card; 2220 unsigned char tx_dma_done; 2221 unsigned char rx_dma_done; 2222 2223 port = dev_to_port(dev); 2224 card = port->card; 2225 2226 tx_dma_done = inb(card->pci_conf + DMACSR1); 2227 rx_dma_done = inb(card->pci_conf + DMACSR0); 2228 dbg(DBG_OPEN, 2229 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n", 2230 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress, 2231 rx_dma_done); 2232 2233 netif_stop_queue(dev); 2234 fst_closeport(dev_to_port(dev)); 2235 if (port->mode != FST_RAW) { 2236 hdlc_close(dev); 2237 } 2238 module_put(THIS_MODULE); 2239 return 0; 2240} 2241 2242static int 2243fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity) 2244{ 2245 /* 2246 * Setting currently fixed in FarSync card so we check and forget 2247 */ 2248 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT) 2249 return -EINVAL; 2250 return 0; 2251} 2252 2253static void 2254fst_tx_timeout(struct net_device *dev) 2255{ 2256 struct fst_port_info *port; 2257 struct fst_card_info *card; 2258 2259 port = dev_to_port(dev); 2260 card = port->card; 2261 dev->stats.tx_errors++; 2262 dev->stats.tx_aborted_errors++; 2263 dbg(DBG_ASS, "Tx timeout card %d port %d\n", 2264 card->card_no, port->index); 2265 fst_issue_cmd(port, ABORTTX); 2266 2267 dev->trans_start = jiffies; 2268 netif_wake_queue(dev); 2269 port->start = 0; 2270} 2271 2272static netdev_tx_t 2273fst_start_xmit(struct sk_buff *skb, struct net_device *dev) 2274{ 2275 struct fst_card_info *card; 2276 struct fst_port_info *port; 2277 unsigned long flags; 2278 int txq_length; 2279 2280 port = dev_to_port(dev); 2281 card = port->card; 2282 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len); 2283 2284 /* Drop packet with error if we don't have carrier */ 2285 if (!netif_carrier_ok(dev)) { 2286 dev_kfree_skb(skb); 2287 dev->stats.tx_errors++; 2288 dev->stats.tx_carrier_errors++; 2289 dbg(DBG_ASS, 2290 "Tried to transmit but no carrier on card %d port %d\n", 2291 card->card_no, port->index); 2292 return NETDEV_TX_OK; 2293 } 2294 2295 /* Drop it if it's too big! MTU failure ? */ 2296 if (skb->len > LEN_TX_BUFFER) { 2297 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len, 2298 LEN_TX_BUFFER); 2299 dev_kfree_skb(skb); 2300 dev->stats.tx_errors++; 2301 return NETDEV_TX_OK; 2302 } 2303 2304 /* 2305 * We are always going to queue the packet 2306 * so that the bottom half is the only place we tx from 2307 * Check there is room in the port txq 2308 */ 2309 spin_lock_irqsave(&card->card_lock, flags); 2310 if ((txq_length = port->txqe - port->txqs) < 0) { 2311 /* 2312 * This is the case where the next free has wrapped but the 2313 * last used hasn't 2314 */ 2315 txq_length = txq_length + FST_TXQ_DEPTH; 2316 } 2317 spin_unlock_irqrestore(&card->card_lock, flags); 2318 if (txq_length > fst_txq_high) { 2319 /* 2320 * We have got enough buffers in the pipeline. Ask the network 2321 * layer to stop sending frames down 2322 */ 2323 netif_stop_queue(dev); 2324 port->start = 1; /* I'm using this to signal stop sent up */ 2325 } 2326 2327 if (txq_length == FST_TXQ_DEPTH - 1) { 2328 /* 2329 * This shouldn't have happened but such is life 2330 */ 2331 dev_kfree_skb(skb); 2332 dev->stats.tx_errors++; 2333 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n", 2334 card->card_no, port->index); 2335 return NETDEV_TX_OK; 2336 } 2337 2338 /* 2339 * queue the buffer 2340 */ 2341 spin_lock_irqsave(&card->card_lock, flags); 2342 port->txq[port->txqe] = skb; 2343 port->txqe++; 2344 if (port->txqe == FST_TXQ_DEPTH) 2345 port->txqe = 0; 2346 spin_unlock_irqrestore(&card->card_lock, flags); 2347 2348 /* Scehdule the bottom half which now does transmit processing */ 2349 fst_q_work_item(&fst_work_txq, card->card_no); 2350 tasklet_schedule(&fst_tx_task); 2351 2352 return NETDEV_TX_OK; 2353} 2354 2355/* 2356 * Card setup having checked hardware resources. 2357 * Should be pretty bizarre if we get an error here (kernel memory 2358 * exhaustion is one possibility). If we do see a problem we report it 2359 * via a printk and leave the corresponding interface and all that follow 2360 * disabled. 2361 */ 2362static char *type_strings[] __devinitdata = { 2363 "no hardware", /* Should never be seen */ 2364 "FarSync T2P", 2365 "FarSync T4P", 2366 "FarSync T1U", 2367 "FarSync T2U", 2368 "FarSync T4U", 2369 "FarSync TE1" 2370}; 2371 2372static void __devinit 2373fst_init_card(struct fst_card_info *card) 2374{ 2375 int i; 2376 int err; 2377 2378 /* We're working on a number of ports based on the card ID. If the 2379 * firmware detects something different later (should never happen) 2380 * we'll have to revise it in some way then. 2381 */ 2382 for (i = 0; i < card->nports; i++) { 2383 err = register_hdlc_device(card->ports[i].dev); 2384 if (err < 0) { 2385 int j; 2386 pr_err("Cannot register HDLC device for port %d (errno %d)\n", 2387 i, -err); 2388 for (j = i; j < card->nports; j++) { 2389 free_netdev(card->ports[j].dev); 2390 card->ports[j].dev = NULL; 2391 } 2392 card->nports = i; 2393 break; 2394 } 2395 } 2396 2397 pr_info("%s-%s: %s IRQ%d, %d ports\n", 2398 port_to_dev(&card->ports[0])->name, 2399 port_to_dev(&card->ports[card->nports - 1])->name, 2400 type_strings[card->type], card->irq, card->nports); 2401} 2402 2403static const struct net_device_ops fst_ops = { 2404 .ndo_open = fst_open, 2405 .ndo_stop = fst_close, 2406 .ndo_change_mtu = hdlc_change_mtu, 2407 .ndo_start_xmit = hdlc_start_xmit, 2408 .ndo_do_ioctl = fst_ioctl, 2409 .ndo_tx_timeout = fst_tx_timeout, 2410}; 2411 2412/* 2413 * Initialise card when detected. 2414 * Returns 0 to indicate success, or errno otherwise. 2415 */ 2416static int __devinit 2417fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent) 2418{ 2419 static int no_of_cards_added = 0; 2420 struct fst_card_info *card; 2421 int err = 0; 2422 int i; 2423 2424 printk_once(KERN_INFO 2425 pr_fmt("FarSync WAN driver " FST_USER_VERSION 2426 " (c) 2001-2004 FarSite Communications Ltd.\n")); 2427#if FST_DEBUG 2428 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask); 2429#endif 2430 /* 2431 * We are going to be clever and allow certain cards not to be 2432 * configured. An exclude list can be provided in /etc/modules.conf 2433 */ 2434 if (fst_excluded_cards != 0) { 2435 /* 2436 * There are cards to exclude 2437 * 2438 */ 2439 for (i = 0; i < fst_excluded_cards; i++) { 2440 if ((pdev->devfn) >> 3 == fst_excluded_list[i]) { 2441 pr_info("FarSync PCI device %d not assigned\n", 2442 (pdev->devfn) >> 3); 2443 return -EBUSY; 2444 } 2445 } 2446 } 2447 2448 /* Allocate driver private data */ 2449 card = kzalloc(sizeof (struct fst_card_info), GFP_KERNEL); 2450 if (card == NULL) { 2451 pr_err("FarSync card found but insufficient memory for driver storage\n"); 2452 return -ENOMEM; 2453 } 2454 2455 /* Try to enable the device */ 2456 if ((err = pci_enable_device(pdev)) != 0) { 2457 pr_err("Failed to enable card. Err %d\n", -err); 2458 kfree(card); 2459 return err; 2460 } 2461 2462 if ((err = pci_request_regions(pdev, "FarSync")) !=0) { 2463 pr_err("Failed to allocate regions. Err %d\n", -err); 2464 pci_disable_device(pdev); 2465 kfree(card); 2466 return err; 2467 } 2468 2469 /* Get virtual addresses of memory regions */ 2470 card->pci_conf = pci_resource_start(pdev, 1); 2471 card->phys_mem = pci_resource_start(pdev, 2); 2472 card->phys_ctlmem = pci_resource_start(pdev, 3); 2473 if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) { 2474 pr_err("Physical memory remap failed\n"); 2475 pci_release_regions(pdev); 2476 pci_disable_device(pdev); 2477 kfree(card); 2478 return -ENODEV; 2479 } 2480 if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) { 2481 pr_err("Control memory remap failed\n"); 2482 pci_release_regions(pdev); 2483 pci_disable_device(pdev); 2484 kfree(card); 2485 return -ENODEV; 2486 } 2487 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem); 2488 2489 /* Register the interrupt handler */ 2490 if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) { 2491 pr_err("Unable to register interrupt %d\n", card->irq); 2492 pci_release_regions(pdev); 2493 pci_disable_device(pdev); 2494 iounmap(card->ctlmem); 2495 iounmap(card->mem); 2496 kfree(card); 2497 return -ENODEV; 2498 } 2499 2500 /* Record info we need */ 2501 card->irq = pdev->irq; 2502 card->type = ent->driver_data; 2503 card->family = ((ent->driver_data == FST_TYPE_T2P) || 2504 (ent->driver_data == FST_TYPE_T4P)) 2505 ? FST_FAMILY_TXP : FST_FAMILY_TXU; 2506 if ((ent->driver_data == FST_TYPE_T1U) || 2507 (ent->driver_data == FST_TYPE_TE1)) 2508 card->nports = 1; 2509 else 2510 card->nports = ((ent->driver_data == FST_TYPE_T2P) || 2511 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4; 2512 2513 card->state = FST_UNINIT; 2514 spin_lock_init ( &card->card_lock ); 2515 2516 for ( i = 0 ; i < card->nports ; i++ ) { 2517 struct net_device *dev = alloc_hdlcdev(&card->ports[i]); 2518 hdlc_device *hdlc; 2519 if (!dev) { 2520 while (i--) 2521 free_netdev(card->ports[i].dev); 2522 pr_err("FarSync: out of memory\n"); 2523 free_irq(card->irq, card); 2524 pci_release_regions(pdev); 2525 pci_disable_device(pdev); 2526 iounmap(card->ctlmem); 2527 iounmap(card->mem); 2528 kfree(card); 2529 return -ENODEV; 2530 } 2531 card->ports[i].dev = dev; 2532 card->ports[i].card = card; 2533 card->ports[i].index = i; 2534 card->ports[i].run = 0; 2535 2536 hdlc = dev_to_hdlc(dev); 2537 2538 /* Fill in the net device info */ 2539 /* Since this is a PCI setup this is purely 2540 * informational. Give them the buffer addresses 2541 * and basic card I/O. 2542 */ 2543 dev->mem_start = card->phys_mem 2544 + BUF_OFFSET ( txBuffer[i][0][0]); 2545 dev->mem_end = card->phys_mem 2546 + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER][0]); 2547 dev->base_addr = card->pci_conf; 2548 dev->irq = card->irq; 2549 2550 dev->netdev_ops = &fst_ops; 2551 dev->tx_queue_len = FST_TX_QUEUE_LEN; 2552 dev->watchdog_timeo = FST_TX_TIMEOUT; 2553 hdlc->attach = fst_attach; 2554 hdlc->xmit = fst_start_xmit; 2555 } 2556 2557 card->device = pdev; 2558 2559 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type, 2560 card->nports, card->irq); 2561 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n", 2562 card->pci_conf, card->phys_mem, card->phys_ctlmem); 2563 2564 /* Reset the card's processor */ 2565 fst_cpureset(card); 2566 card->state = FST_RESET; 2567 2568 /* Initialise DMA (if required) */ 2569 fst_init_dma(card); 2570 2571 /* Record driver data for later use */ 2572 pci_set_drvdata(pdev, card); 2573 2574 /* Remainder of card setup */ 2575 fst_card_array[no_of_cards_added] = card; 2576 card->card_no = no_of_cards_added++; /* Record instance and bump it */ 2577 fst_init_card(card); 2578 if (card->family == FST_FAMILY_TXU) { 2579 /* 2580 * Allocate a dma buffer for transmit and receives 2581 */ 2582 card->rx_dma_handle_host = 2583 pci_alloc_consistent(card->device, FST_MAX_MTU, 2584 &card->rx_dma_handle_card); 2585 if (card->rx_dma_handle_host == NULL) { 2586 pr_err("Could not allocate rx dma buffer\n"); 2587 fst_disable_intr(card); 2588 pci_release_regions(pdev); 2589 pci_disable_device(pdev); 2590 iounmap(card->ctlmem); 2591 iounmap(card->mem); 2592 kfree(card); 2593 return -ENOMEM; 2594 } 2595 card->tx_dma_handle_host = 2596 pci_alloc_consistent(card->device, FST_MAX_MTU, 2597 &card->tx_dma_handle_card); 2598 if (card->tx_dma_handle_host == NULL) { 2599 pr_err("Could not allocate tx dma buffer\n"); 2600 fst_disable_intr(card); 2601 pci_release_regions(pdev); 2602 pci_disable_device(pdev); 2603 iounmap(card->ctlmem); 2604 iounmap(card->mem); 2605 kfree(card); 2606 return -ENOMEM; 2607 } 2608 } 2609 return 0; /* Success */ 2610} 2611 2612/* 2613 * Cleanup and close down a card 2614 */ 2615static void __devexit 2616fst_remove_one(struct pci_dev *pdev) 2617{ 2618 struct fst_card_info *card; 2619 int i; 2620 2621 card = pci_get_drvdata(pdev); 2622 2623 for (i = 0; i < card->nports; i++) { 2624 struct net_device *dev = port_to_dev(&card->ports[i]); 2625 unregister_hdlc_device(dev); 2626 } 2627 2628 fst_disable_intr(card); 2629 free_irq(card->irq, card); 2630 2631 iounmap(card->ctlmem); 2632 iounmap(card->mem); 2633 pci_release_regions(pdev); 2634 if (card->family == FST_FAMILY_TXU) { 2635 /* 2636 * Free dma buffers 2637 */ 2638 pci_free_consistent(card->device, FST_MAX_MTU, 2639 card->rx_dma_handle_host, 2640 card->rx_dma_handle_card); 2641 pci_free_consistent(card->device, FST_MAX_MTU, 2642 card->tx_dma_handle_host, 2643 card->tx_dma_handle_card); 2644 } 2645 fst_card_array[card->card_no] = NULL; 2646} 2647 2648static struct pci_driver fst_driver = { 2649 .name = FST_NAME, 2650 .id_table = fst_pci_dev_id, 2651 .probe = fst_add_one, 2652 .remove = __devexit_p(fst_remove_one), 2653 .suspend = NULL, 2654 .resume = NULL, 2655}; 2656 2657static int __init 2658fst_init(void) 2659{ 2660 int i; 2661 2662 for (i = 0; i < FST_MAX_CARDS; i++) 2663 fst_card_array[i] = NULL; 2664 spin_lock_init(&fst_work_q_lock); 2665 return pci_register_driver(&fst_driver); 2666} 2667 2668static void __exit 2669fst_cleanup_module(void) 2670{ 2671 pr_info("FarSync WAN driver unloading\n"); 2672 pci_unregister_driver(&fst_driver); 2673} 2674 2675module_init(fst_init); 2676module_exit(fst_cleanup_module); 2677