1/* 2 * Copyright (C) 2003 - 2009 NetXen, Inc. 3 * Copyright (C) 2009 - QLogic Corporation. 4 * All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, 19 * MA 02111-1307, USA. 20 * 21 * The full GNU General Public License is included in this distribution 22 * in the file called "COPYING". 23 * 24 */ 25 26#include <linux/slab.h> 27#include "netxen_nic.h" 28#include "netxen_nic_hw.h" 29 30#include <net/ip.h> 31 32#define MASK(n) ((1ULL<<(n))-1) 33#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) 34#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) 35#define MS_WIN(addr) (addr & 0x0ffc0000) 36 37#define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 38 39#define CRB_BLK(off) ((off >> 20) & 0x3f) 40#define CRB_SUBBLK(off) ((off >> 16) & 0xf) 41#define CRB_WINDOW_2M (0x130060) 42#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000)) 43#define CRB_INDIRECT_2M (0x1e0000UL) 44 45static void netxen_nic_io_write_128M(struct netxen_adapter *adapter, 46 void __iomem *addr, u32 data); 47static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter, 48 void __iomem *addr); 49 50#ifndef readq 51static inline u64 readq(void __iomem *addr) 52{ 53 return readl(addr) | (((u64) readl(addr + 4)) << 32LL); 54} 55#endif 56 57#ifndef writeq 58static inline void writeq(u64 val, void __iomem *addr) 59{ 60 writel(((u32) (val)), (addr)); 61 writel(((u32) (val >> 32)), (addr + 4)); 62} 63#endif 64 65#define PCI_OFFSET_FIRST_RANGE(adapter, off) \ 66 ((adapter)->ahw.pci_base0 + (off)) 67#define PCI_OFFSET_SECOND_RANGE(adapter, off) \ 68 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START) 69#define PCI_OFFSET_THIRD_RANGE(adapter, off) \ 70 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START) 71 72static void __iomem *pci_base_offset(struct netxen_adapter *adapter, 73 unsigned long off) 74{ 75 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END)) 76 return PCI_OFFSET_FIRST_RANGE(adapter, off); 77 78 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END)) 79 return PCI_OFFSET_SECOND_RANGE(adapter, off); 80 81 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END)) 82 return PCI_OFFSET_THIRD_RANGE(adapter, off); 83 84 return NULL; 85} 86 87static crb_128M_2M_block_map_t 88crb_128M_2M_map[64] __cacheline_aligned_in_smp = { 89 {{{0, 0, 0, 0} } }, /* 0: PCI */ 90 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ 91 {1, 0x0110000, 0x0120000, 0x130000}, 92 {1, 0x0120000, 0x0122000, 0x124000}, 93 {1, 0x0130000, 0x0132000, 0x126000}, 94 {1, 0x0140000, 0x0142000, 0x128000}, 95 {1, 0x0150000, 0x0152000, 0x12a000}, 96 {1, 0x0160000, 0x0170000, 0x110000}, 97 {1, 0x0170000, 0x0172000, 0x12e000}, 98 {0, 0x0000000, 0x0000000, 0x000000}, 99 {0, 0x0000000, 0x0000000, 0x000000}, 100 {0, 0x0000000, 0x0000000, 0x000000}, 101 {0, 0x0000000, 0x0000000, 0x000000}, 102 {0, 0x0000000, 0x0000000, 0x000000}, 103 {0, 0x0000000, 0x0000000, 0x000000}, 104 {1, 0x01e0000, 0x01e0800, 0x122000}, 105 {0, 0x0000000, 0x0000000, 0x000000} } }, 106 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ 107 {{{0, 0, 0, 0} } }, /* 3: */ 108 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ 109 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ 110 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ 111 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ 112 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ 113 {0, 0x0000000, 0x0000000, 0x000000}, 114 {0, 0x0000000, 0x0000000, 0x000000}, 115 {0, 0x0000000, 0x0000000, 0x000000}, 116 {0, 0x0000000, 0x0000000, 0x000000}, 117 {0, 0x0000000, 0x0000000, 0x000000}, 118 {0, 0x0000000, 0x0000000, 0x000000}, 119 {0, 0x0000000, 0x0000000, 0x000000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {0, 0x0000000, 0x0000000, 0x000000}, 122 {0, 0x0000000, 0x0000000, 0x000000}, 123 {0, 0x0000000, 0x0000000, 0x000000}, 124 {0, 0x0000000, 0x0000000, 0x000000}, 125 {0, 0x0000000, 0x0000000, 0x000000}, 126 {0, 0x0000000, 0x0000000, 0x000000}, 127 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 128 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ 129 {0, 0x0000000, 0x0000000, 0x000000}, 130 {0, 0x0000000, 0x0000000, 0x000000}, 131 {0, 0x0000000, 0x0000000, 0x000000}, 132 {0, 0x0000000, 0x0000000, 0x000000}, 133 {0, 0x0000000, 0x0000000, 0x000000}, 134 {0, 0x0000000, 0x0000000, 0x000000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 144 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ 145 {0, 0x0000000, 0x0000000, 0x000000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {0, 0x0000000, 0x0000000, 0x000000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 160 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ 161 {0, 0x0000000, 0x0000000, 0x000000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {0, 0x0000000, 0x0000000, 0x000000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 176 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ 177 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ 178 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ 179 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ 180 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ 181 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ 182 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ 183 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ 184 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ 185 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ 186 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ 187 {{{0, 0, 0, 0} } }, /* 23: */ 188 {{{0, 0, 0, 0} } }, /* 24: */ 189 {{{0, 0, 0, 0} } }, /* 25: */ 190 {{{0, 0, 0, 0} } }, /* 26: */ 191 {{{0, 0, 0, 0} } }, /* 27: */ 192 {{{0, 0, 0, 0} } }, /* 28: */ 193 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ 194 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ 195 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ 196 {{{0} } }, /* 32: PCI */ 197 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ 198 {1, 0x2110000, 0x2120000, 0x130000}, 199 {1, 0x2120000, 0x2122000, 0x124000}, 200 {1, 0x2130000, 0x2132000, 0x126000}, 201 {1, 0x2140000, 0x2142000, 0x128000}, 202 {1, 0x2150000, 0x2152000, 0x12a000}, 203 {1, 0x2160000, 0x2170000, 0x110000}, 204 {1, 0x2170000, 0x2172000, 0x12e000}, 205 {0, 0x0000000, 0x0000000, 0x000000}, 206 {0, 0x0000000, 0x0000000, 0x000000}, 207 {0, 0x0000000, 0x0000000, 0x000000}, 208 {0, 0x0000000, 0x0000000, 0x000000}, 209 {0, 0x0000000, 0x0000000, 0x000000}, 210 {0, 0x0000000, 0x0000000, 0x000000}, 211 {0, 0x0000000, 0x0000000, 0x000000}, 212 {0, 0x0000000, 0x0000000, 0x000000} } }, 213 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ 214 {{{0} } }, /* 35: */ 215 {{{0} } }, /* 36: */ 216 {{{0} } }, /* 37: */ 217 {{{0} } }, /* 38: */ 218 {{{0} } }, /* 39: */ 219 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ 220 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ 221 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ 222 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ 223 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ 224 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ 225 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ 226 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ 227 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ 228 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ 229 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ 230 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ 231 {{{0} } }, /* 52: */ 232 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ 233 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ 234 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ 235 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ 236 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ 237 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ 238 {{{0} } }, /* 59: I2C0 */ 239 {{{0} } }, /* 60: I2C1 */ 240 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */ 241 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ 242 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ 243}; 244 245/* 246 * top 12 bits of crb internal address (hub, agent) 247 */ 248static unsigned crb_hub_agt[64] = 249{ 250 0, 251 NETXEN_HW_CRB_HUB_AGT_ADR_PS, 252 NETXEN_HW_CRB_HUB_AGT_ADR_MN, 253 NETXEN_HW_CRB_HUB_AGT_ADR_MS, 254 0, 255 NETXEN_HW_CRB_HUB_AGT_ADR_SRE, 256 NETXEN_HW_CRB_HUB_AGT_ADR_NIU, 257 NETXEN_HW_CRB_HUB_AGT_ADR_QMN, 258 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0, 259 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1, 260 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2, 261 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3, 262 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, 263 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, 264 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, 265 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4, 266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, 267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0, 268 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1, 269 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2, 270 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3, 271 NETXEN_HW_CRB_HUB_AGT_ADR_PGND, 272 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI, 273 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0, 274 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1, 275 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2, 276 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3, 277 0, 278 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI, 279 NETXEN_HW_CRB_HUB_AGT_ADR_SN, 280 0, 281 NETXEN_HW_CRB_HUB_AGT_ADR_EG, 282 0, 283 NETXEN_HW_CRB_HUB_AGT_ADR_PS, 284 NETXEN_HW_CRB_HUB_AGT_ADR_CAM, 285 0, 286 0, 287 0, 288 0, 289 0, 290 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, 291 0, 292 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1, 293 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2, 294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3, 295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4, 296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5, 297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6, 298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7, 299 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, 300 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, 301 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, 302 0, 303 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0, 304 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8, 305 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9, 306 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0, 307 0, 308 NETXEN_HW_CRB_HUB_AGT_ADR_SMB, 309 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0, 310 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1, 311 0, 312 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC, 313 0, 314}; 315 316/* PCI Windowing for DDR regions. */ 317 318#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ 319 320#define NETXEN_PCIE_SEM_TIMEOUT 10000 321 322int 323netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg) 324{ 325 int done = 0, timeout = 0; 326 327 while (!done) { 328 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem))); 329 if (done == 1) 330 break; 331 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT) 332 return -EIO; 333 msleep(1); 334 } 335 336 if (id_reg) 337 NXWR32(adapter, id_reg, adapter->portnum); 338 339 return 0; 340} 341 342void 343netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem) 344{ 345 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem))); 346} 347 348int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port) 349{ 350 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { 351 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447); 352 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5); 353 } 354 355 return 0; 356} 357 358/* Disable an XG interface */ 359int netxen_niu_disable_xg_port(struct netxen_adapter *adapter) 360{ 361 __u32 mac_cfg; 362 u32 port = adapter->physical_port; 363 364 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) 365 return 0; 366 367 if (port > NETXEN_NIU_MAX_XG_PORTS) 368 return -EINVAL; 369 370 mac_cfg = 0; 371 if (NXWR32(adapter, 372 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg)) 373 return -EIO; 374 return 0; 375} 376 377#define NETXEN_UNICAST_ADDR(port, index) \ 378 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8)) 379#define NETXEN_MCAST_ADDR(port, index) \ 380 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8)) 381#define MAC_HI(addr) \ 382 ((addr[2] << 16) | (addr[1] << 8) | (addr[0])) 383#define MAC_LO(addr) \ 384 ((addr[5] << 16) | (addr[4] << 8) | (addr[3])) 385 386int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode) 387{ 388 u32 mac_cfg; 389 u32 cnt = 0; 390 __u32 reg = 0x0200; 391 u32 port = adapter->physical_port; 392 u16 board_type = adapter->ahw.board_type; 393 394 if (port > NETXEN_NIU_MAX_XG_PORTS) 395 return -EINVAL; 396 397 mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port)); 398 mac_cfg &= ~0x4; 399 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg); 400 401 if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) || 402 (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ)) 403 reg = (0x20 << port); 404 405 NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg); 406 407 mdelay(10); 408 409 while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20) 410 mdelay(10); 411 412 if (cnt < 20) { 413 414 reg = NXRD32(adapter, 415 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port)); 416 417 if (mode == NETXEN_NIU_PROMISC_MODE) 418 reg = (reg | 0x2000UL); 419 else 420 reg = (reg & ~0x2000UL); 421 422 if (mode == NETXEN_NIU_ALLMULTI_MODE) 423 reg = (reg | 0x1000UL); 424 else 425 reg = (reg & ~0x1000UL); 426 427 NXWR32(adapter, 428 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg); 429 } 430 431 mac_cfg |= 0x4; 432 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg); 433 434 return 0; 435} 436 437int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr) 438{ 439 u32 mac_hi, mac_lo; 440 u32 reg_hi, reg_lo; 441 442 u8 phy = adapter->physical_port; 443 444 if (phy >= NETXEN_NIU_MAX_XG_PORTS) 445 return -EINVAL; 446 447 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24); 448 mac_hi = addr[2] | ((u32)addr[3] << 8) | 449 ((u32)addr[4] << 16) | ((u32)addr[5] << 24); 450 451 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy); 452 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy); 453 454 /* write twice to flush */ 455 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi)) 456 return -EIO; 457 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi)) 458 return -EIO; 459 460 return 0; 461} 462 463static int 464netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter) 465{ 466 u32 val = 0; 467 u16 port = adapter->physical_port; 468 u8 *addr = adapter->mac_addr; 469 470 if (adapter->mc_enabled) 471 return 0; 472 473 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); 474 val |= (1UL << (28+port)); 475 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); 476 477 /* add broadcast addr to filter */ 478 val = 0xffffff; 479 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); 480 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); 481 482 /* add station addr to filter */ 483 val = MAC_HI(addr); 484 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val); 485 val = MAC_LO(addr); 486 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val); 487 488 adapter->mc_enabled = 1; 489 return 0; 490} 491 492static int 493netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter) 494{ 495 u32 val = 0; 496 u16 port = adapter->physical_port; 497 u8 *addr = adapter->mac_addr; 498 499 if (!adapter->mc_enabled) 500 return 0; 501 502 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG); 503 val &= ~(1UL << (28+port)); 504 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); 505 506 val = MAC_HI(addr); 507 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val); 508 val = MAC_LO(addr); 509 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val); 510 511 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0); 512 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0); 513 514 adapter->mc_enabled = 0; 515 return 0; 516} 517 518static int 519netxen_nic_set_mcast_addr(struct netxen_adapter *adapter, 520 int index, u8 *addr) 521{ 522 u32 hi = 0, lo = 0; 523 u16 port = adapter->physical_port; 524 525 lo = MAC_LO(addr); 526 hi = MAC_HI(addr); 527 528 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi); 529 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo); 530 531 return 0; 532} 533 534void netxen_p2_nic_set_multi(struct net_device *netdev) 535{ 536 struct netxen_adapter *adapter = netdev_priv(netdev); 537 struct netdev_hw_addr *ha; 538 u8 null_addr[6]; 539 int i; 540 541 memset(null_addr, 0, 6); 542 543 if (netdev->flags & IFF_PROMISC) { 544 545 adapter->set_promisc(adapter, 546 NETXEN_NIU_PROMISC_MODE); 547 548 /* Full promiscuous mode */ 549 netxen_nic_disable_mcast_filter(adapter); 550 551 return; 552 } 553 554 if (netdev_mc_empty(netdev)) { 555 adapter->set_promisc(adapter, 556 NETXEN_NIU_NON_PROMISC_MODE); 557 netxen_nic_disable_mcast_filter(adapter); 558 return; 559 } 560 561 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE); 562 if (netdev->flags & IFF_ALLMULTI || 563 netdev_mc_count(netdev) > adapter->max_mc_count) { 564 netxen_nic_disable_mcast_filter(adapter); 565 return; 566 } 567 568 netxen_nic_enable_mcast_filter(adapter); 569 570 i = 0; 571 netdev_for_each_mc_addr(ha, netdev) 572 netxen_nic_set_mcast_addr(adapter, i++, ha->addr); 573 574 /* Clear out remaining addresses */ 575 while (i < adapter->max_mc_count) 576 netxen_nic_set_mcast_addr(adapter, i++, null_addr); 577} 578 579static int 580netxen_send_cmd_descs(struct netxen_adapter *adapter, 581 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc) 582{ 583 u32 i, producer, consumer; 584 struct netxen_cmd_buffer *pbuf; 585 struct cmd_desc_type0 *cmd_desc; 586 struct nx_host_tx_ring *tx_ring; 587 588 i = 0; 589 590 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) 591 return -EIO; 592 593 tx_ring = adapter->tx_ring; 594 __netif_tx_lock_bh(tx_ring->txq); 595 596 producer = tx_ring->producer; 597 consumer = tx_ring->sw_consumer; 598 599 if (nr_desc >= netxen_tx_avail(tx_ring)) { 600 netif_tx_stop_queue(tx_ring->txq); 601 __netif_tx_unlock_bh(tx_ring->txq); 602 return -EBUSY; 603 } 604 605 do { 606 cmd_desc = &cmd_desc_arr[i]; 607 608 pbuf = &tx_ring->cmd_buf_arr[producer]; 609 pbuf->skb = NULL; 610 pbuf->frag_count = 0; 611 612 memcpy(&tx_ring->desc_head[producer], 613 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0)); 614 615 producer = get_next_index(producer, tx_ring->num_desc); 616 i++; 617 618 } while (i != nr_desc); 619 620 tx_ring->producer = producer; 621 622 netxen_nic_update_cmd_producer(adapter, tx_ring); 623 624 __netif_tx_unlock_bh(tx_ring->txq); 625 626 return 0; 627} 628 629static int 630nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op) 631{ 632 nx_nic_req_t req; 633 nx_mac_req_t *mac_req; 634 u64 word; 635 636 memset(&req, 0, sizeof(nx_nic_req_t)); 637 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23); 638 639 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16); 640 req.req_hdr = cpu_to_le64(word); 641 642 mac_req = (nx_mac_req_t *)&req.words[0]; 643 mac_req->op = op; 644 memcpy(mac_req->mac_addr, addr, 6); 645 646 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 647} 648 649static int nx_p3_nic_add_mac(struct netxen_adapter *adapter, 650 u8 *addr, struct list_head *del_list) 651{ 652 struct list_head *head; 653 nx_mac_list_t *cur; 654 655 /* look up if already exists */ 656 list_for_each(head, del_list) { 657 cur = list_entry(head, nx_mac_list_t, list); 658 659 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) { 660 list_move_tail(head, &adapter->mac_list); 661 return 0; 662 } 663 } 664 665 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC); 666 if (cur == NULL) { 667 printk(KERN_ERR "%s: failed to add mac address filter\n", 668 adapter->netdev->name); 669 return -ENOMEM; 670 } 671 memcpy(cur->mac_addr, addr, ETH_ALEN); 672 list_add_tail(&cur->list, &adapter->mac_list); 673 return nx_p3_sre_macaddr_change(adapter, 674 cur->mac_addr, NETXEN_MAC_ADD); 675} 676 677void netxen_p3_nic_set_multi(struct net_device *netdev) 678{ 679 struct netxen_adapter *adapter = netdev_priv(netdev); 680 struct netdev_hw_addr *ha; 681 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 682 u32 mode = VPORT_MISS_MODE_DROP; 683 LIST_HEAD(del_list); 684 struct list_head *head; 685 nx_mac_list_t *cur; 686 687 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC) 688 return; 689 690 list_splice_tail_init(&adapter->mac_list, &del_list); 691 692 nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list); 693 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list); 694 695 if (netdev->flags & IFF_PROMISC) { 696 mode = VPORT_MISS_MODE_ACCEPT_ALL; 697 goto send_fw_cmd; 698 } 699 700 if ((netdev->flags & IFF_ALLMULTI) || 701 (netdev_mc_count(netdev) > adapter->max_mc_count)) { 702 mode = VPORT_MISS_MODE_ACCEPT_MULTI; 703 goto send_fw_cmd; 704 } 705 706 if (!netdev_mc_empty(netdev)) { 707 netdev_for_each_mc_addr(ha, netdev) 708 nx_p3_nic_add_mac(adapter, ha->addr, &del_list); 709 } 710 711send_fw_cmd: 712 adapter->set_promisc(adapter, mode); 713 head = &del_list; 714 while (!list_empty(head)) { 715 cur = list_entry(head->next, nx_mac_list_t, list); 716 717 nx_p3_sre_macaddr_change(adapter, 718 cur->mac_addr, NETXEN_MAC_DEL); 719 list_del(&cur->list); 720 kfree(cur); 721 } 722} 723 724int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode) 725{ 726 nx_nic_req_t req; 727 u64 word; 728 729 memset(&req, 0, sizeof(nx_nic_req_t)); 730 731 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 732 733 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE | 734 ((u64)adapter->portnum << 16); 735 req.req_hdr = cpu_to_le64(word); 736 737 req.words[0] = cpu_to_le64(mode); 738 739 return netxen_send_cmd_descs(adapter, 740 (struct cmd_desc_type0 *)&req, 1); 741} 742 743void netxen_p3_free_mac_list(struct netxen_adapter *adapter) 744{ 745 nx_mac_list_t *cur; 746 struct list_head *head = &adapter->mac_list; 747 748 while (!list_empty(head)) { 749 cur = list_entry(head->next, nx_mac_list_t, list); 750 nx_p3_sre_macaddr_change(adapter, 751 cur->mac_addr, NETXEN_MAC_DEL); 752 list_del(&cur->list); 753 kfree(cur); 754 } 755} 756 757int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr) 758{ 759 /* assuming caller has already copied new addr to netdev */ 760 netxen_p3_nic_set_multi(adapter->netdev); 761 return 0; 762} 763 764#define NETXEN_CONFIG_INTR_COALESCE 3 765 766/* 767 * Send the interrupt coalescing parameter set by ethtool to the card. 768 */ 769int netxen_config_intr_coalesce(struct netxen_adapter *adapter) 770{ 771 nx_nic_req_t req; 772 u64 word[6]; 773 int rv, i; 774 775 memset(&req, 0, sizeof(nx_nic_req_t)); 776 memset(word, 0, sizeof(word)); 777 778 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 779 780 word[0] = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16); 781 req.req_hdr = cpu_to_le64(word[0]); 782 783 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal)); 784 for (i = 0; i < 6; i++) 785 req.words[i] = cpu_to_le64(word[i]); 786 787 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 788 if (rv != 0) { 789 printk(KERN_ERR "ERROR. Could not send " 790 "interrupt coalescing parameters\n"); 791 } 792 793 return rv; 794} 795 796int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable) 797{ 798 nx_nic_req_t req; 799 u64 word; 800 int rv = 0; 801 802 if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable) 803 return 0; 804 805 memset(&req, 0, sizeof(nx_nic_req_t)); 806 807 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 808 809 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16); 810 req.req_hdr = cpu_to_le64(word); 811 812 req.words[0] = cpu_to_le64(enable); 813 814 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 815 if (rv != 0) { 816 printk(KERN_ERR "ERROR. Could not send " 817 "configure hw lro request\n"); 818 } 819 820 adapter->flags ^= NETXEN_NIC_LRO_ENABLED; 821 822 return rv; 823} 824 825int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable) 826{ 827 nx_nic_req_t req; 828 u64 word; 829 int rv = 0; 830 831 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable) 832 return rv; 833 834 memset(&req, 0, sizeof(nx_nic_req_t)); 835 836 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 837 838 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING | 839 ((u64)adapter->portnum << 16); 840 req.req_hdr = cpu_to_le64(word); 841 842 req.words[0] = cpu_to_le64(enable); 843 844 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 845 if (rv != 0) { 846 printk(KERN_ERR "ERROR. Could not send " 847 "configure bridge mode request\n"); 848 } 849 850 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED; 851 852 return rv; 853} 854 855 856#define RSS_HASHTYPE_IP_TCP 0x3 857 858int netxen_config_rss(struct netxen_adapter *adapter, int enable) 859{ 860 nx_nic_req_t req; 861 u64 word; 862 int i, rv; 863 864 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL, 865 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, 866 0x255b0ec26d5a56daULL }; 867 868 869 memset(&req, 0, sizeof(nx_nic_req_t)); 870 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 871 872 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16); 873 req.req_hdr = cpu_to_le64(word); 874 875 /* 876 * RSS request: 877 * bits 3-0: hash_method 878 * 5-4: hash_type_ipv4 879 * 7-6: hash_type_ipv6 880 * 8: enable 881 * 9: use indirection table 882 * 47-10: reserved 883 * 63-48: indirection table mask 884 */ 885 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) | 886 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) | 887 ((u64)(enable & 0x1) << 8) | 888 ((0x7ULL) << 48); 889 req.words[0] = cpu_to_le64(word); 890 for (i = 0; i < 5; i++) 891 req.words[i+1] = cpu_to_le64(key[i]); 892 893 894 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 895 if (rv != 0) { 896 printk(KERN_ERR "%s: could not configure RSS\n", 897 adapter->netdev->name); 898 } 899 900 return rv; 901} 902 903int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd) 904{ 905 nx_nic_req_t req; 906 u64 word; 907 int rv; 908 909 memset(&req, 0, sizeof(nx_nic_req_t)); 910 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 911 912 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16); 913 req.req_hdr = cpu_to_le64(word); 914 915 req.words[0] = cpu_to_le64(cmd); 916 req.words[1] = cpu_to_le64(ip); 917 918 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 919 if (rv != 0) { 920 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n", 921 adapter->netdev->name, 922 (cmd == NX_IP_UP) ? "Add" : "Remove", ip); 923 } 924 return rv; 925} 926 927int netxen_linkevent_request(struct netxen_adapter *adapter, int enable) 928{ 929 nx_nic_req_t req; 930 u64 word; 931 int rv; 932 933 memset(&req, 0, sizeof(nx_nic_req_t)); 934 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 935 936 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16); 937 req.req_hdr = cpu_to_le64(word); 938 req.words[0] = cpu_to_le64(enable | (enable << 8)); 939 940 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 941 if (rv != 0) { 942 printk(KERN_ERR "%s: could not configure link notification\n", 943 adapter->netdev->name); 944 } 945 946 return rv; 947} 948 949int netxen_send_lro_cleanup(struct netxen_adapter *adapter) 950{ 951 nx_nic_req_t req; 952 u64 word; 953 int rv; 954 955 memset(&req, 0, sizeof(nx_nic_req_t)); 956 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23); 957 958 word = NX_NIC_H2C_OPCODE_LRO_REQUEST | 959 ((u64)adapter->portnum << 16) | 960 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ; 961 962 req.req_hdr = cpu_to_le64(word); 963 964 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1); 965 if (rv != 0) { 966 printk(KERN_ERR "%s: could not cleanup lro flows\n", 967 adapter->netdev->name); 968 } 969 return rv; 970} 971 972/* 973 * netxen_nic_change_mtu - Change the Maximum Transfer Unit 974 * @returns 0 on success, negative on failure 975 */ 976 977#define MTU_FUDGE_FACTOR 100 978 979int netxen_nic_change_mtu(struct net_device *netdev, int mtu) 980{ 981 struct netxen_adapter *adapter = netdev_priv(netdev); 982 int max_mtu; 983 int rc = 0; 984 985 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) 986 max_mtu = P3_MAX_MTU; 987 else 988 max_mtu = P2_MAX_MTU; 989 990 if (mtu > max_mtu) { 991 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n", 992 netdev->name, max_mtu); 993 return -EINVAL; 994 } 995 996 if (adapter->set_mtu) 997 rc = adapter->set_mtu(adapter, mtu); 998 999 if (!rc) 1000 netdev->mtu = mtu; 1001 1002 return rc; 1003} 1004 1005static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, 1006 int size, __le32 * buf) 1007{ 1008 int i, v, addr; 1009 __le32 *ptr32; 1010 1011 addr = base; 1012 ptr32 = buf; 1013 for (i = 0; i < size / sizeof(u32); i++) { 1014 if (netxen_rom_fast_read(adapter, addr, &v) == -1) 1015 return -1; 1016 *ptr32 = cpu_to_le32(v); 1017 ptr32++; 1018 addr += sizeof(u32); 1019 } 1020 if ((char *)buf + size > (char *)ptr32) { 1021 __le32 local; 1022 if (netxen_rom_fast_read(adapter, addr, &v) == -1) 1023 return -1; 1024 local = cpu_to_le32(v); 1025 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32); 1026 } 1027 1028 return 0; 1029} 1030 1031int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac) 1032{ 1033 __le32 *pmac = (__le32 *) mac; 1034 u32 offset; 1035 1036 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64)); 1037 1038 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1) 1039 return -1; 1040 1041 if (*mac == cpu_to_le64(~0ULL)) { 1042 1043 offset = NX_OLD_MAC_ADDR_OFFSET + 1044 (adapter->portnum * sizeof(u64)); 1045 1046 if (netxen_get_flash_block(adapter, 1047 offset, sizeof(u64), pmac) == -1) 1048 return -1; 1049 1050 if (*mac == cpu_to_le64(~0ULL)) 1051 return -1; 1052 } 1053 return 0; 1054} 1055 1056int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac) 1057{ 1058 uint32_t crbaddr, mac_hi, mac_lo; 1059 int pci_func = adapter->ahw.pci_func; 1060 1061 crbaddr = CRB_MAC_BLOCK_START + 1062 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1)); 1063 1064 mac_lo = NXRD32(adapter, crbaddr); 1065 mac_hi = NXRD32(adapter, crbaddr+4); 1066 1067 if (pci_func & 1) 1068 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16)); 1069 else 1070 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32)); 1071 1072 return 0; 1073} 1074 1075/* 1076 * Changes the CRB window to the specified window. 1077 */ 1078static void 1079netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter, 1080 u32 window) 1081{ 1082 void __iomem *offset; 1083 int count = 10; 1084 u8 func = adapter->ahw.pci_func; 1085 1086 if (adapter->ahw.crb_win == window) 1087 return; 1088 1089 offset = PCI_OFFSET_SECOND_RANGE(adapter, 1090 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func))); 1091 1092 writel(window, offset); 1093 do { 1094 if (window == readl(offset)) 1095 break; 1096 1097 if (printk_ratelimit()) 1098 dev_warn(&adapter->pdev->dev, 1099 "failed to set CRB window to %d\n", 1100 (window == NETXEN_WINDOW_ONE)); 1101 udelay(1); 1102 1103 } while (--count > 0); 1104 1105 if (count > 0) 1106 adapter->ahw.crb_win = window; 1107} 1108 1109/* 1110 * Returns < 0 if off is not valid, 1111 * 1 if window access is needed. 'off' is set to offset from 1112 * CRB space in 128M pci map 1113 * 0 if no window access is needed. 'off' is set to 2M addr 1114 * In: 'off' is offset from base in 128M pci map 1115 */ 1116static int 1117netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, 1118 ulong off, void __iomem **addr) 1119{ 1120 crb_128M_2M_sub_block_map_t *m; 1121 1122 1123 if ((off >= NETXEN_CRB_MAX) || (off < NETXEN_PCI_CRBSPACE)) 1124 return -EINVAL; 1125 1126 off -= NETXEN_PCI_CRBSPACE; 1127 1128 /* 1129 * Try direct map 1130 */ 1131 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)]; 1132 1133 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) { 1134 *addr = adapter->ahw.pci_base0 + m->start_2M + 1135 (off - m->start_128M); 1136 return 0; 1137 } 1138 1139 /* 1140 * Not in direct map, use crb window 1141 */ 1142 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + 1143 (off & MASK(16)); 1144 return 1; 1145} 1146 1147/* 1148 * In: 'off' is offset from CRB space in 128M pci map 1149 * Out: 'off' is 2M pci map addr 1150 * side effect: lock crb window 1151 */ 1152static void 1153netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong off) 1154{ 1155 u32 window; 1156 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M; 1157 1158 off -= NETXEN_PCI_CRBSPACE; 1159 1160 window = CRB_HI(off); 1161 1162 writel(window, addr); 1163 if (readl(addr) != window) { 1164 if (printk_ratelimit()) 1165 dev_warn(&adapter->pdev->dev, 1166 "failed to set CRB window to %d off 0x%lx\n", 1167 window, off); 1168 } 1169} 1170 1171static void __iomem * 1172netxen_nic_map_indirect_address_128M(struct netxen_adapter *adapter, 1173 ulong win_off, void __iomem **mem_ptr) 1174{ 1175 ulong off = win_off; 1176 void __iomem *addr; 1177 resource_size_t mem_base; 1178 1179 if (ADDR_IN_WINDOW1(win_off)) 1180 off = NETXEN_CRB_NORMAL(win_off); 1181 1182 addr = pci_base_offset(adapter, off); 1183 if (addr) 1184 return addr; 1185 1186 if (adapter->ahw.pci_len0 == 0) 1187 off -= NETXEN_PCI_CRBSPACE; 1188 1189 mem_base = pci_resource_start(adapter->pdev, 0); 1190 *mem_ptr = ioremap(mem_base + (off & PAGE_MASK), PAGE_SIZE); 1191 if (*mem_ptr) 1192 addr = *mem_ptr + (off & (PAGE_SIZE - 1)); 1193 1194 return addr; 1195} 1196 1197static int 1198netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data) 1199{ 1200 unsigned long flags; 1201 void __iomem *addr, *mem_ptr = NULL; 1202 1203 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr); 1204 if (!addr) 1205 return -EIO; 1206 1207 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ 1208 netxen_nic_io_write_128M(adapter, addr, data); 1209 } else { /* Window 0 */ 1210 write_lock_irqsave(&adapter->ahw.crb_lock, flags); 1211 netxen_nic_pci_set_crbwindow_128M(adapter, 0); 1212 writel(data, addr); 1213 netxen_nic_pci_set_crbwindow_128M(adapter, 1214 NETXEN_WINDOW_ONE); 1215 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); 1216 } 1217 1218 if (mem_ptr) 1219 iounmap(mem_ptr); 1220 1221 return 0; 1222} 1223 1224static u32 1225netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off) 1226{ 1227 unsigned long flags; 1228 void __iomem *addr, *mem_ptr = NULL; 1229 u32 data; 1230 1231 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr); 1232 if (!addr) 1233 return -EIO; 1234 1235 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ 1236 data = netxen_nic_io_read_128M(adapter, addr); 1237 } else { /* Window 0 */ 1238 write_lock_irqsave(&adapter->ahw.crb_lock, flags); 1239 netxen_nic_pci_set_crbwindow_128M(adapter, 0); 1240 data = readl(addr); 1241 netxen_nic_pci_set_crbwindow_128M(adapter, 1242 NETXEN_WINDOW_ONE); 1243 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); 1244 } 1245 1246 if (mem_ptr) 1247 iounmap(mem_ptr); 1248 1249 return data; 1250} 1251 1252static int 1253netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data) 1254{ 1255 unsigned long flags; 1256 int rv; 1257 void __iomem *addr = NULL; 1258 1259 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr); 1260 1261 if (rv == 0) { 1262 writel(data, addr); 1263 return 0; 1264 } 1265 1266 if (rv > 0) { 1267 /* indirect access */ 1268 write_lock_irqsave(&adapter->ahw.crb_lock, flags); 1269 crb_win_lock(adapter); 1270 netxen_nic_pci_set_crbwindow_2M(adapter, off); 1271 writel(data, addr); 1272 crb_win_unlock(adapter); 1273 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); 1274 return 0; 1275 } 1276 1277 dev_err(&adapter->pdev->dev, 1278 "%s: invalid offset: 0x%016lx\n", __func__, off); 1279 dump_stack(); 1280 return -EIO; 1281} 1282 1283static u32 1284netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off) 1285{ 1286 unsigned long flags; 1287 int rv; 1288 u32 data; 1289 void __iomem *addr = NULL; 1290 1291 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr); 1292 1293 if (rv == 0) 1294 return readl(addr); 1295 1296 if (rv > 0) { 1297 /* indirect access */ 1298 write_lock_irqsave(&adapter->ahw.crb_lock, flags); 1299 crb_win_lock(adapter); 1300 netxen_nic_pci_set_crbwindow_2M(adapter, off); 1301 data = readl(addr); 1302 crb_win_unlock(adapter); 1303 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags); 1304 return data; 1305 } 1306 1307 dev_err(&adapter->pdev->dev, 1308 "%s: invalid offset: 0x%016lx\n", __func__, off); 1309 dump_stack(); 1310 return -1; 1311} 1312 1313/* window 1 registers only */ 1314static void netxen_nic_io_write_128M(struct netxen_adapter *adapter, 1315 void __iomem *addr, u32 data) 1316{ 1317 read_lock(&adapter->ahw.crb_lock); 1318 writel(data, addr); 1319 read_unlock(&adapter->ahw.crb_lock); 1320} 1321 1322static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter, 1323 void __iomem *addr) 1324{ 1325 u32 val; 1326 1327 read_lock(&adapter->ahw.crb_lock); 1328 val = readl(addr); 1329 read_unlock(&adapter->ahw.crb_lock); 1330 1331 return val; 1332} 1333 1334static void netxen_nic_io_write_2M(struct netxen_adapter *adapter, 1335 void __iomem *addr, u32 data) 1336{ 1337 writel(data, addr); 1338} 1339 1340static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter, 1341 void __iomem *addr) 1342{ 1343 return readl(addr); 1344} 1345 1346void __iomem * 1347netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset) 1348{ 1349 void __iomem *addr = NULL; 1350 1351 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { 1352 if ((offset < NETXEN_CRB_PCIX_HOST2) && 1353 (offset > NETXEN_CRB_PCIX_HOST)) 1354 addr = PCI_OFFSET_SECOND_RANGE(adapter, offset); 1355 else 1356 addr = NETXEN_CRB_NORMALIZE(adapter, offset); 1357 } else { 1358 WARN_ON(netxen_nic_pci_get_crb_addr_2M(adapter, 1359 offset, &addr)); 1360 } 1361 1362 return addr; 1363} 1364 1365static int 1366netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter, 1367 u64 addr, u32 *start) 1368{ 1369 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { 1370 *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0); 1371 return 0; 1372 } else if (ADDR_IN_RANGE(addr, 1373 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { 1374 *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1); 1375 return 0; 1376 } 1377 1378 return -EIO; 1379} 1380 1381static int 1382netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, 1383 u64 addr, u32 *start) 1384{ 1385 u32 window; 1386 1387 window = OCM_WIN(addr); 1388 1389 writel(window, adapter->ahw.ocm_win_crb); 1390 /* read back to flush */ 1391 readl(adapter->ahw.ocm_win_crb); 1392 1393 adapter->ahw.ocm_win = window; 1394 *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr); 1395 return 0; 1396} 1397 1398static int 1399netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off, 1400 u64 *data, int op) 1401{ 1402 void __iomem *addr, *mem_ptr = NULL; 1403 resource_size_t mem_base; 1404 int ret; 1405 u32 start; 1406 1407 spin_lock(&adapter->ahw.mem_lock); 1408 1409 ret = adapter->pci_set_window(adapter, off, &start); 1410 if (ret != 0) 1411 goto unlock; 1412 1413 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { 1414 addr = adapter->ahw.pci_base0 + start; 1415 } else { 1416 addr = pci_base_offset(adapter, start); 1417 if (addr) 1418 goto noremap; 1419 1420 mem_base = pci_resource_start(adapter->pdev, 0) + 1421 (start & PAGE_MASK); 1422 mem_ptr = ioremap(mem_base, PAGE_SIZE); 1423 if (mem_ptr == NULL) { 1424 ret = -EIO; 1425 goto unlock; 1426 } 1427 1428 addr = mem_ptr + (start & (PAGE_SIZE-1)); 1429 } 1430noremap: 1431 if (op == 0) /* read */ 1432 *data = readq(addr); 1433 else /* write */ 1434 writeq(*data, addr); 1435 1436unlock: 1437 spin_unlock(&adapter->ahw.mem_lock); 1438 1439 if (mem_ptr) 1440 iounmap(mem_ptr); 1441 return ret; 1442} 1443 1444void 1445netxen_pci_camqm_read_2M(struct netxen_adapter *adapter, u64 off, u64 *data) 1446{ 1447 void __iomem *addr = adapter->ahw.pci_base0 + 1448 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM); 1449 1450 spin_lock(&adapter->ahw.mem_lock); 1451 *data = readq(addr); 1452 spin_unlock(&adapter->ahw.mem_lock); 1453} 1454 1455void 1456netxen_pci_camqm_write_2M(struct netxen_adapter *adapter, u64 off, u64 data) 1457{ 1458 void __iomem *addr = adapter->ahw.pci_base0 + 1459 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM); 1460 1461 spin_lock(&adapter->ahw.mem_lock); 1462 writeq(data, addr); 1463 spin_unlock(&adapter->ahw.mem_lock); 1464} 1465 1466#define MAX_CTL_CHECK 1000 1467 1468static int 1469netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, 1470 u64 off, u64 data) 1471{ 1472 int j, ret; 1473 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo; 1474 void __iomem *mem_crb; 1475 1476 /* Only 64-bit aligned access */ 1477 if (off & 7) 1478 return -EIO; 1479 1480 /* P2 has different SIU and MIU test agent base addr */ 1481 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, 1482 NETXEN_ADDR_QDR_NET_MAX_P2)) { 1483 mem_crb = pci_base_offset(adapter, 1484 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE); 1485 addr_hi = SIU_TEST_AGT_ADDR_HI; 1486 data_lo = SIU_TEST_AGT_WRDATA_LO; 1487 data_hi = SIU_TEST_AGT_WRDATA_HI; 1488 off_lo = off & SIU_TEST_AGT_ADDR_MASK; 1489 off_hi = SIU_TEST_AGT_UPPER_ADDR(off); 1490 goto correct; 1491 } 1492 1493 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { 1494 mem_crb = pci_base_offset(adapter, 1495 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); 1496 addr_hi = MIU_TEST_AGT_ADDR_HI; 1497 data_lo = MIU_TEST_AGT_WRDATA_LO; 1498 data_hi = MIU_TEST_AGT_WRDATA_HI; 1499 off_lo = off & MIU_TEST_AGT_ADDR_MASK; 1500 off_hi = 0; 1501 goto correct; 1502 } 1503 1504 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) || 1505 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { 1506 if (adapter->ahw.pci_len0 != 0) { 1507 return netxen_nic_pci_mem_access_direct(adapter, 1508 off, &data, 1); 1509 } 1510 } 1511 1512 return -EIO; 1513 1514correct: 1515 spin_lock(&adapter->ahw.mem_lock); 1516 netxen_nic_pci_set_crbwindow_128M(adapter, 0); 1517 1518 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO)); 1519 writel(off_hi, (mem_crb + addr_hi)); 1520 writel(data & 0xffffffff, (mem_crb + data_lo)); 1521 writel((data >> 32) & 0xffffffff, (mem_crb + data_hi)); 1522 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL)); 1523 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE), 1524 (mem_crb + TEST_AGT_CTRL)); 1525 1526 for (j = 0; j < MAX_CTL_CHECK; j++) { 1527 temp = readl((mem_crb + TEST_AGT_CTRL)); 1528 if ((temp & TA_CTL_BUSY) == 0) 1529 break; 1530 } 1531 1532 if (j >= MAX_CTL_CHECK) { 1533 if (printk_ratelimit()) 1534 dev_err(&adapter->pdev->dev, 1535 "failed to write through agent\n"); 1536 ret = -EIO; 1537 } else 1538 ret = 0; 1539 1540 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE); 1541 spin_unlock(&adapter->ahw.mem_lock); 1542 return ret; 1543} 1544 1545static int 1546netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, 1547 u64 off, u64 *data) 1548{ 1549 int j, ret; 1550 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo; 1551 u64 val; 1552 void __iomem *mem_crb; 1553 1554 /* Only 64-bit aligned access */ 1555 if (off & 7) 1556 return -EIO; 1557 1558 /* P2 has different SIU and MIU test agent base addr */ 1559 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, 1560 NETXEN_ADDR_QDR_NET_MAX_P2)) { 1561 mem_crb = pci_base_offset(adapter, 1562 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE); 1563 addr_hi = SIU_TEST_AGT_ADDR_HI; 1564 data_lo = SIU_TEST_AGT_RDDATA_LO; 1565 data_hi = SIU_TEST_AGT_RDDATA_HI; 1566 off_lo = off & SIU_TEST_AGT_ADDR_MASK; 1567 off_hi = SIU_TEST_AGT_UPPER_ADDR(off); 1568 goto correct; 1569 } 1570 1571 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { 1572 mem_crb = pci_base_offset(adapter, 1573 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); 1574 addr_hi = MIU_TEST_AGT_ADDR_HI; 1575 data_lo = MIU_TEST_AGT_RDDATA_LO; 1576 data_hi = MIU_TEST_AGT_RDDATA_HI; 1577 off_lo = off & MIU_TEST_AGT_ADDR_MASK; 1578 off_hi = 0; 1579 goto correct; 1580 } 1581 1582 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) || 1583 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { 1584 if (adapter->ahw.pci_len0 != 0) { 1585 return netxen_nic_pci_mem_access_direct(adapter, 1586 off, data, 0); 1587 } 1588 } 1589 1590 return -EIO; 1591 1592correct: 1593 spin_lock(&adapter->ahw.mem_lock); 1594 netxen_nic_pci_set_crbwindow_128M(adapter, 0); 1595 1596 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO)); 1597 writel(off_hi, (mem_crb + addr_hi)); 1598 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL)); 1599 writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL)); 1600 1601 for (j = 0; j < MAX_CTL_CHECK; j++) { 1602 temp = readl(mem_crb + TEST_AGT_CTRL); 1603 if ((temp & TA_CTL_BUSY) == 0) 1604 break; 1605 } 1606 1607 if (j >= MAX_CTL_CHECK) { 1608 if (printk_ratelimit()) 1609 dev_err(&adapter->pdev->dev, 1610 "failed to read through agent\n"); 1611 ret = -EIO; 1612 } else { 1613 1614 temp = readl(mem_crb + data_hi); 1615 val = ((u64)temp << 32); 1616 val |= readl(mem_crb + data_lo); 1617 *data = val; 1618 ret = 0; 1619 } 1620 1621 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE); 1622 spin_unlock(&adapter->ahw.mem_lock); 1623 1624 return ret; 1625} 1626 1627static int 1628netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, 1629 u64 off, u64 data) 1630{ 1631 int j, ret; 1632 u32 temp, off8; 1633 void __iomem *mem_crb; 1634 1635 /* Only 64-bit aligned access */ 1636 if (off & 7) 1637 return -EIO; 1638 1639 /* P3 onward, test agent base for MIU and SIU is same */ 1640 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, 1641 NETXEN_ADDR_QDR_NET_MAX_P3)) { 1642 mem_crb = netxen_get_ioaddr(adapter, 1643 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE); 1644 goto correct; 1645 } 1646 1647 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { 1648 mem_crb = netxen_get_ioaddr(adapter, 1649 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); 1650 goto correct; 1651 } 1652 1653 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) 1654 return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1); 1655 1656 return -EIO; 1657 1658correct: 1659 off8 = off & 0xfffffff8; 1660 1661 spin_lock(&adapter->ahw.mem_lock); 1662 1663 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO)); 1664 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); 1665 1666 writel(data & 0xffffffff, 1667 mem_crb + MIU_TEST_AGT_WRDATA_LO); 1668 writel((data >> 32) & 0xffffffff, 1669 mem_crb + MIU_TEST_AGT_WRDATA_HI); 1670 1671 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL)); 1672 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE), 1673 (mem_crb + TEST_AGT_CTRL)); 1674 1675 for (j = 0; j < MAX_CTL_CHECK; j++) { 1676 temp = readl(mem_crb + TEST_AGT_CTRL); 1677 if ((temp & TA_CTL_BUSY) == 0) 1678 break; 1679 } 1680 1681 if (j >= MAX_CTL_CHECK) { 1682 if (printk_ratelimit()) 1683 dev_err(&adapter->pdev->dev, 1684 "failed to write through agent\n"); 1685 ret = -EIO; 1686 } else 1687 ret = 0; 1688 1689 spin_unlock(&adapter->ahw.mem_lock); 1690 1691 return ret; 1692} 1693 1694static int 1695netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, 1696 u64 off, u64 *data) 1697{ 1698 int j, ret; 1699 u32 temp, off8; 1700 u64 val; 1701 void __iomem *mem_crb; 1702 1703 /* Only 64-bit aligned access */ 1704 if (off & 7) 1705 return -EIO; 1706 1707 /* P3 onward, test agent base for MIU and SIU is same */ 1708 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, 1709 NETXEN_ADDR_QDR_NET_MAX_P3)) { 1710 mem_crb = netxen_get_ioaddr(adapter, 1711 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE); 1712 goto correct; 1713 } 1714 1715 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { 1716 mem_crb = netxen_get_ioaddr(adapter, 1717 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE); 1718 goto correct; 1719 } 1720 1721 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { 1722 return netxen_nic_pci_mem_access_direct(adapter, 1723 off, data, 0); 1724 } 1725 1726 return -EIO; 1727 1728correct: 1729 off8 = off & 0xfffffff8; 1730 1731 spin_lock(&adapter->ahw.mem_lock); 1732 1733 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO)); 1734 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI)); 1735 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL)); 1736 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL)); 1737 1738 for (j = 0; j < MAX_CTL_CHECK; j++) { 1739 temp = readl(mem_crb + TEST_AGT_CTRL); 1740 if ((temp & TA_CTL_BUSY) == 0) 1741 break; 1742 } 1743 1744 if (j >= MAX_CTL_CHECK) { 1745 if (printk_ratelimit()) 1746 dev_err(&adapter->pdev->dev, 1747 "failed to read through agent\n"); 1748 ret = -EIO; 1749 } else { 1750 val = (u64)(readl(mem_crb + MIU_TEST_AGT_RDDATA_HI)) << 32; 1751 val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO); 1752 *data = val; 1753 ret = 0; 1754 } 1755 1756 spin_unlock(&adapter->ahw.mem_lock); 1757 1758 return ret; 1759} 1760 1761void 1762netxen_setup_hwops(struct netxen_adapter *adapter) 1763{ 1764 adapter->init_port = netxen_niu_xg_init_port; 1765 adapter->stop_port = netxen_niu_disable_xg_port; 1766 1767 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { 1768 adapter->crb_read = netxen_nic_hw_read_wx_128M, 1769 adapter->crb_write = netxen_nic_hw_write_wx_128M, 1770 adapter->pci_set_window = netxen_nic_pci_set_window_128M, 1771 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M, 1772 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M, 1773 adapter->io_read = netxen_nic_io_read_128M, 1774 adapter->io_write = netxen_nic_io_write_128M, 1775 1776 adapter->macaddr_set = netxen_p2_nic_set_mac_addr; 1777 adapter->set_multi = netxen_p2_nic_set_multi; 1778 adapter->set_mtu = netxen_nic_set_mtu_xgb; 1779 adapter->set_promisc = netxen_p2_nic_set_promisc; 1780 1781 } else { 1782 adapter->crb_read = netxen_nic_hw_read_wx_2M, 1783 adapter->crb_write = netxen_nic_hw_write_wx_2M, 1784 adapter->pci_set_window = netxen_nic_pci_set_window_2M, 1785 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M, 1786 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M, 1787 adapter->io_read = netxen_nic_io_read_2M, 1788 adapter->io_write = netxen_nic_io_write_2M, 1789 1790 adapter->set_mtu = nx_fw_cmd_set_mtu; 1791 adapter->set_promisc = netxen_p3_nic_set_promisc; 1792 adapter->macaddr_set = netxen_p3_nic_set_mac_addr; 1793 adapter->set_multi = netxen_p3_nic_set_multi; 1794 1795 adapter->phy_read = nx_fw_cmd_query_phy; 1796 adapter->phy_write = nx_fw_cmd_set_phy; 1797 } 1798} 1799 1800int netxen_nic_get_board_info(struct netxen_adapter *adapter) 1801{ 1802 int offset, board_type, magic; 1803 struct pci_dev *pdev = adapter->pdev; 1804 1805 offset = NX_FW_MAGIC_OFFSET; 1806 if (netxen_rom_fast_read(adapter, offset, &magic)) 1807 return -EIO; 1808 1809 if (magic != NETXEN_BDINFO_MAGIC) { 1810 dev_err(&pdev->dev, "invalid board config, magic=%08x\n", 1811 magic); 1812 return -EIO; 1813 } 1814 1815 offset = NX_BRDTYPE_OFFSET; 1816 if (netxen_rom_fast_read(adapter, offset, &board_type)) 1817 return -EIO; 1818 1819 adapter->ahw.board_type = board_type; 1820 1821 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) { 1822 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I); 1823 if ((gpio & 0x8000) == 0) 1824 board_type = NETXEN_BRDTYPE_P3_10G_TP; 1825 } 1826 1827 switch (board_type) { 1828 case NETXEN_BRDTYPE_P2_SB35_4G: 1829 adapter->ahw.port_type = NETXEN_NIC_GBE; 1830 break; 1831 case NETXEN_BRDTYPE_P2_SB31_10G: 1832 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: 1833 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ: 1834 case NETXEN_BRDTYPE_P2_SB31_10G_CX4: 1835 case NETXEN_BRDTYPE_P3_HMEZ: 1836 case NETXEN_BRDTYPE_P3_XG_LOM: 1837 case NETXEN_BRDTYPE_P3_10G_CX4: 1838 case NETXEN_BRDTYPE_P3_10G_CX4_LP: 1839 case NETXEN_BRDTYPE_P3_IMEZ: 1840 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: 1841 case NETXEN_BRDTYPE_P3_10G_SFP_CT: 1842 case NETXEN_BRDTYPE_P3_10G_SFP_QT: 1843 case NETXEN_BRDTYPE_P3_10G_XFP: 1844 case NETXEN_BRDTYPE_P3_10000_BASE_T: 1845 adapter->ahw.port_type = NETXEN_NIC_XGBE; 1846 break; 1847 case NETXEN_BRDTYPE_P1_BD: 1848 case NETXEN_BRDTYPE_P1_SB: 1849 case NETXEN_BRDTYPE_P1_SMAX: 1850 case NETXEN_BRDTYPE_P1_SOCK: 1851 case NETXEN_BRDTYPE_P3_REF_QG: 1852 case NETXEN_BRDTYPE_P3_4_GB: 1853 case NETXEN_BRDTYPE_P3_4_GB_MM: 1854 adapter->ahw.port_type = NETXEN_NIC_GBE; 1855 break; 1856 case NETXEN_BRDTYPE_P3_10G_TP: 1857 adapter->ahw.port_type = (adapter->portnum < 2) ? 1858 NETXEN_NIC_XGBE : NETXEN_NIC_GBE; 1859 break; 1860 default: 1861 dev_err(&pdev->dev, "unknown board type %x\n", board_type); 1862 adapter->ahw.port_type = NETXEN_NIC_XGBE; 1863 break; 1864 } 1865 1866 return 0; 1867} 1868 1869/* NIU access sections */ 1870 1871int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) 1872{ 1873 new_mtu += MTU_FUDGE_FACTOR; 1874 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port), 1875 new_mtu); 1876 return 0; 1877} 1878 1879int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu) 1880{ 1881 new_mtu += MTU_FUDGE_FACTOR; 1882 if (adapter->physical_port == 0) 1883 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu); 1884 else 1885 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu); 1886 return 0; 1887} 1888 1889void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) 1890{ 1891 __u32 status; 1892 __u32 autoneg; 1893 __u32 port_mode; 1894 1895 if (!netif_carrier_ok(adapter->netdev)) { 1896 adapter->link_speed = 0; 1897 adapter->link_duplex = -1; 1898 adapter->link_autoneg = AUTONEG_ENABLE; 1899 return; 1900 } 1901 1902 if (adapter->ahw.port_type == NETXEN_NIC_GBE) { 1903 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR); 1904 if (port_mode == NETXEN_PORT_MODE_802_3_AP) { 1905 adapter->link_speed = SPEED_1000; 1906 adapter->link_duplex = DUPLEX_FULL; 1907 adapter->link_autoneg = AUTONEG_DISABLE; 1908 return; 1909 } 1910 1911 if (adapter->phy_read && 1912 adapter->phy_read(adapter, 1913 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, 1914 &status) == 0) { 1915 if (netxen_get_phy_link(status)) { 1916 switch (netxen_get_phy_speed(status)) { 1917 case 0: 1918 adapter->link_speed = SPEED_10; 1919 break; 1920 case 1: 1921 adapter->link_speed = SPEED_100; 1922 break; 1923 case 2: 1924 adapter->link_speed = SPEED_1000; 1925 break; 1926 default: 1927 adapter->link_speed = 0; 1928 break; 1929 } 1930 switch (netxen_get_phy_duplex(status)) { 1931 case 0: 1932 adapter->link_duplex = DUPLEX_HALF; 1933 break; 1934 case 1: 1935 adapter->link_duplex = DUPLEX_FULL; 1936 break; 1937 default: 1938 adapter->link_duplex = -1; 1939 break; 1940 } 1941 if (adapter->phy_read && 1942 adapter->phy_read(adapter, 1943 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG, 1944 &autoneg) != 0) 1945 adapter->link_autoneg = autoneg; 1946 } else 1947 goto link_down; 1948 } else { 1949 link_down: 1950 adapter->link_speed = 0; 1951 adapter->link_duplex = -1; 1952 } 1953 } 1954} 1955 1956int 1957netxen_nic_wol_supported(struct netxen_adapter *adapter) 1958{ 1959 u32 wol_cfg; 1960 1961 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) 1962 return 0; 1963 1964 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV); 1965 if (wol_cfg & (1UL << adapter->portnum)) { 1966 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG); 1967 if (wol_cfg & (1 << adapter->portnum)) 1968 return 1; 1969 } 1970 1971 return 0; 1972} 1973