1/* 2 * Network device driver for the MACE ethernet controller on 3 * Apple Powermacs. Assumes it's under a DBDMA controller. 4 * 5 * Copyright (C) 1996 Paul Mackerras. 6 */ 7 8#include <linux/module.h> 9#include <linux/kernel.h> 10#include <linux/netdevice.h> 11#include <linux/etherdevice.h> 12#include <linux/delay.h> 13#include <linux/string.h> 14#include <linux/timer.h> 15#include <linux/init.h> 16#include <linux/crc32.h> 17#include <linux/spinlock.h> 18#include <linux/bitrev.h> 19#include <linux/slab.h> 20#include <asm/prom.h> 21#include <asm/dbdma.h> 22#include <asm/io.h> 23#include <asm/pgtable.h> 24#include <asm/macio.h> 25 26#include "mace.h" 27 28static int port_aaui = -1; 29 30#define N_RX_RING 8 31#define N_TX_RING 6 32#define MAX_TX_ACTIVE 1 33#define NCMDS_TX 1 /* dma commands per element in tx ring */ 34#define RX_BUFLEN (ETH_FRAME_LEN + 8) 35#define TX_TIMEOUT HZ /* 1 second */ 36 37#define BROKEN_ADDRCHG_REV 0x0941 38 39/* Bits in transmit DMA status */ 40#define TX_DMA_ERR 0x80 41 42struct mace_data { 43 volatile struct mace __iomem *mace; 44 volatile struct dbdma_regs __iomem *tx_dma; 45 int tx_dma_intr; 46 volatile struct dbdma_regs __iomem *rx_dma; 47 int rx_dma_intr; 48 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */ 49 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */ 50 struct sk_buff *rx_bufs[N_RX_RING]; 51 int rx_fill; 52 int rx_empty; 53 struct sk_buff *tx_bufs[N_TX_RING]; 54 int tx_fill; 55 int tx_empty; 56 unsigned char maccc; 57 unsigned char tx_fullup; 58 unsigned char tx_active; 59 unsigned char tx_bad_runt; 60 struct timer_list tx_timeout; 61 int timeout_active; 62 int port_aaui; 63 int chipid; 64 struct macio_dev *mdev; 65 spinlock_t lock; 66}; 67 68/* 69 * Number of bytes of private data per MACE: allow enough for 70 * the rx and tx dma commands plus a branch dma command each, 71 * and another 16 bytes to allow us to align the dma command 72 * buffers on a 16 byte boundary. 73 */ 74#define PRIV_BYTES (sizeof(struct mace_data) \ 75 + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd)) 76 77static int mace_open(struct net_device *dev); 78static int mace_close(struct net_device *dev); 79static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev); 80static void mace_set_multicast(struct net_device *dev); 81static void mace_reset(struct net_device *dev); 82static int mace_set_address(struct net_device *dev, void *addr); 83static irqreturn_t mace_interrupt(int irq, void *dev_id); 84static irqreturn_t mace_txdma_intr(int irq, void *dev_id); 85static irqreturn_t mace_rxdma_intr(int irq, void *dev_id); 86static void mace_set_timeout(struct net_device *dev); 87static void mace_tx_timeout(unsigned long data); 88static inline void dbdma_reset(volatile struct dbdma_regs __iomem *dma); 89static inline void mace_clean_rings(struct mace_data *mp); 90static void __mace_set_address(struct net_device *dev, void *addr); 91 92/* 93 * If we can't get a skbuff when we need it, we use this area for DMA. 94 */ 95static unsigned char *dummy_buf; 96 97static const struct net_device_ops mace_netdev_ops = { 98 .ndo_open = mace_open, 99 .ndo_stop = mace_close, 100 .ndo_start_xmit = mace_xmit_start, 101 .ndo_set_multicast_list = mace_set_multicast, 102 .ndo_set_mac_address = mace_set_address, 103 .ndo_change_mtu = eth_change_mtu, 104 .ndo_validate_addr = eth_validate_addr, 105}; 106 107static int __devinit mace_probe(struct macio_dev *mdev, const struct of_device_id *match) 108{ 109 struct device_node *mace = macio_get_of_node(mdev); 110 struct net_device *dev; 111 struct mace_data *mp; 112 const unsigned char *addr; 113 int j, rev, rc = -EBUSY; 114 115 if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) { 116 printk(KERN_ERR "can't use MACE %s: need 3 addrs and 3 irqs\n", 117 mace->full_name); 118 return -ENODEV; 119 } 120 121 addr = of_get_property(mace, "mac-address", NULL); 122 if (addr == NULL) { 123 addr = of_get_property(mace, "local-mac-address", NULL); 124 if (addr == NULL) { 125 printk(KERN_ERR "Can't get mac-address for MACE %s\n", 126 mace->full_name); 127 return -ENODEV; 128 } 129 } 130 131 /* 132 * lazy allocate the driver-wide dummy buffer. (Note that we 133 * never have more than one MACE in the system anyway) 134 */ 135 if (dummy_buf == NULL) { 136 dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL); 137 if (dummy_buf == NULL) { 138 printk(KERN_ERR "MACE: couldn't allocate dummy buffer\n"); 139 return -ENOMEM; 140 } 141 } 142 143 if (macio_request_resources(mdev, "mace")) { 144 printk(KERN_ERR "MACE: can't request IO resources !\n"); 145 return -EBUSY; 146 } 147 148 dev = alloc_etherdev(PRIV_BYTES); 149 if (!dev) { 150 printk(KERN_ERR "MACE: can't allocate ethernet device !\n"); 151 rc = -ENOMEM; 152 goto err_release; 153 } 154 SET_NETDEV_DEV(dev, &mdev->ofdev.dev); 155 156 mp = netdev_priv(dev); 157 mp->mdev = mdev; 158 macio_set_drvdata(mdev, dev); 159 160 dev->base_addr = macio_resource_start(mdev, 0); 161 mp->mace = ioremap(dev->base_addr, 0x1000); 162 if (mp->mace == NULL) { 163 printk(KERN_ERR "MACE: can't map IO resources !\n"); 164 rc = -ENOMEM; 165 goto err_free; 166 } 167 dev->irq = macio_irq(mdev, 0); 168 169 rev = addr[0] == 0 && addr[1] == 0xA0; 170 for (j = 0; j < 6; ++j) { 171 dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j]; 172 } 173 mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) | 174 in_8(&mp->mace->chipid_lo); 175 176 177 mp = netdev_priv(dev); 178 mp->maccc = ENXMT | ENRCV; 179 180 mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000); 181 if (mp->tx_dma == NULL) { 182 printk(KERN_ERR "MACE: can't map TX DMA resources !\n"); 183 rc = -ENOMEM; 184 goto err_unmap_io; 185 } 186 mp->tx_dma_intr = macio_irq(mdev, 1); 187 188 mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000); 189 if (mp->rx_dma == NULL) { 190 printk(KERN_ERR "MACE: can't map RX DMA resources !\n"); 191 rc = -ENOMEM; 192 goto err_unmap_tx_dma; 193 } 194 mp->rx_dma_intr = macio_irq(mdev, 2); 195 196 mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1); 197 mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1; 198 199 memset((char *) mp->tx_cmds, 0, 200 (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd)); 201 init_timer(&mp->tx_timeout); 202 spin_lock_init(&mp->lock); 203 mp->timeout_active = 0; 204 205 if (port_aaui >= 0) 206 mp->port_aaui = port_aaui; 207 else { 208 /* Apple Network Server uses the AAUI port */ 209 if (of_machine_is_compatible("AAPL,ShinerESB")) 210 mp->port_aaui = 1; 211 else { 212#ifdef CONFIG_MACE_AAUI_PORT 213 mp->port_aaui = 1; 214#else 215 mp->port_aaui = 0; 216#endif 217 } 218 } 219 220 dev->netdev_ops = &mace_netdev_ops; 221 222 /* 223 * Most of what is below could be moved to mace_open() 224 */ 225 mace_reset(dev); 226 227 rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev); 228 if (rc) { 229 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq); 230 goto err_unmap_rx_dma; 231 } 232 rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev); 233 if (rc) { 234 printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr); 235 goto err_free_irq; 236 } 237 rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev); 238 if (rc) { 239 printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr); 240 goto err_free_tx_irq; 241 } 242 243 rc = register_netdev(dev); 244 if (rc) { 245 printk(KERN_ERR "MACE: Cannot register net device, aborting.\n"); 246 goto err_free_rx_irq; 247 } 248 249 printk(KERN_INFO "%s: MACE at %pM, chip revision %d.%d\n", 250 dev->name, dev->dev_addr, 251 mp->chipid >> 8, mp->chipid & 0xff); 252 253 return 0; 254 255 err_free_rx_irq: 256 free_irq(macio_irq(mdev, 2), dev); 257 err_free_tx_irq: 258 free_irq(macio_irq(mdev, 1), dev); 259 err_free_irq: 260 free_irq(macio_irq(mdev, 0), dev); 261 err_unmap_rx_dma: 262 iounmap(mp->rx_dma); 263 err_unmap_tx_dma: 264 iounmap(mp->tx_dma); 265 err_unmap_io: 266 iounmap(mp->mace); 267 err_free: 268 free_netdev(dev); 269 err_release: 270 macio_release_resources(mdev); 271 272 return rc; 273} 274 275static int __devexit mace_remove(struct macio_dev *mdev) 276{ 277 struct net_device *dev = macio_get_drvdata(mdev); 278 struct mace_data *mp; 279 280 BUG_ON(dev == NULL); 281 282 macio_set_drvdata(mdev, NULL); 283 284 mp = netdev_priv(dev); 285 286 unregister_netdev(dev); 287 288 free_irq(dev->irq, dev); 289 free_irq(mp->tx_dma_intr, dev); 290 free_irq(mp->rx_dma_intr, dev); 291 292 iounmap(mp->rx_dma); 293 iounmap(mp->tx_dma); 294 iounmap(mp->mace); 295 296 free_netdev(dev); 297 298 macio_release_resources(mdev); 299 300 return 0; 301} 302 303static void dbdma_reset(volatile struct dbdma_regs __iomem *dma) 304{ 305 int i; 306 307 out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16); 308 309 /* 310 * Yes this looks peculiar, but apparently it needs to be this 311 * way on some machines. 312 */ 313 for (i = 200; i > 0; --i) 314 if (ld_le32(&dma->control) & RUN) 315 udelay(1); 316} 317 318static void mace_reset(struct net_device *dev) 319{ 320 struct mace_data *mp = netdev_priv(dev); 321 volatile struct mace __iomem *mb = mp->mace; 322 int i; 323 324 /* soft-reset the chip */ 325 i = 200; 326 while (--i) { 327 out_8(&mb->biucc, SWRST); 328 if (in_8(&mb->biucc) & SWRST) { 329 udelay(10); 330 continue; 331 } 332 break; 333 } 334 if (!i) { 335 printk(KERN_ERR "mace: cannot reset chip!\n"); 336 return; 337 } 338 339 out_8(&mb->imr, 0xff); /* disable all intrs for now */ 340 i = in_8(&mb->ir); 341 out_8(&mb->maccc, 0); /* turn off tx, rx */ 342 343 out_8(&mb->biucc, XMTSP_64); 344 out_8(&mb->utr, RTRD); 345 out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST); 346 out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */ 347 out_8(&mb->rcvfc, 0); 348 349 /* load up the hardware address */ 350 __mace_set_address(dev, dev->dev_addr); 351 352 /* clear the multicast filter */ 353 if (mp->chipid == BROKEN_ADDRCHG_REV) 354 out_8(&mb->iac, LOGADDR); 355 else { 356 out_8(&mb->iac, ADDRCHG | LOGADDR); 357 while ((in_8(&mb->iac) & ADDRCHG) != 0) 358 ; 359 } 360 for (i = 0; i < 8; ++i) 361 out_8(&mb->ladrf, 0); 362 363 /* done changing address */ 364 if (mp->chipid != BROKEN_ADDRCHG_REV) 365 out_8(&mb->iac, 0); 366 367 if (mp->port_aaui) 368 out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO); 369 else 370 out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO); 371} 372 373static void __mace_set_address(struct net_device *dev, void *addr) 374{ 375 struct mace_data *mp = netdev_priv(dev); 376 volatile struct mace __iomem *mb = mp->mace; 377 unsigned char *p = addr; 378 int i; 379 380 /* load up the hardware address */ 381 if (mp->chipid == BROKEN_ADDRCHG_REV) 382 out_8(&mb->iac, PHYADDR); 383 else { 384 out_8(&mb->iac, ADDRCHG | PHYADDR); 385 while ((in_8(&mb->iac) & ADDRCHG) != 0) 386 ; 387 } 388 for (i = 0; i < 6; ++i) 389 out_8(&mb->padr, dev->dev_addr[i] = p[i]); 390 if (mp->chipid != BROKEN_ADDRCHG_REV) 391 out_8(&mb->iac, 0); 392} 393 394static int mace_set_address(struct net_device *dev, void *addr) 395{ 396 struct mace_data *mp = netdev_priv(dev); 397 volatile struct mace __iomem *mb = mp->mace; 398 unsigned long flags; 399 400 spin_lock_irqsave(&mp->lock, flags); 401 402 __mace_set_address(dev, addr); 403 404 /* note: setting ADDRCHG clears ENRCV */ 405 out_8(&mb->maccc, mp->maccc); 406 407 spin_unlock_irqrestore(&mp->lock, flags); 408 return 0; 409} 410 411static inline void mace_clean_rings(struct mace_data *mp) 412{ 413 int i; 414 415 /* free some skb's */ 416 for (i = 0; i < N_RX_RING; ++i) { 417 if (mp->rx_bufs[i] != NULL) { 418 dev_kfree_skb(mp->rx_bufs[i]); 419 mp->rx_bufs[i] = NULL; 420 } 421 } 422 for (i = mp->tx_empty; i != mp->tx_fill; ) { 423 dev_kfree_skb(mp->tx_bufs[i]); 424 if (++i >= N_TX_RING) 425 i = 0; 426 } 427} 428 429static int mace_open(struct net_device *dev) 430{ 431 struct mace_data *mp = netdev_priv(dev); 432 volatile struct mace __iomem *mb = mp->mace; 433 volatile struct dbdma_regs __iomem *rd = mp->rx_dma; 434 volatile struct dbdma_regs __iomem *td = mp->tx_dma; 435 volatile struct dbdma_cmd *cp; 436 int i; 437 struct sk_buff *skb; 438 unsigned char *data; 439 440 /* reset the chip */ 441 mace_reset(dev); 442 443 /* initialize list of sk_buffs for receiving and set up recv dma */ 444 mace_clean_rings(mp); 445 memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd)); 446 cp = mp->rx_cmds; 447 for (i = 0; i < N_RX_RING - 1; ++i) { 448 skb = dev_alloc_skb(RX_BUFLEN + 2); 449 if (!skb) { 450 data = dummy_buf; 451 } else { 452 skb_reserve(skb, 2); /* so IP header lands on 4-byte bdry */ 453 data = skb->data; 454 } 455 mp->rx_bufs[i] = skb; 456 st_le16(&cp->req_count, RX_BUFLEN); 457 st_le16(&cp->command, INPUT_LAST + INTR_ALWAYS); 458 st_le32(&cp->phy_addr, virt_to_bus(data)); 459 cp->xfer_status = 0; 460 ++cp; 461 } 462 mp->rx_bufs[i] = NULL; 463 st_le16(&cp->command, DBDMA_STOP); 464 mp->rx_fill = i; 465 mp->rx_empty = 0; 466 467 /* Put a branch back to the beginning of the receive command list */ 468 ++cp; 469 st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS); 470 st_le32(&cp->cmd_dep, virt_to_bus(mp->rx_cmds)); 471 472 /* start rx dma */ 473 out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ 474 out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds)); 475 out_le32(&rd->control, (RUN << 16) | RUN); 476 477 /* put a branch at the end of the tx command list */ 478 cp = mp->tx_cmds + NCMDS_TX * N_TX_RING; 479 st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS); 480 st_le32(&cp->cmd_dep, virt_to_bus(mp->tx_cmds)); 481 482 /* reset tx dma */ 483 out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); 484 out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds)); 485 mp->tx_fill = 0; 486 mp->tx_empty = 0; 487 mp->tx_fullup = 0; 488 mp->tx_active = 0; 489 mp->tx_bad_runt = 0; 490 491 /* turn it on! */ 492 out_8(&mb->maccc, mp->maccc); 493 /* enable all interrupts except receive interrupts */ 494 out_8(&mb->imr, RCVINT); 495 496 return 0; 497} 498 499static int mace_close(struct net_device *dev) 500{ 501 struct mace_data *mp = netdev_priv(dev); 502 volatile struct mace __iomem *mb = mp->mace; 503 volatile struct dbdma_regs __iomem *rd = mp->rx_dma; 504 volatile struct dbdma_regs __iomem *td = mp->tx_dma; 505 506 /* disable rx and tx */ 507 out_8(&mb->maccc, 0); 508 out_8(&mb->imr, 0xff); /* disable all intrs */ 509 510 /* disable rx and tx dma */ 511 st_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ 512 st_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ 513 514 mace_clean_rings(mp); 515 516 return 0; 517} 518 519static inline void mace_set_timeout(struct net_device *dev) 520{ 521 struct mace_data *mp = netdev_priv(dev); 522 523 if (mp->timeout_active) 524 del_timer(&mp->tx_timeout); 525 mp->tx_timeout.expires = jiffies + TX_TIMEOUT; 526 mp->tx_timeout.function = mace_tx_timeout; 527 mp->tx_timeout.data = (unsigned long) dev; 528 add_timer(&mp->tx_timeout); 529 mp->timeout_active = 1; 530} 531 532static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev) 533{ 534 struct mace_data *mp = netdev_priv(dev); 535 volatile struct dbdma_regs __iomem *td = mp->tx_dma; 536 volatile struct dbdma_cmd *cp, *np; 537 unsigned long flags; 538 int fill, next, len; 539 540 /* see if there's a free slot in the tx ring */ 541 spin_lock_irqsave(&mp->lock, flags); 542 fill = mp->tx_fill; 543 next = fill + 1; 544 if (next >= N_TX_RING) 545 next = 0; 546 if (next == mp->tx_empty) { 547 netif_stop_queue(dev); 548 mp->tx_fullup = 1; 549 spin_unlock_irqrestore(&mp->lock, flags); 550 return NETDEV_TX_BUSY; /* can't take it at the moment */ 551 } 552 spin_unlock_irqrestore(&mp->lock, flags); 553 554 /* partially fill in the dma command block */ 555 len = skb->len; 556 if (len > ETH_FRAME_LEN) { 557 printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len); 558 len = ETH_FRAME_LEN; 559 } 560 mp->tx_bufs[fill] = skb; 561 cp = mp->tx_cmds + NCMDS_TX * fill; 562 st_le16(&cp->req_count, len); 563 st_le32(&cp->phy_addr, virt_to_bus(skb->data)); 564 565 np = mp->tx_cmds + NCMDS_TX * next; 566 out_le16(&np->command, DBDMA_STOP); 567 568 /* poke the tx dma channel */ 569 spin_lock_irqsave(&mp->lock, flags); 570 mp->tx_fill = next; 571 if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) { 572 out_le16(&cp->xfer_status, 0); 573 out_le16(&cp->command, OUTPUT_LAST); 574 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE)); 575 ++mp->tx_active; 576 mace_set_timeout(dev); 577 } 578 if (++next >= N_TX_RING) 579 next = 0; 580 if (next == mp->tx_empty) 581 netif_stop_queue(dev); 582 spin_unlock_irqrestore(&mp->lock, flags); 583 584 return NETDEV_TX_OK; 585} 586 587static void mace_set_multicast(struct net_device *dev) 588{ 589 struct mace_data *mp = netdev_priv(dev); 590 volatile struct mace __iomem *mb = mp->mace; 591 int i; 592 u32 crc; 593 unsigned long flags; 594 595 spin_lock_irqsave(&mp->lock, flags); 596 mp->maccc &= ~PROM; 597 if (dev->flags & IFF_PROMISC) { 598 mp->maccc |= PROM; 599 } else { 600 unsigned char multicast_filter[8]; 601 struct netdev_hw_addr *ha; 602 603 if (dev->flags & IFF_ALLMULTI) { 604 for (i = 0; i < 8; i++) 605 multicast_filter[i] = 0xff; 606 } else { 607 for (i = 0; i < 8; i++) 608 multicast_filter[i] = 0; 609 netdev_for_each_mc_addr(ha, dev) { 610 crc = ether_crc_le(6, ha->addr); 611 i = crc >> 26; /* bit number in multicast_filter */ 612 multicast_filter[i >> 3] |= 1 << (i & 7); 613 } 614 } 615 616 if (mp->chipid == BROKEN_ADDRCHG_REV) 617 out_8(&mb->iac, LOGADDR); 618 else { 619 out_8(&mb->iac, ADDRCHG | LOGADDR); 620 while ((in_8(&mb->iac) & ADDRCHG) != 0) 621 ; 622 } 623 for (i = 0; i < 8; ++i) 624 out_8(&mb->ladrf, multicast_filter[i]); 625 if (mp->chipid != BROKEN_ADDRCHG_REV) 626 out_8(&mb->iac, 0); 627 } 628 /* reset maccc */ 629 out_8(&mb->maccc, mp->maccc); 630 spin_unlock_irqrestore(&mp->lock, flags); 631} 632 633static void mace_handle_misc_intrs(struct mace_data *mp, int intr, struct net_device *dev) 634{ 635 volatile struct mace __iomem *mb = mp->mace; 636 static int mace_babbles, mace_jabbers; 637 638 if (intr & MPCO) 639 dev->stats.rx_missed_errors += 256; 640 dev->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */ 641 if (intr & RNTPCO) 642 dev->stats.rx_length_errors += 256; 643 dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */ 644 if (intr & CERR) 645 ++dev->stats.tx_heartbeat_errors; 646 if (intr & BABBLE) 647 if (mace_babbles++ < 4) 648 printk(KERN_DEBUG "mace: babbling transmitter\n"); 649 if (intr & JABBER) 650 if (mace_jabbers++ < 4) 651 printk(KERN_DEBUG "mace: jabbering transceiver\n"); 652} 653 654static irqreturn_t mace_interrupt(int irq, void *dev_id) 655{ 656 struct net_device *dev = (struct net_device *) dev_id; 657 struct mace_data *mp = netdev_priv(dev); 658 volatile struct mace __iomem *mb = mp->mace; 659 volatile struct dbdma_regs __iomem *td = mp->tx_dma; 660 volatile struct dbdma_cmd *cp; 661 int intr, fs, i, stat, x; 662 int xcount, dstat; 663 unsigned long flags; 664 /* static int mace_last_fs, mace_last_xcount; */ 665 666 spin_lock_irqsave(&mp->lock, flags); 667 intr = in_8(&mb->ir); /* read interrupt register */ 668 in_8(&mb->xmtrc); /* get retries */ 669 mace_handle_misc_intrs(mp, intr, dev); 670 671 i = mp->tx_empty; 672 while (in_8(&mb->pr) & XMTSV) { 673 del_timer(&mp->tx_timeout); 674 mp->timeout_active = 0; 675 /* 676 * Clear any interrupt indication associated with this status 677 * word. This appears to unlatch any error indication from 678 * the DMA controller. 679 */ 680 intr = in_8(&mb->ir); 681 if (intr != 0) 682 mace_handle_misc_intrs(mp, intr, dev); 683 if (mp->tx_bad_runt) { 684 fs = in_8(&mb->xmtfs); 685 mp->tx_bad_runt = 0; 686 out_8(&mb->xmtfc, AUTO_PAD_XMIT); 687 continue; 688 } 689 dstat = ld_le32(&td->status); 690 /* stop DMA controller */ 691 out_le32(&td->control, RUN << 16); 692 /* 693 * xcount is the number of complete frames which have been 694 * written to the fifo but for which status has not been read. 695 */ 696 xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK; 697 if (xcount == 0 || (dstat & DEAD)) { 698 /* 699 * If a packet was aborted before the DMA controller has 700 * finished transferring it, it seems that there are 2 bytes 701 * which are stuck in some buffer somewhere. These will get 702 * transmitted as soon as we read the frame status (which 703 * reenables the transmit data transfer request). Turning 704 * off the DMA controller and/or resetting the MACE doesn't 705 * help. So we disable auto-padding and FCS transmission 706 * so the two bytes will only be a runt packet which should 707 * be ignored by other stations. 708 */ 709 out_8(&mb->xmtfc, DXMTFCS); 710 } 711 fs = in_8(&mb->xmtfs); 712 if ((fs & XMTSV) == 0) { 713 printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n", 714 fs, xcount, dstat); 715 mace_reset(dev); 716 } 717 cp = mp->tx_cmds + NCMDS_TX * i; 718 stat = ld_le16(&cp->xfer_status); 719 if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) { 720 /* 721 * Check whether there were in fact 2 bytes written to 722 * the transmit FIFO. 723 */ 724 udelay(1); 725 x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK; 726 if (x != 0) { 727 /* there were two bytes with an end-of-packet indication */ 728 mp->tx_bad_runt = 1; 729 mace_set_timeout(dev); 730 } else { 731 /* 732 * Either there weren't the two bytes buffered up, or they 733 * didn't have an end-of-packet indication. 734 * We flush the transmit FIFO just in case (by setting the 735 * XMTFWU bit with the transmitter disabled). 736 */ 737 out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT); 738 out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU); 739 udelay(1); 740 out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT); 741 out_8(&mb->xmtfc, AUTO_PAD_XMIT); 742 } 743 } 744 /* dma should have finished */ 745 if (i == mp->tx_fill) { 746 printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n", 747 fs, xcount, dstat); 748 continue; 749 } 750 /* Update stats */ 751 if (fs & (UFLO|LCOL|LCAR|RTRY)) { 752 ++dev->stats.tx_errors; 753 if (fs & LCAR) 754 ++dev->stats.tx_carrier_errors; 755 if (fs & (UFLO|LCOL|RTRY)) 756 ++dev->stats.tx_aborted_errors; 757 } else { 758 dev->stats.tx_bytes += mp->tx_bufs[i]->len; 759 ++dev->stats.tx_packets; 760 } 761 dev_kfree_skb_irq(mp->tx_bufs[i]); 762 --mp->tx_active; 763 if (++i >= N_TX_RING) 764 i = 0; 765 } 766 767 if (i != mp->tx_empty) { 768 mp->tx_fullup = 0; 769 netif_wake_queue(dev); 770 } 771 mp->tx_empty = i; 772 i += mp->tx_active; 773 if (i >= N_TX_RING) 774 i -= N_TX_RING; 775 if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) { 776 do { 777 /* set up the next one */ 778 cp = mp->tx_cmds + NCMDS_TX * i; 779 out_le16(&cp->xfer_status, 0); 780 out_le16(&cp->command, OUTPUT_LAST); 781 ++mp->tx_active; 782 if (++i >= N_TX_RING) 783 i = 0; 784 } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE); 785 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE)); 786 mace_set_timeout(dev); 787 } 788 spin_unlock_irqrestore(&mp->lock, flags); 789 return IRQ_HANDLED; 790} 791 792static void mace_tx_timeout(unsigned long data) 793{ 794 struct net_device *dev = (struct net_device *) data; 795 struct mace_data *mp = netdev_priv(dev); 796 volatile struct mace __iomem *mb = mp->mace; 797 volatile struct dbdma_regs __iomem *td = mp->tx_dma; 798 volatile struct dbdma_regs __iomem *rd = mp->rx_dma; 799 volatile struct dbdma_cmd *cp; 800 unsigned long flags; 801 int i; 802 803 spin_lock_irqsave(&mp->lock, flags); 804 mp->timeout_active = 0; 805 if (mp->tx_active == 0 && !mp->tx_bad_runt) 806 goto out; 807 808 /* update various counters */ 809 mace_handle_misc_intrs(mp, in_8(&mb->ir), dev); 810 811 cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty; 812 813 /* turn off both tx and rx and reset the chip */ 814 out_8(&mb->maccc, 0); 815 printk(KERN_ERR "mace: transmit timeout - resetting\n"); 816 dbdma_reset(td); 817 mace_reset(dev); 818 819 /* restart rx dma */ 820 cp = bus_to_virt(ld_le32(&rd->cmdptr)); 821 dbdma_reset(rd); 822 out_le16(&cp->xfer_status, 0); 823 out_le32(&rd->cmdptr, virt_to_bus(cp)); 824 out_le32(&rd->control, (RUN << 16) | RUN); 825 826 /* fix up the transmit side */ 827 i = mp->tx_empty; 828 mp->tx_active = 0; 829 ++dev->stats.tx_errors; 830 if (mp->tx_bad_runt) { 831 mp->tx_bad_runt = 0; 832 } else if (i != mp->tx_fill) { 833 dev_kfree_skb(mp->tx_bufs[i]); 834 if (++i >= N_TX_RING) 835 i = 0; 836 mp->tx_empty = i; 837 } 838 mp->tx_fullup = 0; 839 netif_wake_queue(dev); 840 if (i != mp->tx_fill) { 841 cp = mp->tx_cmds + NCMDS_TX * i; 842 out_le16(&cp->xfer_status, 0); 843 out_le16(&cp->command, OUTPUT_LAST); 844 out_le32(&td->cmdptr, virt_to_bus(cp)); 845 out_le32(&td->control, (RUN << 16) | RUN); 846 ++mp->tx_active; 847 mace_set_timeout(dev); 848 } 849 850 /* turn it back on */ 851 out_8(&mb->imr, RCVINT); 852 out_8(&mb->maccc, mp->maccc); 853 854out: 855 spin_unlock_irqrestore(&mp->lock, flags); 856} 857 858static irqreturn_t mace_txdma_intr(int irq, void *dev_id) 859{ 860 return IRQ_HANDLED; 861} 862 863static irqreturn_t mace_rxdma_intr(int irq, void *dev_id) 864{ 865 struct net_device *dev = (struct net_device *) dev_id; 866 struct mace_data *mp = netdev_priv(dev); 867 volatile struct dbdma_regs __iomem *rd = mp->rx_dma; 868 volatile struct dbdma_cmd *cp, *np; 869 int i, nb, stat, next; 870 struct sk_buff *skb; 871 unsigned frame_status; 872 static int mace_lost_status; 873 unsigned char *data; 874 unsigned long flags; 875 876 spin_lock_irqsave(&mp->lock, flags); 877 for (i = mp->rx_empty; i != mp->rx_fill; ) { 878 cp = mp->rx_cmds + i; 879 stat = ld_le16(&cp->xfer_status); 880 if ((stat & ACTIVE) == 0) { 881 next = i + 1; 882 if (next >= N_RX_RING) 883 next = 0; 884 np = mp->rx_cmds + next; 885 if (next != mp->rx_fill && 886 (ld_le16(&np->xfer_status) & ACTIVE) != 0) { 887 printk(KERN_DEBUG "mace: lost a status word\n"); 888 ++mace_lost_status; 889 } else 890 break; 891 } 892 nb = ld_le16(&cp->req_count) - ld_le16(&cp->res_count); 893 out_le16(&cp->command, DBDMA_STOP); 894 /* got a packet, have a look at it */ 895 skb = mp->rx_bufs[i]; 896 if (!skb) { 897 ++dev->stats.rx_dropped; 898 } else if (nb > 8) { 899 data = skb->data; 900 frame_status = (data[nb-3] << 8) + data[nb-4]; 901 if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) { 902 ++dev->stats.rx_errors; 903 if (frame_status & RS_OFLO) 904 ++dev->stats.rx_over_errors; 905 if (frame_status & RS_FRAMERR) 906 ++dev->stats.rx_frame_errors; 907 if (frame_status & RS_FCSERR) 908 ++dev->stats.rx_crc_errors; 909 } else { 910 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the 911 * FCS on frames with 802.3 headers. This means that Ethernet 912 * frames have 8 extra octets at the end, while 802.3 frames 913 * have only 4. We need to correctly account for this. */ 914 if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */ 915 nb -= 4; 916 else /* Ethernet header; mace includes FCS */ 917 nb -= 8; 918 skb_put(skb, nb); 919 skb->protocol = eth_type_trans(skb, dev); 920 dev->stats.rx_bytes += skb->len; 921 netif_rx(skb); 922 mp->rx_bufs[i] = NULL; 923 ++dev->stats.rx_packets; 924 } 925 } else { 926 ++dev->stats.rx_errors; 927 ++dev->stats.rx_length_errors; 928 } 929 930 /* advance to next */ 931 if (++i >= N_RX_RING) 932 i = 0; 933 } 934 mp->rx_empty = i; 935 936 i = mp->rx_fill; 937 for (;;) { 938 next = i + 1; 939 if (next >= N_RX_RING) 940 next = 0; 941 if (next == mp->rx_empty) 942 break; 943 cp = mp->rx_cmds + i; 944 skb = mp->rx_bufs[i]; 945 if (!skb) { 946 skb = dev_alloc_skb(RX_BUFLEN + 2); 947 if (skb) { 948 skb_reserve(skb, 2); 949 mp->rx_bufs[i] = skb; 950 } 951 } 952 st_le16(&cp->req_count, RX_BUFLEN); 953 data = skb? skb->data: dummy_buf; 954 st_le32(&cp->phy_addr, virt_to_bus(data)); 955 out_le16(&cp->xfer_status, 0); 956 out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS); 957 i = next; 958 } 959 if (i != mp->rx_fill) { 960 out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE)); 961 mp->rx_fill = i; 962 } 963 spin_unlock_irqrestore(&mp->lock, flags); 964 return IRQ_HANDLED; 965} 966 967static struct of_device_id mace_match[] = 968{ 969 { 970 .name = "mace", 971 }, 972 {}, 973}; 974MODULE_DEVICE_TABLE (of, mace_match); 975 976static struct macio_driver mace_driver = 977{ 978 .driver = { 979 .name = "mace", 980 .owner = THIS_MODULE, 981 .of_match_table = mace_match, 982 }, 983 .probe = mace_probe, 984 .remove = mace_remove, 985}; 986 987 988static int __init mace_init(void) 989{ 990 return macio_register_driver(&mace_driver); 991} 992 993static void __exit mace_cleanup(void) 994{ 995 macio_unregister_driver(&mace_driver); 996 997 kfree(dummy_buf); 998 dummy_buf = NULL; 999} 1000 1001MODULE_AUTHOR("Paul Mackerras"); 1002MODULE_DESCRIPTION("PowerMac MACE driver."); 1003module_param(port_aaui, int, 0); 1004MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)"); 1005MODULE_LICENSE("GPL"); 1006 1007module_init(mace_init); 1008module_exit(mace_cleanup); 1009