1/******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2010 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28#ifndef _IXGBE_H_ 29#define _IXGBE_H_ 30 31#include <linux/types.h> 32#include <linux/pci.h> 33#include <linux/netdevice.h> 34#include <linux/aer.h> 35 36#include "ixgbe_type.h" 37#include "ixgbe_common.h" 38#include "ixgbe_dcb.h" 39#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) 40#define IXGBE_FCOE 41#include "ixgbe_fcoe.h" 42#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ 43#ifdef CONFIG_IXGBE_DCA 44#include <linux/dca.h> 45#endif 46 47/* common prefix used by pr_<> macros */ 48#undef pr_fmt 49#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 50 51/* TX/RX descriptor defines */ 52#define IXGBE_DEFAULT_TXD 512 53#define IXGBE_MAX_TXD 4096 54#define IXGBE_MIN_TXD 64 55 56#define IXGBE_DEFAULT_RXD 512 57#define IXGBE_MAX_RXD 4096 58#define IXGBE_MIN_RXD 64 59 60/* flow control */ 61#define IXGBE_DEFAULT_FCRTL 0x10000 62#define IXGBE_MIN_FCRTL 0x40 63#define IXGBE_MAX_FCRTL 0x7FF80 64#define IXGBE_DEFAULT_FCRTH 0x20000 65#define IXGBE_MIN_FCRTH 0x600 66#define IXGBE_MAX_FCRTH 0x7FFF0 67#define IXGBE_DEFAULT_FCPAUSE 0xFFFF 68#define IXGBE_MIN_FCPAUSE 0 69#define IXGBE_MAX_FCPAUSE 0xFFFF 70 71/* Supported Rx Buffer Sizes */ 72#define IXGBE_RXBUFFER_64 64 /* Used for packet split */ 73#define IXGBE_RXBUFFER_128 128 /* Used for packet split */ 74#define IXGBE_RXBUFFER_256 256 /* Used for packet split */ 75#define IXGBE_RXBUFFER_2048 2048 76#define IXGBE_RXBUFFER_4096 4096 77#define IXGBE_RXBUFFER_8192 8192 78#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ 79 80#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 81 82#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) 83 84/* How many Rx Buffers do we bundle into one write to the hardware ? */ 85#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 86 87#define IXGBE_TX_FLAGS_CSUM (u32)(1) 88#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1) 89#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2) 90#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3) 91#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4) 92#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5) 93#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 94#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000 95#define IXGBE_TX_FLAGS_VLAN_SHIFT 16 96 97#define IXGBE_MAX_RSC_INT_RATE 162760 98 99#define IXGBE_MAX_VF_MC_ENTRIES 30 100#define IXGBE_MAX_VF_FUNCTIONS 64 101#define IXGBE_MAX_VFTA_ENTRIES 128 102#define MAX_EMULATION_MAC_ADDRS 16 103#define VMDQ_P(p) ((p) + adapter->num_vfs) 104 105struct vf_data_storage { 106 unsigned char vf_mac_addresses[ETH_ALEN]; 107 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; 108 u16 num_vf_mc_hashes; 109 u16 default_vf_vlan_id; 110 u16 vlans_enabled; 111 bool clear_to_send; 112 bool pf_set_mac; 113 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 114 u16 pf_qos; 115}; 116 117/* wrapper around a pointer to a socket buffer, 118 * so a DMA handle can be stored along with the buffer */ 119struct ixgbe_tx_buffer { 120 struct sk_buff *skb; 121 dma_addr_t dma; 122 unsigned long time_stamp; 123 u16 length; 124 u16 next_to_watch; 125 u16 mapped_as_page; 126}; 127 128struct ixgbe_rx_buffer { 129 struct sk_buff *skb; 130 dma_addr_t dma; 131 struct page *page; 132 dma_addr_t page_dma; 133 unsigned int page_offset; 134}; 135 136struct ixgbe_queue_stats { 137 u64 packets; 138 u64 bytes; 139}; 140 141struct ixgbe_ring { 142 void *desc; /* descriptor ring memory */ 143 union { 144 struct ixgbe_tx_buffer *tx_buffer_info; 145 struct ixgbe_rx_buffer *rx_buffer_info; 146 }; 147 u8 atr_sample_rate; 148 u8 atr_count; 149 u16 count; /* amount of descriptors */ 150 u16 rx_buf_len; 151 u16 next_to_use; 152 u16 next_to_clean; 153 154 u8 queue_index; /* needed for multiqueue queue management */ 155 156#define IXGBE_RING_RX_PS_ENABLED (u8)(1) 157 u8 flags; /* per ring feature flags */ 158 u16 head; 159 u16 tail; 160 161 unsigned int total_bytes; 162 unsigned int total_packets; 163 164#ifdef CONFIG_IXGBE_DCA 165 /* cpu for tx queue */ 166 int cpu; 167#endif 168 169 u16 work_limit; /* max work per interrupt */ 170 u16 reg_idx; /* holds the special value that gets 171 * the hardware register offset 172 * associated with this ring, which is 173 * different for DCB and RSS modes 174 */ 175 176 struct ixgbe_queue_stats stats; 177 unsigned long reinit_state; 178 int numa_node; 179 u64 rsc_count; /* stat for coalesced packets */ 180 u64 rsc_flush; /* stats for flushed packets */ 181 u32 restart_queue; /* track tx queue restarts */ 182 u32 non_eop_descs; /* track hardware descriptor chaining */ 183 184 unsigned int size; /* length in bytes */ 185 dma_addr_t dma; /* phys. address of descriptor ring */ 186} ____cacheline_internodealigned_in_smp; 187 188enum ixgbe_ring_f_enum { 189 RING_F_NONE = 0, 190 RING_F_DCB, 191 RING_F_VMDQ, /* SR-IOV uses the same ring feature */ 192 RING_F_RSS, 193 RING_F_FDIR, 194#ifdef IXGBE_FCOE 195 RING_F_FCOE, 196#endif /* IXGBE_FCOE */ 197 198 RING_F_ARRAY_SIZE /* must be last in enum set */ 199}; 200 201#define IXGBE_MAX_DCB_INDICES 8 202#define IXGBE_MAX_RSS_INDICES 16 203#define IXGBE_MAX_VMDQ_INDICES 64 204#define IXGBE_MAX_FDIR_INDICES 64 205#ifdef IXGBE_FCOE 206#define IXGBE_MAX_FCOE_INDICES 8 207#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES) 208#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES) 209#else 210#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES 211#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES 212#endif /* IXGBE_FCOE */ 213struct ixgbe_ring_feature { 214 int indices; 215 int mask; 216} ____cacheline_internodealigned_in_smp; 217 218 219#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ 220 ? 8 : 1) 221#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS 222 223/* MAX_MSIX_Q_VECTORS of these are allocated, 224 * but we only use one per queue-specific vector. 225 */ 226struct ixgbe_q_vector { 227 struct ixgbe_adapter *adapter; 228 unsigned int v_idx; /* index of q_vector within array, also used for 229 * finding the bit in EICR and friends that 230 * represents the vector for this ring */ 231 struct napi_struct napi; 232 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */ 233 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */ 234 u8 rxr_count; /* Rx ring count assigned to this vector */ 235 u8 txr_count; /* Tx ring count assigned to this vector */ 236 u8 tx_itr; 237 u8 rx_itr; 238 u32 eitr; 239}; 240 241/* Helper macros to switch between ints/sec and what the register uses. 242 * And yes, it's the same math going both ways. The lowest value 243 * supported by all of the ixgbe hardware is 8. 244 */ 245#define EITR_INTS_PER_SEC_TO_REG(_eitr) \ 246 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8) 247#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG 248 249#define IXGBE_DESC_UNUSED(R) \ 250 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 251 (R)->next_to_clean - (R)->next_to_use - 1) 252 253#define IXGBE_RX_DESC_ADV(R, i) \ 254 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i])) 255#define IXGBE_TX_DESC_ADV(R, i) \ 256 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i])) 257#define IXGBE_TX_CTXTDESC_ADV(R, i) \ 258 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i])) 259 260#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128 261#ifdef IXGBE_FCOE 262/* Use 3K as the baby jumbo frame size for FCoE */ 263#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 264#endif /* IXGBE_FCOE */ 265 266#define OTHER_VECTOR 1 267#define NON_Q_VECTORS (OTHER_VECTOR) 268 269#define MAX_MSIX_VECTORS_82599 64 270#define MAX_MSIX_Q_VECTORS_82599 64 271#define MAX_MSIX_VECTORS_82598 18 272#define MAX_MSIX_Q_VECTORS_82598 16 273 274#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599 275#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 276 277#define MIN_MSIX_Q_VECTORS 2 278#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 279 280/* board specific private data structure */ 281struct ixgbe_adapter { 282 struct timer_list watchdog_timer; 283 struct vlan_group *vlgrp; 284 u16 bd_number; 285 struct work_struct reset_task; 286 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS]; 287 char name[MAX_MSIX_COUNT][IFNAMSIZ + 9]; 288 struct ixgbe_dcb_config dcb_cfg; 289 struct ixgbe_dcb_config temp_dcb_cfg; 290 u8 dcb_set_bitmap; 291 enum ixgbe_fc_mode last_lfc_mode; 292 293 /* Interrupt Throttle Rate */ 294 u32 rx_itr_setting; 295 u32 tx_itr_setting; 296 u16 eitr_low; 297 u16 eitr_high; 298 299 /* TX */ 300 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; 301 int num_tx_queues; 302 u32 tx_timeout_count; 303 bool detect_tx_hung; 304 305 u64 restart_queue; 306 u64 lsc_int; 307 308 /* RX */ 309 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp; 310 int num_rx_queues; 311 int num_rx_pools; /* == num_rx_queues in 82598 */ 312 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ 313 u64 hw_csum_rx_error; 314 u64 hw_rx_no_dma_resources; 315 u64 non_eop_descs; 316 int num_msix_vectors; 317 int max_msix_q_vectors; /* true count of q_vectors for device */ 318 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; 319 struct msix_entry *msix_entries; 320 321 u32 alloc_rx_page_failed; 322 u32 alloc_rx_buff_failed; 323 324 /* Some features need tri-state capability, 325 * thus the additional *_CAPABLE flags. 326 */ 327 u32 flags; 328#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1) 329#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1) 330#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2) 331#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3) 332#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4) 333#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6) 334#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7) 335#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8) 336#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9) 337#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10) 338#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11) 339#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12) 340#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13) 341#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14) 342#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16) 343#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17) 344#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18) 345#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19) 346#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20) 347#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22) 348#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23) 349#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24) 350#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25) 351#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26) 352#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27) 353#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28) 354#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29) 355#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30) 356 357 u32 flags2; 358#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1) 359#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) 360#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) 361/* default to trying for four seconds */ 362#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) 363 364 /* OS defined structs */ 365 struct net_device *netdev; 366 struct pci_dev *pdev; 367 368 u32 test_icr; 369 struct ixgbe_ring test_tx_ring; 370 struct ixgbe_ring test_rx_ring; 371 372 /* structs defined in ixgbe_hw.h */ 373 struct ixgbe_hw hw; 374 u16 msg_enable; 375 struct ixgbe_hw_stats stats; 376 377 /* Interrupt Throttle Rate */ 378 u32 rx_eitr_param; 379 u32 tx_eitr_param; 380 381 unsigned long state; 382 u64 tx_busy; 383 unsigned int tx_ring_count; 384 unsigned int rx_ring_count; 385 386 u32 link_speed; 387 bool link_up; 388 unsigned long link_check_timeout; 389 390 struct work_struct watchdog_task; 391 struct work_struct sfp_task; 392 struct timer_list sfp_timer; 393 struct work_struct multispeed_fiber_task; 394 struct work_struct sfp_config_module_task; 395 u32 fdir_pballoc; 396 u32 atr_sample_rate; 397 spinlock_t fdir_perfect_lock; 398 struct work_struct fdir_reinit_task; 399#ifdef IXGBE_FCOE 400 struct ixgbe_fcoe fcoe; 401#endif /* IXGBE_FCOE */ 402 u64 rsc_total_count; 403 u64 rsc_total_flush; 404 u32 wol; 405 u16 eeprom_version; 406 407 int node; 408 struct work_struct check_overtemp_task; 409 u32 interrupt_event; 410 411 /* SR-IOV */ 412 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); 413 unsigned int num_vfs; 414 struct vf_data_storage *vfinfo; 415}; 416 417enum ixbge_state_t { 418 __IXGBE_TESTING, 419 __IXGBE_RESETTING, 420 __IXGBE_DOWN, 421 __IXGBE_FDIR_INIT_DONE, 422 __IXGBE_SFP_MODULE_NOT_FOUND 423}; 424 425enum ixgbe_boards { 426 board_82598, 427 board_82599, 428}; 429 430extern struct ixgbe_info ixgbe_82598_info; 431extern struct ixgbe_info ixgbe_82599_info; 432#ifdef CONFIG_IXGBE_DCB 433extern const struct dcbnl_rtnl_ops dcbnl_ops; 434extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg, 435 struct ixgbe_dcb_config *dst_dcb_cfg, 436 int tc_max); 437#endif 438 439extern char ixgbe_driver_name[]; 440extern const char ixgbe_driver_version[]; 441 442extern int ixgbe_up(struct ixgbe_adapter *adapter); 443extern void ixgbe_down(struct ixgbe_adapter *adapter); 444extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); 445extern void ixgbe_reset(struct ixgbe_adapter *adapter); 446extern void ixgbe_set_ethtool_ops(struct net_device *netdev); 447extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 448extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 449extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 450extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); 451extern void ixgbe_update_stats(struct ixgbe_adapter *adapter); 452extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); 453extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); 454extern void ixgbe_write_eitr(struct ixgbe_q_vector *); 455extern int ethtool_ioctl(struct ifreq *ifr); 456extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); 457extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc); 458extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc); 459extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, 460 struct ixgbe_atr_input *input, 461 u8 queue); 462extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, 463 struct ixgbe_atr_input *input, 464 struct ixgbe_atr_input_masks *input_masks, 465 u16 soft_id, u8 queue); 466extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, 467 u16 vlan_id); 468extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, 469 u32 src_addr); 470extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, 471 u32 dst_addr); 472extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, 473 u16 src_port); 474extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, 475 u16 dst_port); 476extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, 477 u16 flex_byte); 478extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, 479 u8 l4type); 480extern void ixgbe_set_rx_mode(struct net_device *netdev); 481#ifdef IXGBE_FCOE 482extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); 483extern int ixgbe_fso(struct ixgbe_adapter *adapter, 484 struct ixgbe_ring *tx_ring, struct sk_buff *skb, 485 u32 tx_flags, u8 *hdr_len); 486extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter); 487extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, 488 union ixgbe_adv_rx_desc *rx_desc, 489 struct sk_buff *skb); 490extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, 491 struct scatterlist *sgl, unsigned int sgc); 492extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); 493extern int ixgbe_fcoe_enable(struct net_device *netdev); 494extern int ixgbe_fcoe_disable(struct net_device *netdev); 495#ifdef CONFIG_IXGBE_DCB 496extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); 497extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); 498#endif /* CONFIG_IXGBE_DCB */ 499extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); 500#endif /* IXGBE_FCOE */ 501 502#endif /* _IXGBE_H_ */ 503