1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2009 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28#ifndef _E1000_DEFINES_H_ 29#define _E1000_DEFINES_H_ 30 31/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 32#define REQ_TX_DESCRIPTOR_MULTIPLE 8 33#define REQ_RX_DESCRIPTOR_MULTIPLE 8 34 35/* Definitions for power management and wakeup registers */ 36/* Wake Up Control */ 37#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 38 39/* Wake Up Filter Control */ 40#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 41#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 42#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 43#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 44#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 45 46/* Extended Device Control */ 47#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */ 48/* Physical Func Reset Done Indication */ 49#define E1000_CTRL_EXT_PFRSTD 0x00004000 50#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 51#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 52#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 53#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 54#define E1000_CTRL_EXT_EIAME 0x01000000 55#define E1000_CTRL_EXT_IRCA 0x00000001 56/* Interrupt delay cancellation */ 57/* Driver loaded bit for FW */ 58#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 59/* Interrupt acknowledge Auto-mask */ 60/* Clear Interrupt timers after IMS clear */ 61/* packet buffer parity error detection enabled */ 62/* descriptor FIFO parity error detection enable */ 63#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 64#define E1000_I2CCMD_REG_ADDR_SHIFT 16 65#define E1000_I2CCMD_PHY_ADDR_SHIFT 24 66#define E1000_I2CCMD_OPCODE_READ 0x08000000 67#define E1000_I2CCMD_OPCODE_WRITE 0x00000000 68#define E1000_I2CCMD_READY 0x20000000 69#define E1000_I2CCMD_ERROR 0x80000000 70#define E1000_MAX_SGMII_PHY_REG_ADDR 255 71#define E1000_I2CCMD_PHY_TIMEOUT 200 72#define E1000_IVAR_VALID 0x80 73#define E1000_GPIE_NSICR 0x00000001 74#define E1000_GPIE_MSIX_MODE 0x00000010 75#define E1000_GPIE_EIAME 0x40000000 76#define E1000_GPIE_PBA 0x80000000 77 78/* Receive Descriptor bit definitions */ 79#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 80#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 81#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 82#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 83#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 84#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 85#define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */ 86 87#define E1000_RXDEXT_STATERR_CE 0x01000000 88#define E1000_RXDEXT_STATERR_SE 0x02000000 89#define E1000_RXDEXT_STATERR_SEQ 0x04000000 90#define E1000_RXDEXT_STATERR_CXE 0x10000000 91#define E1000_RXDEXT_STATERR_TCPE 0x20000000 92#define E1000_RXDEXT_STATERR_IPE 0x40000000 93#define E1000_RXDEXT_STATERR_RXE 0x80000000 94 95/* Same mask, but for extended and packet split descriptors */ 96#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 97 E1000_RXDEXT_STATERR_CE | \ 98 E1000_RXDEXT_STATERR_SE | \ 99 E1000_RXDEXT_STATERR_SEQ | \ 100 E1000_RXDEXT_STATERR_CXE | \ 101 E1000_RXDEXT_STATERR_RXE) 102 103#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 104#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 105#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 106#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 107#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 108 109 110/* Management Control */ 111#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 112#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 113/* Enable Neighbor Discovery Filtering */ 114#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 115#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 116/* Enable MAC address filtering */ 117#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 118 119/* Receive Control */ 120#define E1000_RCTL_EN 0x00000002 /* enable */ 121#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 122#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 123#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 124#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 125#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 126#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 127#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 128#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 129#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 130#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 131#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 132#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 133#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 134#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 135 136/* 137 * Use byte values for the following shift parameters 138 * Usage: 139 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 140 * E1000_PSRCTL_BSIZE0_MASK) | 141 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 142 * E1000_PSRCTL_BSIZE1_MASK) | 143 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 144 * E1000_PSRCTL_BSIZE2_MASK) | 145 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 146 * E1000_PSRCTL_BSIZE3_MASK)) 147 * where value0 = [128..16256], default=256 148 * value1 = [1024..64512], default=4096 149 * value2 = [0..64512], default=4096 150 * value3 = [0..64512], default=0 151 */ 152 153#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 154#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 155#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 156#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 157 158#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 159#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 160#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 161#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 162 163/* SWFW_SYNC Definitions */ 164#define E1000_SWFW_EEP_SM 0x1 165#define E1000_SWFW_PHY0_SM 0x2 166#define E1000_SWFW_PHY1_SM 0x4 167#define E1000_SWFW_PHY2_SM 0x20 168#define E1000_SWFW_PHY3_SM 0x40 169 170/* FACTPS Definitions */ 171/* Device Control */ 172#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 173#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 174#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 175#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 176#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 177#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 178#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 179#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 180#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 181#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 182#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 183/* Defined polarity of Dock/Undock indication in SDP[0] */ 184/* Reset both PHY ports, through PHYRST_N pin */ 185/* enable link status from external LINK_0 and LINK_1 pins */ 186#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 187#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 188#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 189#define E1000_CTRL_RST 0x04000000 /* Global reset */ 190#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 191#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 192#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 193#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 194/* Initiate an interrupt to manageability engine */ 195#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 196 197/* Bit definitions for the Management Data IO (MDIO) and Management Data 198 * Clock (MDC) pins in the Device Control Register. 199 */ 200 201#define E1000_CONNSW_ENRGSRC 0x4 202#define E1000_PCS_CFG_PCS_EN 8 203#define E1000_PCS_LCTL_FLV_LINK_UP 1 204#define E1000_PCS_LCTL_FSV_100 2 205#define E1000_PCS_LCTL_FSV_1000 4 206#define E1000_PCS_LCTL_FDV_FULL 8 207#define E1000_PCS_LCTL_FSD 0x10 208#define E1000_PCS_LCTL_FORCE_LINK 0x20 209#define E1000_PCS_LCTL_FORCE_FCTRL 0x80 210#define E1000_PCS_LCTL_AN_ENABLE 0x10000 211#define E1000_PCS_LCTL_AN_RESTART 0x20000 212#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 213#define E1000_ENABLE_SERDES_LOOPBACK 0x0410 214 215#define E1000_PCS_LSTS_LINK_OK 1 216#define E1000_PCS_LSTS_SPEED_100 2 217#define E1000_PCS_LSTS_SPEED_1000 4 218#define E1000_PCS_LSTS_DUPLEX_FULL 8 219#define E1000_PCS_LSTS_SYNK_OK 0x10 220 221/* Device Status */ 222#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 223#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 224#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 225#define E1000_STATUS_FUNC_SHIFT 2 226#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 227#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 228#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 229#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 230/* Change in Dock/Undock state. Clear on write '0'. */ 231/* Status of Master requests. */ 232#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 233/* BMC external code execution disabled */ 234 235/* Constants used to intrepret the masked PCI-X bus speed. */ 236 237#define SPEED_10 10 238#define SPEED_100 100 239#define SPEED_1000 1000 240#define HALF_DUPLEX 1 241#define FULL_DUPLEX 2 242 243 244#define ADVERTISE_10_HALF 0x0001 245#define ADVERTISE_10_FULL 0x0002 246#define ADVERTISE_100_HALF 0x0004 247#define ADVERTISE_100_FULL 0x0008 248#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 249#define ADVERTISE_1000_FULL 0x0020 250 251/* 1000/H is not supported, nor spec-compliant. */ 252#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 253 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 254 ADVERTISE_1000_FULL) 255#define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 256 ADVERTISE_100_HALF | ADVERTISE_100_FULL) 257#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 258#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 259#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ 260 ADVERTISE_1000_FULL) 261#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 262 263#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 264 265/* LED Control */ 266#define E1000_LEDCTL_LED0_MODE_SHIFT 0 267#define E1000_LEDCTL_LED0_BLINK 0x00000080 268 269#define E1000_LEDCTL_MODE_LED_ON 0xE 270#define E1000_LEDCTL_MODE_LED_OFF 0xF 271 272/* Transmit Descriptor bit definitions */ 273#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 274#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 275#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 276#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 277#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 278#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 279#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 280/* Extended desc bits for Linksec and timesync */ 281 282/* Transmit Control */ 283#define E1000_TCTL_EN 0x00000002 /* enable tx */ 284#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 285#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 286#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 287#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 288 289/* Transmit Arbitration Count */ 290 291/* SerDes Control */ 292#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 293 294/* Receive Checksum Control */ 295#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 296#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 297#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 298#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 299 300/* Header split receive */ 301#define E1000_RFCTL_LEF 0x00040000 302 303/* Collision related configuration parameters */ 304#define E1000_COLLISION_THRESHOLD 15 305#define E1000_CT_SHIFT 4 306#define E1000_COLLISION_DISTANCE 63 307#define E1000_COLD_SHIFT 12 308 309/* Ethertype field values */ 310#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 311 312#define MAX_JUMBO_FRAME_SIZE 0x3F00 313 314/* PBA constants */ 315#define E1000_PBA_34K 0x0022 316#define E1000_PBA_64K 0x0040 /* 64KB */ 317 318/* SW Semaphore Register */ 319#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 320#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 321 322/* Interrupt Cause Read */ 323#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 324#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 325#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 326#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 327#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 328#define E1000_ICR_VMMB 0x00000100 /* VM MB event */ 329#define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 330/* If this bit asserted, the driver should claim the interrupt */ 331#define E1000_ICR_INT_ASSERTED 0x80000000 332/* LAN connected device generates an interrupt */ 333#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 334 335/* Extended Interrupt Cause Read */ 336#define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 337#define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 338#define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 339#define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 340#define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 341#define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 342#define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 343#define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 344#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 345/* TCP Timer */ 346 347/* 348 * This defines the bits that are set in the Interrupt Mask 349 * Set/Read Register. Each bit is documented below: 350 * o RXT0 = Receiver Timer Interrupt (ring 0) 351 * o TXDW = Transmit Descriptor Written Back 352 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 353 * o RXSEQ = Receive Sequence Error 354 * o LSC = Link Status Change 355 */ 356#define IMS_ENABLE_MASK ( \ 357 E1000_IMS_RXT0 | \ 358 E1000_IMS_TXDW | \ 359 E1000_IMS_RXDMT0 | \ 360 E1000_IMS_RXSEQ | \ 361 E1000_IMS_LSC | \ 362 E1000_IMS_DOUTSYNC) 363 364/* Interrupt Mask Set */ 365#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 366#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 367#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ 368#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 369#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 370#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 371#define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ 372#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 373 374/* Extended Interrupt Mask Set */ 375#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 376 377/* Interrupt Cause Set */ 378#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 379#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 380#define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */ 381 382/* Extended Interrupt Cause Set */ 383 384/* Transmit Descriptor Control */ 385/* Enable the counting of descriptors still to be processed. */ 386 387/* Flow Control Constants */ 388#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 389#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 390#define FLOW_CONTROL_TYPE 0x8808 391 392/* 802.1q VLAN Packet Size */ 393#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 394#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 395 396/* Receive Address */ 397/* 398 * Number of high/low register pairs in the RAR. The RAR (Receive Address 399 * Registers) holds the directed and multicast addresses that we monitor. 400 * Technically, we have 16 spots. However, we reserve one of these spots 401 * (RAR[15]) for our directed address used by controllers with 402 * manageability enabled, allowing us room for 15 multicast addresses. 403 */ 404#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 405#define E1000_RAL_MAC_ADDR_LEN 4 406#define E1000_RAH_MAC_ADDR_LEN 2 407#define E1000_RAH_POOL_MASK 0x03FC0000 408#define E1000_RAH_POOL_1 0x00040000 409 410/* Error Codes */ 411#define E1000_ERR_NVM 1 412#define E1000_ERR_PHY 2 413#define E1000_ERR_CONFIG 3 414#define E1000_ERR_PARAM 4 415#define E1000_ERR_MAC_INIT 5 416#define E1000_ERR_RESET 9 417#define E1000_ERR_MASTER_REQUESTS_PENDING 10 418#define E1000_BLK_PHY_RESET 12 419#define E1000_ERR_SWFW_SYNC 13 420#define E1000_NOT_IMPLEMENTED 14 421#define E1000_ERR_MBX 15 422 423/* Loop limit on how long we wait for auto-negotiation to complete */ 424#define COPPER_LINK_UP_LIMIT 10 425#define PHY_AUTO_NEG_LIMIT 45 426#define PHY_FORCE_LIMIT 20 427/* Number of 100 microseconds we wait for PCI Express master disable */ 428#define MASTER_DISABLE_TIMEOUT 800 429/* Number of milliseconds we wait for PHY configuration done after MAC reset */ 430#define PHY_CFG_TIMEOUT 100 431/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 432/* Number of milliseconds for NVM auto read done after MAC reset. */ 433#define AUTO_READ_DONE_TIMEOUT 10 434 435/* Flow Control */ 436#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 437 438#define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */ 439#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */ 440 441#define E1000_TSYNCRXCTL_VALID 0x00000001 /* rx timestamp valid */ 442#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* rx type mask */ 443#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 444#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 445#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 446#define E1000_TSYNCRXCTL_TYPE_ALL 0x08 447#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 448#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable rx timestampping */ 449 450#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 451#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 452#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 453#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 454#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 455#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 456 457#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 458#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 459#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 460#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 461#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 462#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 463#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 464#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 465#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 466#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 467#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 468 469#define E1000_TIMINCA_16NS_SHIFT 24 470 471#define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 472#define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 473#define E1000_MDICNFG_PHY_MASK 0x03E00000 474#define E1000_MDICNFG_PHY_SHIFT 21 475 476/* PCI Express Control */ 477#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 478#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 479#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 480#define E1000_GCR_CAP_VER2 0x00040000 481 482/* PHY Control Register */ 483#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 484#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 485#define MII_CR_POWER_DOWN 0x0800 /* Power down */ 486#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 487#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 488#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 489#define MII_CR_SPEED_1000 0x0040 490#define MII_CR_SPEED_100 0x2000 491#define MII_CR_SPEED_10 0x0000 492 493/* PHY Status Register */ 494#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 495#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 496 497/* Autoneg Advertisement Register */ 498#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 499#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 500#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 501#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 502#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 503#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 504 505/* Link Partner Ability Register (Base Page) */ 506#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 507#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 508 509/* Autoneg Expansion Register */ 510 511/* 1000BASE-T Control Register */ 512#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 513#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 514#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 515 /* 0=Configure PHY as Slave */ 516#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 517 /* 0=Automatic Master/Slave config */ 518 519/* 1000BASE-T Status Register */ 520#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 521#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 522 523 524/* PHY 1000 MII Register/Bit Definitions */ 525/* PHY Registers defined by IEEE */ 526#define PHY_CONTROL 0x00 /* Control Register */ 527#define PHY_STATUS 0x01 /* Status Register */ 528#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 529#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 530#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 531#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 532#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 533#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 534 535/* NVM Control */ 536#define E1000_EECD_SK 0x00000001 /* NVM Clock */ 537#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 538#define E1000_EECD_DI 0x00000004 /* NVM Data In */ 539#define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 540#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 541#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 542#define E1000_EECD_PRES 0x00000100 /* NVM Present */ 543/* NVM Addressing bits based on type 0=small, 1=large */ 544#define E1000_EECD_ADDR_BITS 0x00000400 545#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 546#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 547#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 548#define E1000_EECD_SIZE_EX_SHIFT 11 549 550/* Offset to data in NVM read/write registers */ 551#define E1000_NVM_RW_REG_DATA 16 552#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 553#define E1000_NVM_RW_REG_START 1 /* Start operation */ 554#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 555#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 556 557/* NVM Word Offsets */ 558#define NVM_ID_LED_SETTINGS 0x0004 559/* For SERDES output amplitude adjustment. */ 560#define NVM_INIT_CONTROL2_REG 0x000F 561#define NVM_INIT_CONTROL3_PORT_B 0x0014 562#define NVM_INIT_CONTROL3_PORT_A 0x0024 563#define NVM_ALT_MAC_ADDR_PTR 0x0037 564#define NVM_CHECKSUM_REG 0x003F 565 566#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 567#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 568#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 569#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 570 571#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0) 572 573/* Mask bits for fields in Word 0x24 of the NVM */ 574#define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ 575#define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */ 576 577/* Mask bits for fields in Word 0x0f of the NVM */ 578#define NVM_WORD0F_PAUSE_MASK 0x3000 579#define NVM_WORD0F_ASM_DIR 0x2000 580 581/* Mask bits for fields in Word 0x1a of the NVM */ 582 583/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 584#define NVM_SUM 0xBABA 585 586#define NVM_PBA_OFFSET_0 8 587#define NVM_PBA_OFFSET_1 9 588#define NVM_WORD_SIZE_BASE_SHIFT 6 589 590/* NVM Commands - Microwire */ 591 592/* NVM Commands - SPI */ 593#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 594#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 595#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 596#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 597#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 598 599/* SPI NVM Status Register */ 600#define NVM_STATUS_RDY_SPI 0x01 601 602/* Word definitions for ID LED Settings */ 603#define ID_LED_RESERVED_0000 0x0000 604#define ID_LED_RESERVED_FFFF 0xFFFF 605#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 606 (ID_LED_OFF1_OFF2 << 8) | \ 607 (ID_LED_DEF1_DEF2 << 4) | \ 608 (ID_LED_DEF1_DEF2)) 609#define ID_LED_DEF1_DEF2 0x1 610#define ID_LED_DEF1_ON2 0x2 611#define ID_LED_DEF1_OFF2 0x3 612#define ID_LED_ON1_DEF2 0x4 613#define ID_LED_ON1_ON2 0x5 614#define ID_LED_ON1_OFF2 0x6 615#define ID_LED_OFF1_DEF2 0x7 616#define ID_LED_OFF1_ON2 0x8 617#define ID_LED_OFF1_OFF2 0x9 618 619#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 620#define IGP_ACTIVITY_LED_ENABLE 0x0300 621#define IGP_LED3_MODE 0x07000000 622 623/* PCI/PCI-X/PCI-EX Config space */ 624#define PCIE_DEVICE_CONTROL2 0x28 625#define PCIE_DEVICE_CONTROL2_16ms 0x0005 626 627#define PHY_REVISION_MASK 0xFFFFFFF0 628#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 629#define MAX_PHY_MULTI_PAGE_REG 0xF 630 631/* Bit definitions for valid PHY IDs. */ 632/* 633 * I = Integrated 634 * E = External 635 */ 636#define M88E1111_I_PHY_ID 0x01410CC0 637#define IGP03E1000_E_PHY_ID 0x02A80390 638#define I82580_I_PHY_ID 0x015403A0 639#define I350_I_PHY_ID 0x015403B0 640#define M88_VENDOR 0x0141 641 642/* M88E1000 Specific Registers */ 643#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 644#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 645#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 646 647#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 648#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 649 650/* M88E1000 PHY Specific Control Register */ 651#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 652/* 1=CLK125 low, 0=CLK125 toggling */ 653#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 654 /* Manual MDI configuration */ 655#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 656/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 657#define M88E1000_PSCR_AUTO_X_1000T 0x0040 658/* Auto crossover enabled all speeds */ 659#define M88E1000_PSCR_AUTO_X_MODE 0x0060 660/* 661 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold 662 * 0=Normal 10BASE-T Rx Threshold 663 */ 664/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ 665#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 666 667/* M88E1000 PHY Specific Status Register */ 668#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 669#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 670#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 671/* 672 * 0 = <50M 673 * 1 = 50-80M 674 * 2 = 80-110M 675 * 3 = 110-140M 676 * 4 = >140M 677 */ 678#define M88E1000_PSSR_CABLE_LENGTH 0x0380 679#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 680#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 681 682#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 683 684/* M88E1000 Extended PHY Specific Control Register */ 685/* 686 * 1 = Lost lock detect enabled. 687 * Will assert lost lock and bring 688 * link down if idle not seen 689 * within 1ms in 1000BASE-T 690 */ 691/* 692 * Number of times we will attempt to autonegotiate before downshifting if we 693 * are the master 694 */ 695#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 696#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 697/* 698 * Number of times we will attempt to autonegotiate before downshifting if we 699 * are the slave 700 */ 701#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 702#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 703#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 704 705/* M88EC018 Rev 2 specific DownShift settings */ 706#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 707#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 708 709/* MDI Control */ 710#define E1000_MDIC_DATA_MASK 0x0000FFFF 711#define E1000_MDIC_REG_MASK 0x001F0000 712#define E1000_MDIC_REG_SHIFT 16 713#define E1000_MDIC_PHY_MASK 0x03E00000 714#define E1000_MDIC_PHY_SHIFT 21 715#define E1000_MDIC_OP_WRITE 0x04000000 716#define E1000_MDIC_OP_READ 0x08000000 717#define E1000_MDIC_READY 0x10000000 718#define E1000_MDIC_INT_EN 0x20000000 719#define E1000_MDIC_ERROR 0x40000000 720#define E1000_MDIC_DEST 0x80000000 721 722/* SerDes Control */ 723#define E1000_GEN_CTL_READY 0x80000000 724#define E1000_GEN_CTL_ADDRESS_SHIFT 8 725#define E1000_GEN_POLL_TIMEOUT 640 726 727#define E1000_VFTA_ENTRY_SHIFT 5 728#define E1000_VFTA_ENTRY_MASK 0x7F 729#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 730 731/* DMA Coalescing register fields */ 732#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision based 733 on DMA coal */ 734 735#endif 736