1/******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2010 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27*******************************************************************************/ 28 29/* 30 * 82571EB Gigabit Ethernet Controller 31 * 82571EB Gigabit Ethernet Controller (Copper) 32 * 82571EB Gigabit Ethernet Controller (Fiber) 33 * 82571EB Dual Port Gigabit Mezzanine Adapter 34 * 82571EB Quad Port Gigabit Mezzanine Adapter 35 * 82571PT Gigabit PT Quad Port Server ExpressModule 36 * 82572EI Gigabit Ethernet Controller (Copper) 37 * 82572EI Gigabit Ethernet Controller (Fiber) 38 * 82572EI Gigabit Ethernet Controller 39 * 82573V Gigabit Ethernet Controller (Copper) 40 * 82573E Gigabit Ethernet Controller (Copper) 41 * 82573L Gigabit Ethernet Controller 42 * 82574L Gigabit Network Connection 43 * 82583V Gigabit Network Connection 44 */ 45 46#include "e1000.h" 47 48#define ID_LED_RESERVED_F746 0xF746 49#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ 50 (ID_LED_OFF1_ON2 << 8) | \ 51 (ID_LED_DEF1_DEF2 << 4) | \ 52 (ID_LED_DEF1_DEF2)) 53 54#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 55 56#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ 57 58static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 59static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 60static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 61static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); 62static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 63 u16 words, u16 *data); 64static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 65static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 66static s32 e1000_setup_link_82571(struct e1000_hw *hw); 67static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 68static void e1000_clear_vfta_82571(struct e1000_hw *hw); 69static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); 70static s32 e1000_led_on_82574(struct e1000_hw *hw); 71static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 72static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); 73 74/** 75 * e1000_init_phy_params_82571 - Init PHY func ptrs. 76 * @hw: pointer to the HW structure 77 **/ 78static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 79{ 80 struct e1000_phy_info *phy = &hw->phy; 81 s32 ret_val; 82 83 if (hw->phy.media_type != e1000_media_type_copper) { 84 phy->type = e1000_phy_none; 85 return 0; 86 } 87 88 phy->addr = 1; 89 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 90 phy->reset_delay_us = 100; 91 92 phy->ops.power_up = e1000_power_up_phy_copper; 93 phy->ops.power_down = e1000_power_down_phy_copper_82571; 94 95 switch (hw->mac.type) { 96 case e1000_82571: 97 case e1000_82572: 98 phy->type = e1000_phy_igp_2; 99 break; 100 case e1000_82573: 101 phy->type = e1000_phy_m88; 102 break; 103 case e1000_82574: 104 case e1000_82583: 105 phy->type = e1000_phy_bm; 106 break; 107 default: 108 return -E1000_ERR_PHY; 109 break; 110 } 111 112 /* This can only be done after all function pointers are setup. */ 113 ret_val = e1000_get_phy_id_82571(hw); 114 115 /* Verify phy id */ 116 switch (hw->mac.type) { 117 case e1000_82571: 118 case e1000_82572: 119 if (phy->id != IGP01E1000_I_PHY_ID) 120 return -E1000_ERR_PHY; 121 break; 122 case e1000_82573: 123 if (phy->id != M88E1111_I_PHY_ID) 124 return -E1000_ERR_PHY; 125 break; 126 case e1000_82574: 127 case e1000_82583: 128 if (phy->id != BME1000_E_PHY_ID_R2) 129 return -E1000_ERR_PHY; 130 break; 131 default: 132 return -E1000_ERR_PHY; 133 break; 134 } 135 136 return 0; 137} 138 139/** 140 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 141 * @hw: pointer to the HW structure 142 **/ 143static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 144{ 145 struct e1000_nvm_info *nvm = &hw->nvm; 146 u32 eecd = er32(EECD); 147 u16 size; 148 149 nvm->opcode_bits = 8; 150 nvm->delay_usec = 1; 151 switch (nvm->override) { 152 case e1000_nvm_override_spi_large: 153 nvm->page_size = 32; 154 nvm->address_bits = 16; 155 break; 156 case e1000_nvm_override_spi_small: 157 nvm->page_size = 8; 158 nvm->address_bits = 8; 159 break; 160 default: 161 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 162 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 163 break; 164 } 165 166 switch (hw->mac.type) { 167 case e1000_82573: 168 case e1000_82574: 169 case e1000_82583: 170 if (((eecd >> 15) & 0x3) == 0x3) { 171 nvm->type = e1000_nvm_flash_hw; 172 nvm->word_size = 2048; 173 /* 174 * Autonomous Flash update bit must be cleared due 175 * to Flash update issue. 176 */ 177 eecd &= ~E1000_EECD_AUPDEN; 178 ew32(EECD, eecd); 179 break; 180 } 181 /* Fall Through */ 182 default: 183 nvm->type = e1000_nvm_eeprom_spi; 184 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 185 E1000_EECD_SIZE_EX_SHIFT); 186 /* 187 * Added to a constant, "size" becomes the left-shift value 188 * for setting word_size. 189 */ 190 size += NVM_WORD_SIZE_BASE_SHIFT; 191 192 /* EEPROM access above 16k is unsupported */ 193 if (size > 14) 194 size = 14; 195 nvm->word_size = 1 << size; 196 break; 197 } 198 199 return 0; 200} 201 202/** 203 * e1000_init_mac_params_82571 - Init MAC func ptrs. 204 * @hw: pointer to the HW structure 205 **/ 206static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) 207{ 208 struct e1000_hw *hw = &adapter->hw; 209 struct e1000_mac_info *mac = &hw->mac; 210 struct e1000_mac_operations *func = &mac->ops; 211 u32 swsm = 0; 212 u32 swsm2 = 0; 213 bool force_clear_smbi = false; 214 215 /* Set media type */ 216 switch (adapter->pdev->device) { 217 case E1000_DEV_ID_82571EB_FIBER: 218 case E1000_DEV_ID_82572EI_FIBER: 219 case E1000_DEV_ID_82571EB_QUAD_FIBER: 220 hw->phy.media_type = e1000_media_type_fiber; 221 break; 222 case E1000_DEV_ID_82571EB_SERDES: 223 case E1000_DEV_ID_82572EI_SERDES: 224 case E1000_DEV_ID_82571EB_SERDES_DUAL: 225 case E1000_DEV_ID_82571EB_SERDES_QUAD: 226 hw->phy.media_type = e1000_media_type_internal_serdes; 227 break; 228 default: 229 hw->phy.media_type = e1000_media_type_copper; 230 break; 231 } 232 233 /* Set mta register count */ 234 mac->mta_reg_count = 128; 235 /* Set rar entry count */ 236 mac->rar_entry_count = E1000_RAR_ENTRIES; 237 /* Adaptive IFS supported */ 238 mac->adaptive_ifs = true; 239 240 /* check for link */ 241 switch (hw->phy.media_type) { 242 case e1000_media_type_copper: 243 func->setup_physical_interface = e1000_setup_copper_link_82571; 244 func->check_for_link = e1000e_check_for_copper_link; 245 func->get_link_up_info = e1000e_get_speed_and_duplex_copper; 246 break; 247 case e1000_media_type_fiber: 248 func->setup_physical_interface = 249 e1000_setup_fiber_serdes_link_82571; 250 func->check_for_link = e1000e_check_for_fiber_link; 251 func->get_link_up_info = 252 e1000e_get_speed_and_duplex_fiber_serdes; 253 break; 254 case e1000_media_type_internal_serdes: 255 func->setup_physical_interface = 256 e1000_setup_fiber_serdes_link_82571; 257 func->check_for_link = e1000_check_for_serdes_link_82571; 258 func->get_link_up_info = 259 e1000e_get_speed_and_duplex_fiber_serdes; 260 break; 261 default: 262 return -E1000_ERR_CONFIG; 263 break; 264 } 265 266 switch (hw->mac.type) { 267 case e1000_82573: 268 func->set_lan_id = e1000_set_lan_id_single_port; 269 func->check_mng_mode = e1000e_check_mng_mode_generic; 270 func->led_on = e1000e_led_on_generic; 271 272 /* FWSM register */ 273 mac->has_fwsm = true; 274 /* 275 * ARC supported; valid only if manageability features are 276 * enabled. 277 */ 278 mac->arc_subsystem_valid = 279 (er32(FWSM) & E1000_FWSM_MODE_MASK) 280 ? true : false; 281 break; 282 case e1000_82574: 283 case e1000_82583: 284 func->set_lan_id = e1000_set_lan_id_single_port; 285 func->check_mng_mode = e1000_check_mng_mode_82574; 286 func->led_on = e1000_led_on_82574; 287 break; 288 default: 289 func->check_mng_mode = e1000e_check_mng_mode_generic; 290 func->led_on = e1000e_led_on_generic; 291 292 /* FWSM register */ 293 mac->has_fwsm = true; 294 break; 295 } 296 297 /* 298 * Ensure that the inter-port SWSM.SMBI lock bit is clear before 299 * first NVM or PHY acess. This should be done for single-port 300 * devices, and for one port only on dual-port devices so that 301 * for those devices we can still use the SMBI lock to synchronize 302 * inter-port accesses to the PHY & NVM. 303 */ 304 switch (hw->mac.type) { 305 case e1000_82571: 306 case e1000_82572: 307 swsm2 = er32(SWSM2); 308 309 if (!(swsm2 & E1000_SWSM2_LOCK)) { 310 /* Only do this for the first interface on this card */ 311 ew32(SWSM2, 312 swsm2 | E1000_SWSM2_LOCK); 313 force_clear_smbi = true; 314 } else 315 force_clear_smbi = false; 316 break; 317 default: 318 force_clear_smbi = true; 319 break; 320 } 321 322 if (force_clear_smbi) { 323 /* Make sure SWSM.SMBI is clear */ 324 swsm = er32(SWSM); 325 if (swsm & E1000_SWSM_SMBI) { 326 /* This bit should not be set on a first interface, and 327 * indicates that the bootagent or EFI code has 328 * improperly left this bit enabled 329 */ 330 e_dbg("Please update your 82571 Bootagent\n"); 331 } 332 ew32(SWSM, swsm & ~E1000_SWSM_SMBI); 333 } 334 335 /* 336 * Initialize device specific counter of SMBI acquisition 337 * timeouts. 338 */ 339 hw->dev_spec.e82571.smb_counter = 0; 340 341 return 0; 342} 343 344static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) 345{ 346 struct e1000_hw *hw = &adapter->hw; 347 static int global_quad_port_a; /* global port a indication */ 348 struct pci_dev *pdev = adapter->pdev; 349 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; 350 s32 rc; 351 352 rc = e1000_init_mac_params_82571(adapter); 353 if (rc) 354 return rc; 355 356 rc = e1000_init_nvm_params_82571(hw); 357 if (rc) 358 return rc; 359 360 rc = e1000_init_phy_params_82571(hw); 361 if (rc) 362 return rc; 363 364 /* tag quad port adapters first, it's used below */ 365 switch (pdev->device) { 366 case E1000_DEV_ID_82571EB_QUAD_COPPER: 367 case E1000_DEV_ID_82571EB_QUAD_FIBER: 368 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 369 case E1000_DEV_ID_82571PT_QUAD_COPPER: 370 adapter->flags |= FLAG_IS_QUAD_PORT; 371 /* mark the first port */ 372 if (global_quad_port_a == 0) 373 adapter->flags |= FLAG_IS_QUAD_PORT_A; 374 /* Reset for multiple quad port adapters */ 375 global_quad_port_a++; 376 if (global_quad_port_a == 4) 377 global_quad_port_a = 0; 378 break; 379 default: 380 break; 381 } 382 383 switch (adapter->hw.mac.type) { 384 case e1000_82571: 385 /* these dual ports don't have WoL on port B at all */ 386 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || 387 (pdev->device == E1000_DEV_ID_82571EB_SERDES) || 388 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && 389 (is_port_b)) 390 adapter->flags &= ~FLAG_HAS_WOL; 391 /* quad ports only support WoL on port A */ 392 if (adapter->flags & FLAG_IS_QUAD_PORT && 393 (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) 394 adapter->flags &= ~FLAG_HAS_WOL; 395 /* Does not support WoL on any port */ 396 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) 397 adapter->flags &= ~FLAG_HAS_WOL; 398 break; 399 case e1000_82573: 400 case e1000_82574: 401 case e1000_82583: 402 /* Disable ASPM L0s due to hardware errata */ 403 e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L0S); 404 405 if (pdev->device == E1000_DEV_ID_82573L) { 406 adapter->flags |= FLAG_HAS_JUMBO_FRAMES; 407 adapter->max_hw_frame_size = DEFAULT_JUMBO; 408 } 409 break; 410 default: 411 break; 412 } 413 414 return 0; 415} 416 417/** 418 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 419 * @hw: pointer to the HW structure 420 * 421 * Reads the PHY registers and stores the PHY ID and possibly the PHY 422 * revision in the hardware structure. 423 **/ 424static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 425{ 426 struct e1000_phy_info *phy = &hw->phy; 427 s32 ret_val; 428 u16 phy_id = 0; 429 430 switch (hw->mac.type) { 431 case e1000_82571: 432 case e1000_82572: 433 /* 434 * The 82571 firmware may still be configuring the PHY. 435 * In this case, we cannot access the PHY until the 436 * configuration is done. So we explicitly set the 437 * PHY ID. 438 */ 439 phy->id = IGP01E1000_I_PHY_ID; 440 break; 441 case e1000_82573: 442 return e1000e_get_phy_id(hw); 443 break; 444 case e1000_82574: 445 case e1000_82583: 446 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); 447 if (ret_val) 448 return ret_val; 449 450 phy->id = (u32)(phy_id << 16); 451 udelay(20); 452 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); 453 if (ret_val) 454 return ret_val; 455 456 phy->id |= (u32)(phy_id); 457 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 458 break; 459 default: 460 return -E1000_ERR_PHY; 461 break; 462 } 463 464 return 0; 465} 466 467/** 468 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 469 * @hw: pointer to the HW structure 470 * 471 * Acquire the HW semaphore to access the PHY or NVM 472 **/ 473static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 474{ 475 u32 swsm; 476 s32 sw_timeout = hw->nvm.word_size + 1; 477 s32 fw_timeout = hw->nvm.word_size + 1; 478 s32 i = 0; 479 480 /* 481 * If we have timedout 3 times on trying to acquire 482 * the inter-port SMBI semaphore, there is old code 483 * operating on the other port, and it is not 484 * releasing SMBI. Modify the number of times that 485 * we try for the semaphore to interwork with this 486 * older code. 487 */ 488 if (hw->dev_spec.e82571.smb_counter > 2) 489 sw_timeout = 1; 490 491 /* Get the SW semaphore */ 492 while (i < sw_timeout) { 493 swsm = er32(SWSM); 494 if (!(swsm & E1000_SWSM_SMBI)) 495 break; 496 497 udelay(50); 498 i++; 499 } 500 501 if (i == sw_timeout) { 502 e_dbg("Driver can't access device - SMBI bit is set.\n"); 503 hw->dev_spec.e82571.smb_counter++; 504 } 505 /* Get the FW semaphore. */ 506 for (i = 0; i < fw_timeout; i++) { 507 swsm = er32(SWSM); 508 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); 509 510 /* Semaphore acquired if bit latched */ 511 if (er32(SWSM) & E1000_SWSM_SWESMBI) 512 break; 513 514 udelay(50); 515 } 516 517 if (i == fw_timeout) { 518 /* Release semaphores */ 519 e1000_put_hw_semaphore_82571(hw); 520 e_dbg("Driver can't access the NVM\n"); 521 return -E1000_ERR_NVM; 522 } 523 524 return 0; 525} 526 527/** 528 * e1000_put_hw_semaphore_82571 - Release hardware semaphore 529 * @hw: pointer to the HW structure 530 * 531 * Release hardware semaphore used to access the PHY or NVM 532 **/ 533static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 534{ 535 u32 swsm; 536 537 swsm = er32(SWSM); 538 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 539 ew32(SWSM, swsm); 540} 541 542/** 543 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 544 * @hw: pointer to the HW structure 545 * 546 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 547 * Then for non-82573 hardware, set the EEPROM access request bit and wait 548 * for EEPROM access grant bit. If the access grant bit is not set, release 549 * hardware semaphore. 550 **/ 551static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 552{ 553 s32 ret_val; 554 555 ret_val = e1000_get_hw_semaphore_82571(hw); 556 if (ret_val) 557 return ret_val; 558 559 switch (hw->mac.type) { 560 case e1000_82573: 561 case e1000_82574: 562 case e1000_82583: 563 break; 564 default: 565 ret_val = e1000e_acquire_nvm(hw); 566 break; 567 } 568 569 if (ret_val) 570 e1000_put_hw_semaphore_82571(hw); 571 572 return ret_val; 573} 574 575/** 576 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 577 * @hw: pointer to the HW structure 578 * 579 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 580 **/ 581static void e1000_release_nvm_82571(struct e1000_hw *hw) 582{ 583 e1000e_release_nvm(hw); 584 e1000_put_hw_semaphore_82571(hw); 585} 586 587/** 588 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 589 * @hw: pointer to the HW structure 590 * @offset: offset within the EEPROM to be written to 591 * @words: number of words to write 592 * @data: 16 bit word(s) to be written to the EEPROM 593 * 594 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 595 * 596 * If e1000e_update_nvm_checksum is not called after this function, the 597 * EEPROM will most likely contain an invalid checksum. 598 **/ 599static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 600 u16 *data) 601{ 602 s32 ret_val; 603 604 switch (hw->mac.type) { 605 case e1000_82573: 606 case e1000_82574: 607 case e1000_82583: 608 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 609 break; 610 case e1000_82571: 611 case e1000_82572: 612 ret_val = e1000e_write_nvm_spi(hw, offset, words, data); 613 break; 614 default: 615 ret_val = -E1000_ERR_NVM; 616 break; 617 } 618 619 return ret_val; 620} 621 622/** 623 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 624 * @hw: pointer to the HW structure 625 * 626 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 627 * up to the checksum. Then calculates the EEPROM checksum and writes the 628 * value to the EEPROM. 629 **/ 630static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 631{ 632 u32 eecd; 633 s32 ret_val; 634 u16 i; 635 636 ret_val = e1000e_update_nvm_checksum_generic(hw); 637 if (ret_val) 638 return ret_val; 639 640 /* 641 * If our nvm is an EEPROM, then we're done 642 * otherwise, commit the checksum to the flash NVM. 643 */ 644 if (hw->nvm.type != e1000_nvm_flash_hw) 645 return ret_val; 646 647 /* Check for pending operations. */ 648 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 649 msleep(1); 650 if ((er32(EECD) & E1000_EECD_FLUPD) == 0) 651 break; 652 } 653 654 if (i == E1000_FLASH_UPDATES) 655 return -E1000_ERR_NVM; 656 657 /* Reset the firmware if using STM opcode. */ 658 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { 659 /* 660 * The enabling of and the actual reset must be done 661 * in two write cycles. 662 */ 663 ew32(HICR, E1000_HICR_FW_RESET_ENABLE); 664 e1e_flush(); 665 ew32(HICR, E1000_HICR_FW_RESET); 666 } 667 668 /* Commit the write to flash */ 669 eecd = er32(EECD) | E1000_EECD_FLUPD; 670 ew32(EECD, eecd); 671 672 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 673 msleep(1); 674 if ((er32(EECD) & E1000_EECD_FLUPD) == 0) 675 break; 676 } 677 678 if (i == E1000_FLASH_UPDATES) 679 return -E1000_ERR_NVM; 680 681 return 0; 682} 683 684/** 685 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 686 * @hw: pointer to the HW structure 687 * 688 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 689 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 690 **/ 691static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 692{ 693 if (hw->nvm.type == e1000_nvm_flash_hw) 694 e1000_fix_nvm_checksum_82571(hw); 695 696 return e1000e_validate_nvm_checksum_generic(hw); 697} 698 699/** 700 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 701 * @hw: pointer to the HW structure 702 * @offset: offset within the EEPROM to be written to 703 * @words: number of words to write 704 * @data: 16 bit word(s) to be written to the EEPROM 705 * 706 * After checking for invalid values, poll the EEPROM to ensure the previous 707 * command has completed before trying to write the next word. After write 708 * poll for completion. 709 * 710 * If e1000e_update_nvm_checksum is not called after this function, the 711 * EEPROM will most likely contain an invalid checksum. 712 **/ 713static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 714 u16 words, u16 *data) 715{ 716 struct e1000_nvm_info *nvm = &hw->nvm; 717 u32 i, eewr = 0; 718 s32 ret_val = 0; 719 720 /* 721 * A check for invalid values: offset too large, too many words, 722 * and not enough words. 723 */ 724 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 725 (words == 0)) { 726 e_dbg("nvm parameter(s) out of bounds\n"); 727 return -E1000_ERR_NVM; 728 } 729 730 for (i = 0; i < words; i++) { 731 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 732 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 733 E1000_NVM_RW_REG_START; 734 735 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 736 if (ret_val) 737 break; 738 739 ew32(EEWR, eewr); 740 741 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 742 if (ret_val) 743 break; 744 } 745 746 return ret_val; 747} 748 749/** 750 * e1000_get_cfg_done_82571 - Poll for configuration done 751 * @hw: pointer to the HW structure 752 * 753 * Reads the management control register for the config done bit to be set. 754 **/ 755static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 756{ 757 s32 timeout = PHY_CFG_TIMEOUT; 758 759 while (timeout) { 760 if (er32(EEMNGCTL) & 761 E1000_NVM_CFG_DONE_PORT_0) 762 break; 763 msleep(1); 764 timeout--; 765 } 766 if (!timeout) { 767 e_dbg("MNG configuration cycle has not completed.\n"); 768 return -E1000_ERR_RESET; 769 } 770 771 return 0; 772} 773 774/** 775 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 776 * @hw: pointer to the HW structure 777 * @active: true to enable LPLU, false to disable 778 * 779 * Sets the LPLU D0 state according to the active flag. When activating LPLU 780 * this function also disables smart speed and vice versa. LPLU will not be 781 * activated unless the device autonegotiation advertisement meets standards 782 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 783 * pointer entry point only called by PHY setup routines. 784 **/ 785static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 786{ 787 struct e1000_phy_info *phy = &hw->phy; 788 s32 ret_val; 789 u16 data; 790 791 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); 792 if (ret_val) 793 return ret_val; 794 795 if (active) { 796 data |= IGP02E1000_PM_D0_LPLU; 797 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 798 if (ret_val) 799 return ret_val; 800 801 /* When LPLU is enabled, we should disable SmartSpeed */ 802 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 803 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 804 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 805 if (ret_val) 806 return ret_val; 807 } else { 808 data &= ~IGP02E1000_PM_D0_LPLU; 809 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 810 /* 811 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 812 * during Dx states where the power conservation is most 813 * important. During driver activity we should enable 814 * SmartSpeed, so performance is maintained. 815 */ 816 if (phy->smart_speed == e1000_smart_speed_on) { 817 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 818 &data); 819 if (ret_val) 820 return ret_val; 821 822 data |= IGP01E1000_PSCFR_SMART_SPEED; 823 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 824 data); 825 if (ret_val) 826 return ret_val; 827 } else if (phy->smart_speed == e1000_smart_speed_off) { 828 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 829 &data); 830 if (ret_val) 831 return ret_val; 832 833 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 834 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 835 data); 836 if (ret_val) 837 return ret_val; 838 } 839 } 840 841 return 0; 842} 843 844/** 845 * e1000_reset_hw_82571 - Reset hardware 846 * @hw: pointer to the HW structure 847 * 848 * This resets the hardware into a known state. 849 **/ 850static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 851{ 852 u32 ctrl, extcnf_ctrl, ctrl_ext, icr; 853 s32 ret_val; 854 u16 i = 0; 855 856 /* 857 * Prevent the PCI-E bus from sticking if there is no TLP connection 858 * on the last TLP read/write transaction when MAC is reset. 859 */ 860 ret_val = e1000e_disable_pcie_master(hw); 861 if (ret_val) 862 e_dbg("PCI-E Master disable polling has failed.\n"); 863 864 e_dbg("Masking off all interrupts\n"); 865 ew32(IMC, 0xffffffff); 866 867 ew32(RCTL, 0); 868 ew32(TCTL, E1000_TCTL_PSP); 869 e1e_flush(); 870 871 msleep(10); 872 873 /* 874 * Must acquire the MDIO ownership before MAC reset. 875 * Ownership defaults to firmware after a reset. 876 */ 877 switch (hw->mac.type) { 878 case e1000_82573: 879 case e1000_82574: 880 case e1000_82583: 881 extcnf_ctrl = er32(EXTCNF_CTRL); 882 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 883 884 do { 885 ew32(EXTCNF_CTRL, extcnf_ctrl); 886 extcnf_ctrl = er32(EXTCNF_CTRL); 887 888 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 889 break; 890 891 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 892 893 msleep(2); 894 i++; 895 } while (i < MDIO_OWNERSHIP_TIMEOUT); 896 break; 897 default: 898 break; 899 } 900 901 ctrl = er32(CTRL); 902 903 e_dbg("Issuing a global reset to MAC\n"); 904 ew32(CTRL, ctrl | E1000_CTRL_RST); 905 906 if (hw->nvm.type == e1000_nvm_flash_hw) { 907 udelay(10); 908 ctrl_ext = er32(CTRL_EXT); 909 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 910 ew32(CTRL_EXT, ctrl_ext); 911 e1e_flush(); 912 } 913 914 ret_val = e1000e_get_auto_rd_done(hw); 915 if (ret_val) 916 /* We don't want to continue accessing MAC registers. */ 917 return ret_val; 918 919 /* 920 * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 921 * Need to wait for Phy configuration completion before accessing 922 * NVM and Phy. 923 */ 924 925 switch (hw->mac.type) { 926 case e1000_82573: 927 case e1000_82574: 928 case e1000_82583: 929 msleep(25); 930 break; 931 default: 932 break; 933 } 934 935 /* Clear any pending interrupt events. */ 936 ew32(IMC, 0xffffffff); 937 icr = er32(ICR); 938 939 if (hw->mac.type == e1000_82571) { 940 /* Install any alternate MAC address into RAR0 */ 941 ret_val = e1000_check_alt_mac_addr_generic(hw); 942 if (ret_val) 943 return ret_val; 944 945 e1000e_set_laa_state_82571(hw, true); 946 } 947 948 /* Reinitialize the 82571 serdes link state machine */ 949 if (hw->phy.media_type == e1000_media_type_internal_serdes) 950 hw->mac.serdes_link_state = e1000_serdes_link_down; 951 952 return 0; 953} 954 955/** 956 * e1000_init_hw_82571 - Initialize hardware 957 * @hw: pointer to the HW structure 958 * 959 * This inits the hardware readying it for operation. 960 **/ 961static s32 e1000_init_hw_82571(struct e1000_hw *hw) 962{ 963 struct e1000_mac_info *mac = &hw->mac; 964 u32 reg_data; 965 s32 ret_val; 966 u16 i, rar_count = mac->rar_entry_count; 967 968 e1000_initialize_hw_bits_82571(hw); 969 970 /* Initialize identification LED */ 971 ret_val = e1000e_id_led_init(hw); 972 if (ret_val) 973 e_dbg("Error initializing identification LED\n"); 974 /* This is not fatal and we should not stop init due to this */ 975 976 /* Disabling VLAN filtering */ 977 e_dbg("Initializing the IEEE VLAN\n"); 978 mac->ops.clear_vfta(hw); 979 980 /* Setup the receive address. */ 981 if (e1000e_get_laa_state_82571(hw)) 982 rar_count--; 983 e1000e_init_rx_addrs(hw, rar_count); 984 985 /* Zero out the Multicast HASH table */ 986 e_dbg("Zeroing the MTA\n"); 987 for (i = 0; i < mac->mta_reg_count; i++) 988 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 989 990 /* Setup link and flow control */ 991 ret_val = e1000_setup_link_82571(hw); 992 993 /* Set the transmit descriptor write-back policy */ 994 reg_data = er32(TXDCTL(0)); 995 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 996 E1000_TXDCTL_FULL_TX_DESC_WB | 997 E1000_TXDCTL_COUNT_DESC; 998 ew32(TXDCTL(0), reg_data); 999 1000 /* ...for both queues. */ 1001 switch (mac->type) { 1002 case e1000_82573: 1003 e1000e_enable_tx_pkt_filtering(hw); 1004 /* fall through */ 1005 case e1000_82574: 1006 case e1000_82583: 1007 reg_data = er32(GCR); 1008 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1009 ew32(GCR, reg_data); 1010 break; 1011 default: 1012 reg_data = er32(TXDCTL(1)); 1013 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 1014 E1000_TXDCTL_FULL_TX_DESC_WB | 1015 E1000_TXDCTL_COUNT_DESC; 1016 ew32(TXDCTL(1), reg_data); 1017 break; 1018 } 1019 1020 /* 1021 * Clear all of the statistics registers (clear on read). It is 1022 * important that we do this after we have tried to establish link 1023 * because the symbol error count will increment wildly if there 1024 * is no link. 1025 */ 1026 e1000_clear_hw_cntrs_82571(hw); 1027 1028 return ret_val; 1029} 1030 1031/** 1032 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 1033 * @hw: pointer to the HW structure 1034 * 1035 * Initializes required hardware-dependent bits needed for normal operation. 1036 **/ 1037static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 1038{ 1039 u32 reg; 1040 1041 /* Transmit Descriptor Control 0 */ 1042 reg = er32(TXDCTL(0)); 1043 reg |= (1 << 22); 1044 ew32(TXDCTL(0), reg); 1045 1046 /* Transmit Descriptor Control 1 */ 1047 reg = er32(TXDCTL(1)); 1048 reg |= (1 << 22); 1049 ew32(TXDCTL(1), reg); 1050 1051 /* Transmit Arbitration Control 0 */ 1052 reg = er32(TARC(0)); 1053 reg &= ~(0xF << 27); /* 30:27 */ 1054 switch (hw->mac.type) { 1055 case e1000_82571: 1056 case e1000_82572: 1057 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 1058 break; 1059 default: 1060 break; 1061 } 1062 ew32(TARC(0), reg); 1063 1064 /* Transmit Arbitration Control 1 */ 1065 reg = er32(TARC(1)); 1066 switch (hw->mac.type) { 1067 case e1000_82571: 1068 case e1000_82572: 1069 reg &= ~((1 << 29) | (1 << 30)); 1070 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1071 if (er32(TCTL) & E1000_TCTL_MULR) 1072 reg &= ~(1 << 28); 1073 else 1074 reg |= (1 << 28); 1075 ew32(TARC(1), reg); 1076 break; 1077 default: 1078 break; 1079 } 1080 1081 /* Device Control */ 1082 switch (hw->mac.type) { 1083 case e1000_82573: 1084 case e1000_82574: 1085 case e1000_82583: 1086 reg = er32(CTRL); 1087 reg &= ~(1 << 29); 1088 ew32(CTRL, reg); 1089 break; 1090 default: 1091 break; 1092 } 1093 1094 /* Extended Device Control */ 1095 switch (hw->mac.type) { 1096 case e1000_82573: 1097 case e1000_82574: 1098 case e1000_82583: 1099 reg = er32(CTRL_EXT); 1100 reg &= ~(1 << 23); 1101 reg |= (1 << 22); 1102 ew32(CTRL_EXT, reg); 1103 break; 1104 default: 1105 break; 1106 } 1107 1108 if (hw->mac.type == e1000_82571) { 1109 reg = er32(PBA_ECC); 1110 reg |= E1000_PBA_ECC_CORR_EN; 1111 ew32(PBA_ECC, reg); 1112 } 1113 1114 if ((hw->mac.type == e1000_82571) || 1115 (hw->mac.type == e1000_82572)) { 1116 reg = er32(CTRL_EXT); 1117 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 1118 ew32(CTRL_EXT, reg); 1119 } 1120 1121 1122 /* PCI-Ex Control Registers */ 1123 switch (hw->mac.type) { 1124 case e1000_82574: 1125 case e1000_82583: 1126 reg = er32(GCR); 1127 reg |= (1 << 22); 1128 ew32(GCR, reg); 1129 1130 reg = er32(GCR2); 1131 reg |= 1; 1132 ew32(GCR2, reg); 1133 break; 1134 default: 1135 break; 1136 } 1137} 1138 1139/** 1140 * e1000_clear_vfta_82571 - Clear VLAN filter table 1141 * @hw: pointer to the HW structure 1142 * 1143 * Clears the register array which contains the VLAN filter table by 1144 * setting all the values to 0. 1145 **/ 1146static void e1000_clear_vfta_82571(struct e1000_hw *hw) 1147{ 1148 u32 offset; 1149 u32 vfta_value = 0; 1150 u32 vfta_offset = 0; 1151 u32 vfta_bit_in_reg = 0; 1152 1153 switch (hw->mac.type) { 1154 case e1000_82573: 1155 case e1000_82574: 1156 case e1000_82583: 1157 if (hw->mng_cookie.vlan_id != 0) { 1158 /* 1159 * The VFTA is a 4096b bit-field, each identifying 1160 * a single VLAN ID. The following operations 1161 * determine which 32b entry (i.e. offset) into the 1162 * array we want to set the VLAN ID (i.e. bit) of 1163 * the manageability unit. 1164 */ 1165 vfta_offset = (hw->mng_cookie.vlan_id >> 1166 E1000_VFTA_ENTRY_SHIFT) & 1167 E1000_VFTA_ENTRY_MASK; 1168 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1169 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1170 } 1171 break; 1172 default: 1173 break; 1174 } 1175 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1176 /* 1177 * If the offset we want to clear is the same offset of the 1178 * manageability VLAN ID, then clear all bits except that of 1179 * the manageability unit. 1180 */ 1181 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1182 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1183 e1e_flush(); 1184 } 1185} 1186 1187/** 1188 * e1000_check_mng_mode_82574 - Check manageability is enabled 1189 * @hw: pointer to the HW structure 1190 * 1191 * Reads the NVM Initialization Control Word 2 and returns true 1192 * (>0) if any manageability is enabled, else false (0). 1193 **/ 1194static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) 1195{ 1196 u16 data; 1197 1198 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); 1199 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; 1200} 1201 1202/** 1203 * e1000_led_on_82574 - Turn LED on 1204 * @hw: pointer to the HW structure 1205 * 1206 * Turn LED on. 1207 **/ 1208static s32 e1000_led_on_82574(struct e1000_hw *hw) 1209{ 1210 u32 ctrl; 1211 u32 i; 1212 1213 ctrl = hw->mac.ledctl_mode2; 1214 if (!(E1000_STATUS_LU & er32(STATUS))) { 1215 /* 1216 * If no link, then turn LED on by setting the invert bit 1217 * for each LED that's "on" (0x0E) in ledctl_mode2. 1218 */ 1219 for (i = 0; i < 4; i++) 1220 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1221 E1000_LEDCTL_MODE_LED_ON) 1222 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 1223 } 1224 ew32(LEDCTL, ctrl); 1225 1226 return 0; 1227} 1228 1229/** 1230 * e1000_setup_link_82571 - Setup flow control and link settings 1231 * @hw: pointer to the HW structure 1232 * 1233 * Determines which flow control settings to use, then configures flow 1234 * control. Calls the appropriate media-specific link configuration 1235 * function. Assuming the adapter has a valid link partner, a valid link 1236 * should be established. Assumes the hardware has previously been reset 1237 * and the transmitter and receiver are not enabled. 1238 **/ 1239static s32 e1000_setup_link_82571(struct e1000_hw *hw) 1240{ 1241 /* 1242 * 82573 does not have a word in the NVM to determine 1243 * the default flow control setting, so we explicitly 1244 * set it to full. 1245 */ 1246 switch (hw->mac.type) { 1247 case e1000_82573: 1248 case e1000_82574: 1249 case e1000_82583: 1250 if (hw->fc.requested_mode == e1000_fc_default) 1251 hw->fc.requested_mode = e1000_fc_full; 1252 break; 1253 default: 1254 break; 1255 } 1256 1257 return e1000e_setup_link(hw); 1258} 1259 1260/** 1261 * e1000_setup_copper_link_82571 - Configure copper link settings 1262 * @hw: pointer to the HW structure 1263 * 1264 * Configures the link for auto-neg or forced speed and duplex. Then we check 1265 * for link, once link is established calls to configure collision distance 1266 * and flow control are called. 1267 **/ 1268static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1269{ 1270 u32 ctrl; 1271 s32 ret_val; 1272 1273 ctrl = er32(CTRL); 1274 ctrl |= E1000_CTRL_SLU; 1275 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1276 ew32(CTRL, ctrl); 1277 1278 switch (hw->phy.type) { 1279 case e1000_phy_m88: 1280 case e1000_phy_bm: 1281 ret_val = e1000e_copper_link_setup_m88(hw); 1282 break; 1283 case e1000_phy_igp_2: 1284 ret_val = e1000e_copper_link_setup_igp(hw); 1285 break; 1286 default: 1287 return -E1000_ERR_PHY; 1288 break; 1289 } 1290 1291 if (ret_val) 1292 return ret_val; 1293 1294 ret_val = e1000e_setup_copper_link(hw); 1295 1296 return ret_val; 1297} 1298 1299/** 1300 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1301 * @hw: pointer to the HW structure 1302 * 1303 * Configures collision distance and flow control for fiber and serdes links. 1304 * Upon successful setup, poll for link. 1305 **/ 1306static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1307{ 1308 switch (hw->mac.type) { 1309 case e1000_82571: 1310 case e1000_82572: 1311 /* 1312 * If SerDes loopback mode is entered, there is no form 1313 * of reset to take the adapter out of that mode. So we 1314 * have to explicitly take the adapter out of loopback 1315 * mode. This prevents drivers from twiddling their thumbs 1316 * if another tool failed to take it out of loopback mode. 1317 */ 1318 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1319 break; 1320 default: 1321 break; 1322 } 1323 1324 return e1000e_setup_fiber_serdes_link(hw); 1325} 1326 1327/** 1328 * e1000_check_for_serdes_link_82571 - Check for link (Serdes) 1329 * @hw: pointer to the HW structure 1330 * 1331 * Reports the link state as up or down. 1332 * 1333 * If autonegotiation is supported by the link partner, the link state is 1334 * determined by the result of autonegotiation. This is the most likely case. 1335 * If autonegotiation is not supported by the link partner, and the link 1336 * has a valid signal, force the link up. 1337 * 1338 * The link state is represented internally here by 4 states: 1339 * 1340 * 1) down 1341 * 2) autoneg_progress 1342 * 3) autoneg_complete (the link successfully autonegotiated) 1343 * 4) forced_up (the link has been forced up, it did not autonegotiate) 1344 * 1345 **/ 1346static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 1347{ 1348 struct e1000_mac_info *mac = &hw->mac; 1349 u32 rxcw; 1350 u32 ctrl; 1351 u32 status; 1352 s32 ret_val = 0; 1353 1354 ctrl = er32(CTRL); 1355 status = er32(STATUS); 1356 rxcw = er32(RXCW); 1357 1358 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 1359 1360 /* Receiver is synchronized with no invalid bits. */ 1361 switch (mac->serdes_link_state) { 1362 case e1000_serdes_link_autoneg_complete: 1363 if (!(status & E1000_STATUS_LU)) { 1364 /* 1365 * We have lost link, retry autoneg before 1366 * reporting link failure 1367 */ 1368 mac->serdes_link_state = 1369 e1000_serdes_link_autoneg_progress; 1370 mac->serdes_has_link = false; 1371 e_dbg("AN_UP -> AN_PROG\n"); 1372 } 1373 break; 1374 1375 case e1000_serdes_link_forced_up: 1376 /* 1377 * If we are receiving /C/ ordered sets, re-enable 1378 * auto-negotiation in the TXCW register and disable 1379 * forced link in the Device Control register in an 1380 * attempt to auto-negotiate with our link partner. 1381 */ 1382 if (rxcw & E1000_RXCW_C) { 1383 /* Enable autoneg, and unforce link up */ 1384 ew32(TXCW, mac->txcw); 1385 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 1386 mac->serdes_link_state = 1387 e1000_serdes_link_autoneg_progress; 1388 mac->serdes_has_link = false; 1389 e_dbg("FORCED_UP -> AN_PROG\n"); 1390 } 1391 break; 1392 1393 case e1000_serdes_link_autoneg_progress: 1394 if (rxcw & E1000_RXCW_C) { 1395 /* 1396 * We received /C/ ordered sets, meaning the 1397 * link partner has autonegotiated, and we can 1398 * trust the Link Up (LU) status bit. 1399 */ 1400 if (status & E1000_STATUS_LU) { 1401 mac->serdes_link_state = 1402 e1000_serdes_link_autoneg_complete; 1403 e_dbg("AN_PROG -> AN_UP\n"); 1404 mac->serdes_has_link = true; 1405 } else { 1406 /* Autoneg completed, but failed. */ 1407 mac->serdes_link_state = 1408 e1000_serdes_link_down; 1409 e_dbg("AN_PROG -> DOWN\n"); 1410 } 1411 } else { 1412 /* 1413 * The link partner did not autoneg. 1414 * Force link up and full duplex, and change 1415 * state to forced. 1416 */ 1417 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 1418 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 1419 ew32(CTRL, ctrl); 1420 1421 /* Configure Flow Control after link up. */ 1422 ret_val = e1000e_config_fc_after_link_up(hw); 1423 if (ret_val) { 1424 e_dbg("Error config flow control\n"); 1425 break; 1426 } 1427 mac->serdes_link_state = 1428 e1000_serdes_link_forced_up; 1429 mac->serdes_has_link = true; 1430 e_dbg("AN_PROG -> FORCED_UP\n"); 1431 } 1432 break; 1433 1434 case e1000_serdes_link_down: 1435 default: 1436 /* 1437 * The link was down but the receiver has now gained 1438 * valid sync, so lets see if we can bring the link 1439 * up. 1440 */ 1441 ew32(TXCW, mac->txcw); 1442 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 1443 mac->serdes_link_state = 1444 e1000_serdes_link_autoneg_progress; 1445 e_dbg("DOWN -> AN_PROG\n"); 1446 break; 1447 } 1448 } else { 1449 if (!(rxcw & E1000_RXCW_SYNCH)) { 1450 mac->serdes_has_link = false; 1451 mac->serdes_link_state = e1000_serdes_link_down; 1452 e_dbg("ANYSTATE -> DOWN\n"); 1453 } else { 1454 /* 1455 * We have sync, and can tolerate one invalid (IV) 1456 * codeword before declaring link down, so reread 1457 * to look again. 1458 */ 1459 udelay(10); 1460 rxcw = er32(RXCW); 1461 if (rxcw & E1000_RXCW_IV) { 1462 mac->serdes_link_state = e1000_serdes_link_down; 1463 mac->serdes_has_link = false; 1464 e_dbg("ANYSTATE -> DOWN\n"); 1465 } 1466 } 1467 } 1468 1469 return ret_val; 1470} 1471 1472/** 1473 * e1000_valid_led_default_82571 - Verify a valid default LED config 1474 * @hw: pointer to the HW structure 1475 * @data: pointer to the NVM (EEPROM) 1476 * 1477 * Read the EEPROM for the current default LED configuration. If the 1478 * LED configuration is not valid, set to a valid LED configuration. 1479 **/ 1480static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1481{ 1482 s32 ret_val; 1483 1484 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1485 if (ret_val) { 1486 e_dbg("NVM Read Error\n"); 1487 return ret_val; 1488 } 1489 1490 switch (hw->mac.type) { 1491 case e1000_82573: 1492 case e1000_82574: 1493 case e1000_82583: 1494 if (*data == ID_LED_RESERVED_F746) 1495 *data = ID_LED_DEFAULT_82573; 1496 break; 1497 default: 1498 if (*data == ID_LED_RESERVED_0000 || 1499 *data == ID_LED_RESERVED_FFFF) 1500 *data = ID_LED_DEFAULT; 1501 break; 1502 } 1503 1504 return 0; 1505} 1506 1507/** 1508 * e1000e_get_laa_state_82571 - Get locally administered address state 1509 * @hw: pointer to the HW structure 1510 * 1511 * Retrieve and return the current locally administered address state. 1512 **/ 1513bool e1000e_get_laa_state_82571(struct e1000_hw *hw) 1514{ 1515 if (hw->mac.type != e1000_82571) 1516 return false; 1517 1518 return hw->dev_spec.e82571.laa_is_present; 1519} 1520 1521/** 1522 * e1000e_set_laa_state_82571 - Set locally administered address state 1523 * @hw: pointer to the HW structure 1524 * @state: enable/disable locally administered address 1525 * 1526 * Enable/Disable the current locally administered address state. 1527 **/ 1528void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) 1529{ 1530 if (hw->mac.type != e1000_82571) 1531 return; 1532 1533 hw->dev_spec.e82571.laa_is_present = state; 1534 1535 if (state) 1536 /* 1537 * Hold a copy of the LAA in RAR[14] This is done so that 1538 * between the time RAR[0] gets clobbered and the time it 1539 * gets fixed, the actual LAA is in one of the RARs and no 1540 * incoming packets directed to this port are dropped. 1541 * Eventually the LAA will be in RAR[0] and RAR[14]. 1542 */ 1543 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); 1544} 1545 1546/** 1547 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1548 * @hw: pointer to the HW structure 1549 * 1550 * Verifies that the EEPROM has completed the update. After updating the 1551 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1552 * the checksum fix is not implemented, we need to set the bit and update 1553 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1554 * we need to return bad checksum. 1555 **/ 1556static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1557{ 1558 struct e1000_nvm_info *nvm = &hw->nvm; 1559 s32 ret_val; 1560 u16 data; 1561 1562 if (nvm->type != e1000_nvm_flash_hw) 1563 return 0; 1564 1565 /* 1566 * Check bit 4 of word 10h. If it is 0, firmware is done updating 1567 * 10h-12h. Checksum may need to be fixed. 1568 */ 1569 ret_val = e1000_read_nvm(hw, 0x10, 1, &data); 1570 if (ret_val) 1571 return ret_val; 1572 1573 if (!(data & 0x10)) { 1574 /* 1575 * Read 0x23 and check bit 15. This bit is a 1 1576 * when the checksum has already been fixed. If 1577 * the checksum is still wrong and this bit is a 1578 * 1, we need to return bad checksum. Otherwise, 1579 * we need to set this bit to a 1 and update the 1580 * checksum. 1581 */ 1582 ret_val = e1000_read_nvm(hw, 0x23, 1, &data); 1583 if (ret_val) 1584 return ret_val; 1585 1586 if (!(data & 0x8000)) { 1587 data |= 0x8000; 1588 ret_val = e1000_write_nvm(hw, 0x23, 1, &data); 1589 if (ret_val) 1590 return ret_val; 1591 ret_val = e1000e_update_nvm_checksum(hw); 1592 } 1593 } 1594 1595 return 0; 1596} 1597 1598/** 1599 * e1000_read_mac_addr_82571 - Read device MAC address 1600 * @hw: pointer to the HW structure 1601 **/ 1602static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1603{ 1604 s32 ret_val = 0; 1605 1606 if (hw->mac.type == e1000_82571) { 1607 /* 1608 * If there's an alternate MAC address place it in RAR0 1609 * so that it will override the Si installed default perm 1610 * address. 1611 */ 1612 ret_val = e1000_check_alt_mac_addr_generic(hw); 1613 if (ret_val) 1614 goto out; 1615 } 1616 1617 ret_val = e1000_read_mac_addr_generic(hw); 1618 1619out: 1620 return ret_val; 1621} 1622 1623/** 1624 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down 1625 * @hw: pointer to the HW structure 1626 * 1627 * In the case of a PHY power down to save power, or to turn off link during a 1628 * driver unload, or wake on lan is not enabled, remove the link. 1629 **/ 1630static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) 1631{ 1632 struct e1000_phy_info *phy = &hw->phy; 1633 struct e1000_mac_info *mac = &hw->mac; 1634 1635 if (!(phy->ops.check_reset_block)) 1636 return; 1637 1638 /* If the management interface is not enabled, then power down */ 1639 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 1640 e1000_power_down_phy_copper(hw); 1641} 1642 1643/** 1644 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1645 * @hw: pointer to the HW structure 1646 * 1647 * Clears the hardware counters by reading the counter registers. 1648 **/ 1649static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1650{ 1651 e1000e_clear_hw_cntrs_base(hw); 1652 1653 er32(PRC64); 1654 er32(PRC127); 1655 er32(PRC255); 1656 er32(PRC511); 1657 er32(PRC1023); 1658 er32(PRC1522); 1659 er32(PTC64); 1660 er32(PTC127); 1661 er32(PTC255); 1662 er32(PTC511); 1663 er32(PTC1023); 1664 er32(PTC1522); 1665 1666 er32(ALGNERRC); 1667 er32(RXERRC); 1668 er32(TNCRS); 1669 er32(CEXTERR); 1670 er32(TSCTC); 1671 er32(TSCTFC); 1672 1673 er32(MGTPRC); 1674 er32(MGTPDC); 1675 er32(MGTPTC); 1676 1677 er32(IAC); 1678 er32(ICRXOC); 1679 1680 er32(ICRXPTC); 1681 er32(ICRXATC); 1682 er32(ICTXPTC); 1683 er32(ICTXATC); 1684 er32(ICTXQEC); 1685 er32(ICTXQMTC); 1686 er32(ICRXDMTC); 1687} 1688 1689static struct e1000_mac_operations e82571_mac_ops = { 1690 /* .check_mng_mode: mac type dependent */ 1691 /* .check_for_link: media type dependent */ 1692 .id_led_init = e1000e_id_led_init, 1693 .cleanup_led = e1000e_cleanup_led_generic, 1694 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, 1695 .get_bus_info = e1000e_get_bus_info_pcie, 1696 .set_lan_id = e1000_set_lan_id_multi_port_pcie, 1697 /* .get_link_up_info: media type dependent */ 1698 /* .led_on: mac type dependent */ 1699 .led_off = e1000e_led_off_generic, 1700 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 1701 .write_vfta = e1000_write_vfta_generic, 1702 .clear_vfta = e1000_clear_vfta_82571, 1703 .reset_hw = e1000_reset_hw_82571, 1704 .init_hw = e1000_init_hw_82571, 1705 .setup_link = e1000_setup_link_82571, 1706 /* .setup_physical_interface: media type dependent */ 1707 .setup_led = e1000e_setup_led_generic, 1708 .read_mac_addr = e1000_read_mac_addr_82571, 1709}; 1710 1711static struct e1000_phy_operations e82_phy_ops_igp = { 1712 .acquire = e1000_get_hw_semaphore_82571, 1713 .check_polarity = e1000_check_polarity_igp, 1714 .check_reset_block = e1000e_check_reset_block_generic, 1715 .commit = NULL, 1716 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, 1717 .get_cfg_done = e1000_get_cfg_done_82571, 1718 .get_cable_length = e1000e_get_cable_length_igp_2, 1719 .get_info = e1000e_get_phy_info_igp, 1720 .read_reg = e1000e_read_phy_reg_igp, 1721 .release = e1000_put_hw_semaphore_82571, 1722 .reset = e1000e_phy_hw_reset_generic, 1723 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, 1724 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1725 .write_reg = e1000e_write_phy_reg_igp, 1726 .cfg_on_link_up = NULL, 1727}; 1728 1729static struct e1000_phy_operations e82_phy_ops_m88 = { 1730 .acquire = e1000_get_hw_semaphore_82571, 1731 .check_polarity = e1000_check_polarity_m88, 1732 .check_reset_block = e1000e_check_reset_block_generic, 1733 .commit = e1000e_phy_sw_reset, 1734 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, 1735 .get_cfg_done = e1000e_get_cfg_done, 1736 .get_cable_length = e1000e_get_cable_length_m88, 1737 .get_info = e1000e_get_phy_info_m88, 1738 .read_reg = e1000e_read_phy_reg_m88, 1739 .release = e1000_put_hw_semaphore_82571, 1740 .reset = e1000e_phy_hw_reset_generic, 1741 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, 1742 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1743 .write_reg = e1000e_write_phy_reg_m88, 1744 .cfg_on_link_up = NULL, 1745}; 1746 1747static struct e1000_phy_operations e82_phy_ops_bm = { 1748 .acquire = e1000_get_hw_semaphore_82571, 1749 .check_polarity = e1000_check_polarity_m88, 1750 .check_reset_block = e1000e_check_reset_block_generic, 1751 .commit = e1000e_phy_sw_reset, 1752 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, 1753 .get_cfg_done = e1000e_get_cfg_done, 1754 .get_cable_length = e1000e_get_cable_length_m88, 1755 .get_info = e1000e_get_phy_info_m88, 1756 .read_reg = e1000e_read_phy_reg_bm2, 1757 .release = e1000_put_hw_semaphore_82571, 1758 .reset = e1000e_phy_hw_reset_generic, 1759 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, 1760 .set_d3_lplu_state = e1000e_set_d3_lplu_state, 1761 .write_reg = e1000e_write_phy_reg_bm2, 1762 .cfg_on_link_up = NULL, 1763}; 1764 1765static struct e1000_nvm_operations e82571_nvm_ops = { 1766 .acquire = e1000_acquire_nvm_82571, 1767 .read = e1000e_read_nvm_eerd, 1768 .release = e1000_release_nvm_82571, 1769 .update = e1000_update_nvm_checksum_82571, 1770 .valid_led_default = e1000_valid_led_default_82571, 1771 .validate = e1000_validate_nvm_checksum_82571, 1772 .write = e1000_write_nvm_82571, 1773}; 1774 1775struct e1000_info e1000_82571_info = { 1776 .mac = e1000_82571, 1777 .flags = FLAG_HAS_HW_VLAN_FILTER 1778 | FLAG_HAS_JUMBO_FRAMES 1779 | FLAG_HAS_WOL 1780 | FLAG_APME_IN_CTRL3 1781 | FLAG_RX_CSUM_ENABLED 1782 | FLAG_HAS_CTRLEXT_ON_LOAD 1783 | FLAG_HAS_SMART_POWER_DOWN 1784 | FLAG_RESET_OVERWRITES_LAA /* errata */ 1785 | FLAG_TARC_SPEED_MODE_BIT /* errata */ 1786 | FLAG_APME_CHECK_PORT_B, 1787 .flags2 = FLAG2_DISABLE_ASPM_L1, /* errata 13 */ 1788 .pba = 38, 1789 .max_hw_frame_size = DEFAULT_JUMBO, 1790 .get_variants = e1000_get_variants_82571, 1791 .mac_ops = &e82571_mac_ops, 1792 .phy_ops = &e82_phy_ops_igp, 1793 .nvm_ops = &e82571_nvm_ops, 1794}; 1795 1796struct e1000_info e1000_82572_info = { 1797 .mac = e1000_82572, 1798 .flags = FLAG_HAS_HW_VLAN_FILTER 1799 | FLAG_HAS_JUMBO_FRAMES 1800 | FLAG_HAS_WOL 1801 | FLAG_APME_IN_CTRL3 1802 | FLAG_RX_CSUM_ENABLED 1803 | FLAG_HAS_CTRLEXT_ON_LOAD 1804 | FLAG_TARC_SPEED_MODE_BIT, /* errata */ 1805 .flags2 = FLAG2_DISABLE_ASPM_L1, /* errata 13 */ 1806 .pba = 38, 1807 .max_hw_frame_size = DEFAULT_JUMBO, 1808 .get_variants = e1000_get_variants_82571, 1809 .mac_ops = &e82571_mac_ops, 1810 .phy_ops = &e82_phy_ops_igp, 1811 .nvm_ops = &e82571_nvm_ops, 1812}; 1813 1814struct e1000_info e1000_82573_info = { 1815 .mac = e1000_82573, 1816 .flags = FLAG_HAS_HW_VLAN_FILTER 1817 | FLAG_HAS_WOL 1818 | FLAG_APME_IN_CTRL3 1819 | FLAG_RX_CSUM_ENABLED 1820 | FLAG_HAS_SMART_POWER_DOWN 1821 | FLAG_HAS_AMT 1822 | FLAG_HAS_SWSM_ON_LOAD, 1823 .flags2 = FLAG2_DISABLE_ASPM_L1, 1824 .pba = 20, 1825 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, 1826 .get_variants = e1000_get_variants_82571, 1827 .mac_ops = &e82571_mac_ops, 1828 .phy_ops = &e82_phy_ops_m88, 1829 .nvm_ops = &e82571_nvm_ops, 1830}; 1831 1832struct e1000_info e1000_82574_info = { 1833 .mac = e1000_82574, 1834 .flags = FLAG_HAS_HW_VLAN_FILTER 1835 | FLAG_HAS_MSIX 1836 | FLAG_HAS_JUMBO_FRAMES 1837 | FLAG_HAS_WOL 1838 | FLAG_APME_IN_CTRL3 1839 | FLAG_RX_CSUM_ENABLED 1840 | FLAG_HAS_SMART_POWER_DOWN 1841 | FLAG_HAS_AMT 1842 | FLAG_HAS_CTRLEXT_ON_LOAD, 1843 .pba = 36, 1844 .max_hw_frame_size = DEFAULT_JUMBO, 1845 .get_variants = e1000_get_variants_82571, 1846 .mac_ops = &e82571_mac_ops, 1847 .phy_ops = &e82_phy_ops_bm, 1848 .nvm_ops = &e82571_nvm_ops, 1849}; 1850 1851struct e1000_info e1000_82583_info = { 1852 .mac = e1000_82583, 1853 .flags = FLAG_HAS_HW_VLAN_FILTER 1854 | FLAG_HAS_WOL 1855 | FLAG_APME_IN_CTRL3 1856 | FLAG_RX_CSUM_ENABLED 1857 | FLAG_HAS_SMART_POWER_DOWN 1858 | FLAG_HAS_AMT 1859 | FLAG_HAS_CTRLEXT_ON_LOAD, 1860 .pba = 36, 1861 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, 1862 .get_variants = e1000_get_variants_82571, 1863 .mac_ops = &e82571_mac_ops, 1864 .phy_ops = &e82_phy_ops_bm, 1865 .nvm_ops = &e82571_nvm_ops, 1866}; 1867