1/* 2 * Dave DNET Ethernet Controller driver 3 * 4 * Copyright (C) 2008 Dave S.r.l. <www.dave.eu> 5 * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/io.h> 12#include <linux/module.h> 13#include <linux/moduleparam.h> 14#include <linux/kernel.h> 15#include <linux/types.h> 16#include <linux/slab.h> 17#include <linux/delay.h> 18#include <linux/init.h> 19#include <linux/netdevice.h> 20#include <linux/etherdevice.h> 21#include <linux/dma-mapping.h> 22#include <linux/platform_device.h> 23#include <linux/phy.h> 24 25#include "dnet.h" 26 27#undef DEBUG 28 29/* function for reading internal MAC register */ 30u16 dnet_readw_mac(struct dnet *bp, u16 reg) 31{ 32 u16 data_read; 33 34 /* issue a read */ 35 dnet_writel(bp, reg, MACREG_ADDR); 36 37 /* since a read/write op to the MAC is very slow, 38 * we must wait before reading the data */ 39 ndelay(500); 40 41 /* read data read from the MAC register */ 42 data_read = dnet_readl(bp, MACREG_DATA); 43 44 /* all done */ 45 return data_read; 46} 47 48/* function for writing internal MAC register */ 49void dnet_writew_mac(struct dnet *bp, u16 reg, u16 val) 50{ 51 /* load data to write */ 52 dnet_writel(bp, val, MACREG_DATA); 53 54 /* issue a write */ 55 dnet_writel(bp, reg | DNET_INTERNAL_WRITE, MACREG_ADDR); 56 57 /* since a read/write op to the MAC is very slow, 58 * we must wait before exiting */ 59 ndelay(500); 60} 61 62static void __dnet_set_hwaddr(struct dnet *bp) 63{ 64 u16 tmp; 65 66 tmp = cpu_to_be16(*((u16 *) bp->dev->dev_addr)); 67 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG, tmp); 68 tmp = cpu_to_be16(*((u16 *) (bp->dev->dev_addr + 2))); 69 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG, tmp); 70 tmp = cpu_to_be16(*((u16 *) (bp->dev->dev_addr + 4))); 71 dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG, tmp); 72} 73 74static void __devinit dnet_get_hwaddr(struct dnet *bp) 75{ 76 u16 tmp; 77 u8 addr[6]; 78 79 /* 80 * from MAC docs: 81 * "Note that the MAC address is stored in the registers in Hexadecimal 82 * form. For example, to set the MAC Address to: AC-DE-48-00-00-80 83 * would require writing 0xAC (octet 0) to address 0x0B (high byte of 84 * Mac_addr[15:0]), 0xDE (octet 1) to address 0x0A (Low byte of 85 * Mac_addr[15:0]), 0x48 (octet 2) to address 0x0D (high byte of 86 * Mac_addr[15:0]), 0x00 (octet 3) to address 0x0C (Low byte of 87 * Mac_addr[15:0]), 0x00 (octet 4) to address 0x0F (high byte of 88 * Mac_addr[15:0]), and 0x80 (octet 5) to address * 0x0E (Low byte of 89 * Mac_addr[15:0]). 90 */ 91 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG); 92 *((u16 *) addr) = be16_to_cpu(tmp); 93 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG); 94 *((u16 *) (addr + 2)) = be16_to_cpu(tmp); 95 tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG); 96 *((u16 *) (addr + 4)) = be16_to_cpu(tmp); 97 98 if (is_valid_ether_addr(addr)) 99 memcpy(bp->dev->dev_addr, addr, sizeof(addr)); 100} 101 102static int dnet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 103{ 104 struct dnet *bp = bus->priv; 105 u16 value; 106 107 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) 108 & DNET_INTERNAL_GMII_MNG_CMD_FIN)) 109 cpu_relax(); 110 111 /* only 5 bits allowed for phy-addr and reg_offset */ 112 mii_id &= 0x1f; 113 regnum &= 0x1f; 114 115 /* prepare reg_value for a read */ 116 value = (mii_id << 8); 117 value |= regnum; 118 119 /* write control word */ 120 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, value); 121 122 /* wait for end of transfer */ 123 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) 124 & DNET_INTERNAL_GMII_MNG_CMD_FIN)) 125 cpu_relax(); 126 127 value = dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG); 128 129 pr_debug("mdio_read %02x:%02x <- %04x\n", mii_id, regnum, value); 130 131 return value; 132} 133 134static int dnet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 135 u16 value) 136{ 137 struct dnet *bp = bus->priv; 138 u16 tmp; 139 140 pr_debug("mdio_write %02x:%02x <- %04x\n", mii_id, regnum, value); 141 142 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) 143 & DNET_INTERNAL_GMII_MNG_CMD_FIN)) 144 cpu_relax(); 145 146 /* prepare for a write operation */ 147 tmp = (1 << 13); 148 149 /* only 5 bits allowed for phy-addr and reg_offset */ 150 mii_id &= 0x1f; 151 regnum &= 0x1f; 152 153 /* only 16 bits on data */ 154 value &= 0xffff; 155 156 /* prepare reg_value for a write */ 157 tmp |= (mii_id << 8); 158 tmp |= regnum; 159 160 /* write data to write first */ 161 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG, value); 162 163 /* write control word */ 164 dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp); 165 166 while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) 167 & DNET_INTERNAL_GMII_MNG_CMD_FIN)) 168 cpu_relax(); 169 170 return 0; 171} 172 173static int dnet_mdio_reset(struct mii_bus *bus) 174{ 175 return 0; 176} 177 178static void dnet_handle_link_change(struct net_device *dev) 179{ 180 struct dnet *bp = netdev_priv(dev); 181 struct phy_device *phydev = bp->phy_dev; 182 unsigned long flags; 183 u32 mode_reg, ctl_reg; 184 185 int status_change = 0; 186 187 spin_lock_irqsave(&bp->lock, flags); 188 189 mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG); 190 ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG); 191 192 if (phydev->link) { 193 if (bp->duplex != phydev->duplex) { 194 if (phydev->duplex) 195 ctl_reg &= 196 ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP); 197 else 198 ctl_reg |= 199 DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP; 200 201 bp->duplex = phydev->duplex; 202 status_change = 1; 203 } 204 205 if (bp->speed != phydev->speed) { 206 status_change = 1; 207 switch (phydev->speed) { 208 case 1000: 209 mode_reg |= DNET_INTERNAL_MODE_GBITEN; 210 break; 211 case 100: 212 case 10: 213 mode_reg &= ~DNET_INTERNAL_MODE_GBITEN; 214 break; 215 default: 216 printk(KERN_WARNING 217 "%s: Ack! Speed (%d) is not " 218 "10/100/1000!\n", dev->name, 219 phydev->speed); 220 break; 221 } 222 bp->speed = phydev->speed; 223 } 224 } 225 226 if (phydev->link != bp->link) { 227 if (phydev->link) { 228 mode_reg |= 229 (DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN); 230 } else { 231 mode_reg &= 232 ~(DNET_INTERNAL_MODE_RXEN | 233 DNET_INTERNAL_MODE_TXEN); 234 bp->speed = 0; 235 bp->duplex = -1; 236 } 237 bp->link = phydev->link; 238 239 status_change = 1; 240 } 241 242 if (status_change) { 243 dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg); 244 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg); 245 } 246 247 spin_unlock_irqrestore(&bp->lock, flags); 248 249 if (status_change) { 250 if (phydev->link) 251 printk(KERN_INFO "%s: link up (%d/%s)\n", 252 dev->name, phydev->speed, 253 DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); 254 else 255 printk(KERN_INFO "%s: link down\n", dev->name); 256 } 257} 258 259static int dnet_mii_probe(struct net_device *dev) 260{ 261 struct dnet *bp = netdev_priv(dev); 262 struct phy_device *phydev = NULL; 263 int phy_addr; 264 265 /* find the first phy */ 266 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { 267 if (bp->mii_bus->phy_map[phy_addr]) { 268 phydev = bp->mii_bus->phy_map[phy_addr]; 269 break; 270 } 271 } 272 273 if (!phydev) { 274 printk(KERN_ERR "%s: no PHY found\n", dev->name); 275 return -ENODEV; 276 } 277 278 /* TODO : add pin_irq */ 279 280 /* attach the mac to the phy */ 281 if (bp->capabilities & DNET_HAS_RMII) { 282 phydev = phy_connect(dev, dev_name(&phydev->dev), 283 &dnet_handle_link_change, 0, 284 PHY_INTERFACE_MODE_RMII); 285 } else { 286 phydev = phy_connect(dev, dev_name(&phydev->dev), 287 &dnet_handle_link_change, 0, 288 PHY_INTERFACE_MODE_MII); 289 } 290 291 if (IS_ERR(phydev)) { 292 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); 293 return PTR_ERR(phydev); 294 } 295 296 /* mask with MAC supported features */ 297 if (bp->capabilities & DNET_HAS_GIGABIT) 298 phydev->supported &= PHY_GBIT_FEATURES; 299 else 300 phydev->supported &= PHY_BASIC_FEATURES; 301 302 phydev->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause; 303 304 phydev->advertising = phydev->supported; 305 306 bp->link = 0; 307 bp->speed = 0; 308 bp->duplex = -1; 309 bp->phy_dev = phydev; 310 311 return 0; 312} 313 314static int dnet_mii_init(struct dnet *bp) 315{ 316 int err, i; 317 318 bp->mii_bus = mdiobus_alloc(); 319 if (bp->mii_bus == NULL) 320 return -ENOMEM; 321 322 bp->mii_bus->name = "dnet_mii_bus"; 323 bp->mii_bus->read = &dnet_mdio_read; 324 bp->mii_bus->write = &dnet_mdio_write; 325 bp->mii_bus->reset = &dnet_mdio_reset; 326 327 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); 328 329 bp->mii_bus->priv = bp; 330 331 bp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 332 if (!bp->mii_bus->irq) { 333 err = -ENOMEM; 334 goto err_out; 335 } 336 337 for (i = 0; i < PHY_MAX_ADDR; i++) 338 bp->mii_bus->irq[i] = PHY_POLL; 339 340 platform_set_drvdata(bp->dev, bp->mii_bus); 341 342 if (mdiobus_register(bp->mii_bus)) { 343 err = -ENXIO; 344 goto err_out_free_mdio_irq; 345 } 346 347 if (dnet_mii_probe(bp->dev) != 0) { 348 err = -ENXIO; 349 goto err_out_unregister_bus; 350 } 351 352 return 0; 353 354err_out_unregister_bus: 355 mdiobus_unregister(bp->mii_bus); 356err_out_free_mdio_irq: 357 kfree(bp->mii_bus->irq); 358err_out: 359 mdiobus_free(bp->mii_bus); 360 return err; 361} 362 363/* For Neptune board: LINK1000 as Link LED and TX as activity LED */ 364int dnet_phy_marvell_fixup(struct phy_device *phydev) 365{ 366 return phy_write(phydev, 0x18, 0x4148); 367} 368 369static void dnet_update_stats(struct dnet *bp) 370{ 371 u32 __iomem *reg = bp->regs + DNET_RX_PKT_IGNR_CNT; 372 u32 *p = &bp->hw_stats.rx_pkt_ignr; 373 u32 *end = &bp->hw_stats.rx_byte + 1; 374 375 WARN_ON((unsigned long)(end - p - 1) != 376 (DNET_RX_BYTE_CNT - DNET_RX_PKT_IGNR_CNT) / 4); 377 378 for (; p < end; p++, reg++) 379 *p += readl(reg); 380 381 reg = bp->regs + DNET_TX_UNICAST_CNT; 382 p = &bp->hw_stats.tx_unicast; 383 end = &bp->hw_stats.tx_byte + 1; 384 385 WARN_ON((unsigned long)(end - p - 1) != 386 (DNET_TX_BYTE_CNT - DNET_TX_UNICAST_CNT) / 4); 387 388 for (; p < end; p++, reg++) 389 *p += readl(reg); 390} 391 392static int dnet_poll(struct napi_struct *napi, int budget) 393{ 394 struct dnet *bp = container_of(napi, struct dnet, napi); 395 struct net_device *dev = bp->dev; 396 int npackets = 0; 397 unsigned int pkt_len; 398 struct sk_buff *skb; 399 unsigned int *data_ptr; 400 u32 int_enable; 401 u32 cmd_word; 402 int i; 403 404 while (npackets < budget) { 405 /* 406 * break out of while loop if there are no more 407 * packets waiting 408 */ 409 if (!(dnet_readl(bp, RX_FIFO_WCNT) >> 16)) { 410 napi_complete(napi); 411 int_enable = dnet_readl(bp, INTR_ENB); 412 int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF; 413 dnet_writel(bp, int_enable, INTR_ENB); 414 return 0; 415 } 416 417 cmd_word = dnet_readl(bp, RX_LEN_FIFO); 418 pkt_len = cmd_word & 0xFFFF; 419 420 if (cmd_word & 0xDF180000) 421 printk(KERN_ERR "%s packet receive error %x\n", 422 __func__, cmd_word); 423 424 skb = dev_alloc_skb(pkt_len + 5); 425 if (skb != NULL) { 426 /* Align IP on 16 byte boundaries */ 427 skb_reserve(skb, 2); 428 /* 429 * 'skb_put()' points to the start of sk_buff 430 * data area. 431 */ 432 data_ptr = (unsigned int *)skb_put(skb, pkt_len); 433 for (i = 0; i < (pkt_len + 3) >> 2; i++) 434 *data_ptr++ = dnet_readl(bp, RX_DATA_FIFO); 435 skb->protocol = eth_type_trans(skb, dev); 436 netif_receive_skb(skb); 437 npackets++; 438 } else 439 printk(KERN_NOTICE 440 "%s: No memory to allocate a sk_buff of " 441 "size %u.\n", dev->name, pkt_len); 442 } 443 444 budget -= npackets; 445 446 if (npackets < budget) { 447 /* We processed all packets available. Tell NAPI it can 448 * stop polling then re-enable rx interrupts */ 449 napi_complete(napi); 450 int_enable = dnet_readl(bp, INTR_ENB); 451 int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF; 452 dnet_writel(bp, int_enable, INTR_ENB); 453 return 0; 454 } 455 456 /* There are still packets waiting */ 457 return 1; 458} 459 460static irqreturn_t dnet_interrupt(int irq, void *dev_id) 461{ 462 struct net_device *dev = dev_id; 463 struct dnet *bp = netdev_priv(dev); 464 u32 int_src, int_enable, int_current; 465 unsigned long flags; 466 unsigned int handled = 0; 467 468 spin_lock_irqsave(&bp->lock, flags); 469 470 /* read and clear the DNET irq (clear on read) */ 471 int_src = dnet_readl(bp, INTR_SRC); 472 int_enable = dnet_readl(bp, INTR_ENB); 473 int_current = int_src & int_enable; 474 475 /* restart the queue if we had stopped it for TX fifo almost full */ 476 if (int_current & DNET_INTR_SRC_TX_FIFOAE) { 477 int_enable = dnet_readl(bp, INTR_ENB); 478 int_enable &= ~DNET_INTR_ENB_TX_FIFOAE; 479 dnet_writel(bp, int_enable, INTR_ENB); 480 netif_wake_queue(dev); 481 handled = 1; 482 } 483 484 /* RX FIFO error checking */ 485 if (int_current & 486 (DNET_INTR_SRC_RX_CMDFIFOFF | DNET_INTR_SRC_RX_DATAFIFOFF)) { 487 printk(KERN_ERR "%s: RX fifo error %x, irq %x\n", __func__, 488 dnet_readl(bp, RX_STATUS), int_current); 489 /* we can only flush the RX FIFOs */ 490 dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH, SYS_CTL); 491 ndelay(500); 492 dnet_writel(bp, 0, SYS_CTL); 493 handled = 1; 494 } 495 496 /* TX FIFO error checking */ 497 if (int_current & 498 (DNET_INTR_SRC_TX_FIFOFULL | DNET_INTR_SRC_TX_DISCFRM)) { 499 printk(KERN_ERR "%s: TX fifo error %x, irq %x\n", __func__, 500 dnet_readl(bp, TX_STATUS), int_current); 501 /* we can only flush the TX FIFOs */ 502 dnet_writel(bp, DNET_SYS_CTL_TXFIFOFLUSH, SYS_CTL); 503 ndelay(500); 504 dnet_writel(bp, 0, SYS_CTL); 505 handled = 1; 506 } 507 508 if (int_current & DNET_INTR_SRC_RX_CMDFIFOAF) { 509 if (napi_schedule_prep(&bp->napi)) { 510 /* 511 * There's no point taking any more interrupts 512 * until we have processed the buffers 513 */ 514 /* Disable Rx interrupts and schedule NAPI poll */ 515 int_enable = dnet_readl(bp, INTR_ENB); 516 int_enable &= ~DNET_INTR_SRC_RX_CMDFIFOAF; 517 dnet_writel(bp, int_enable, INTR_ENB); 518 __napi_schedule(&bp->napi); 519 } 520 handled = 1; 521 } 522 523 if (!handled) 524 pr_debug("%s: irq %x remains\n", __func__, int_current); 525 526 spin_unlock_irqrestore(&bp->lock, flags); 527 528 return IRQ_RETVAL(handled); 529} 530 531#ifdef DEBUG 532static inline void dnet_print_skb(struct sk_buff *skb) 533{ 534 int k; 535 printk(KERN_DEBUG PFX "data:"); 536 for (k = 0; k < skb->len; k++) 537 printk(" %02x", (unsigned int)skb->data[k]); 538 printk("\n"); 539} 540#else 541#define dnet_print_skb(skb) do {} while (0) 542#endif 543 544static netdev_tx_t dnet_start_xmit(struct sk_buff *skb, struct net_device *dev) 545{ 546 547 struct dnet *bp = netdev_priv(dev); 548 u32 tx_status, irq_enable; 549 unsigned int len, i, tx_cmd, wrsz; 550 unsigned long flags; 551 unsigned int *bufp; 552 553 tx_status = dnet_readl(bp, TX_STATUS); 554 555 pr_debug("start_xmit: len %u head %p data %p\n", 556 skb->len, skb->head, skb->data); 557 dnet_print_skb(skb); 558 559 /* frame size (words) */ 560 len = (skb->len + 3) >> 2; 561 562 spin_lock_irqsave(&bp->lock, flags); 563 564 tx_status = dnet_readl(bp, TX_STATUS); 565 566 bufp = (unsigned int *)(((unsigned long) skb->data) & ~0x3UL); 567 wrsz = (u32) skb->len + 3; 568 wrsz += ((unsigned long) skb->data) & 0x3; 569 wrsz >>= 2; 570 tx_cmd = ((((unsigned long)(skb->data)) & 0x03) << 16) | (u32) skb->len; 571 572 /* check if there is enough room for the current frame */ 573 if (wrsz < (DNET_FIFO_SIZE - dnet_readl(bp, TX_FIFO_WCNT))) { 574 for (i = 0; i < wrsz; i++) 575 dnet_writel(bp, *bufp++, TX_DATA_FIFO); 576 577 /* 578 * inform MAC that a packet's written and ready to be 579 * shipped out 580 */ 581 dnet_writel(bp, tx_cmd, TX_LEN_FIFO); 582 } 583 584 if (dnet_readl(bp, TX_FIFO_WCNT) > DNET_FIFO_TX_DATA_AF_TH) { 585 netif_stop_queue(dev); 586 tx_status = dnet_readl(bp, INTR_SRC); 587 irq_enable = dnet_readl(bp, INTR_ENB); 588 irq_enable |= DNET_INTR_ENB_TX_FIFOAE; 589 dnet_writel(bp, irq_enable, INTR_ENB); 590 } 591 592 /* free the buffer */ 593 dev_kfree_skb(skb); 594 595 spin_unlock_irqrestore(&bp->lock, flags); 596 597 return NETDEV_TX_OK; 598} 599 600static void dnet_reset_hw(struct dnet *bp) 601{ 602 /* put ts_mac in IDLE state i.e. disable rx/tx */ 603 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, DNET_INTERNAL_MODE_FCEN); 604 605 /* 606 * RX FIFO almost full threshold: only cmd FIFO almost full is 607 * implemented for RX side 608 */ 609 dnet_writel(bp, DNET_FIFO_RX_CMD_AF_TH, RX_FIFO_TH); 610 /* 611 * TX FIFO almost empty threshold: only data FIFO almost empty 612 * is implemented for TX side 613 */ 614 dnet_writel(bp, DNET_FIFO_TX_DATA_AE_TH, TX_FIFO_TH); 615 616 /* flush rx/tx fifos */ 617 dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH, 618 SYS_CTL); 619 msleep(1); 620 dnet_writel(bp, 0, SYS_CTL); 621} 622 623static void dnet_init_hw(struct dnet *bp) 624{ 625 u32 config; 626 627 dnet_reset_hw(bp); 628 __dnet_set_hwaddr(bp); 629 630 config = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG); 631 632 if (bp->dev->flags & IFF_PROMISC) 633 /* Copy All Frames */ 634 config |= DNET_INTERNAL_RXTX_CONTROL_ENPROMISC; 635 if (!(bp->dev->flags & IFF_BROADCAST)) 636 /* No BroadCast */ 637 config |= DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST; 638 639 config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE | 640 DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST | 641 DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL | 642 DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS; 643 644 dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, config); 645 646 /* clear irq before enabling them */ 647 config = dnet_readl(bp, INTR_SRC); 648 649 /* enable RX/TX interrupt, recv packet ready interrupt */ 650 dnet_writel(bp, DNET_INTR_ENB_GLOBAL_ENABLE | DNET_INTR_ENB_RX_SUMMARY | 651 DNET_INTR_ENB_TX_SUMMARY | DNET_INTR_ENB_RX_FIFOERR | 652 DNET_INTR_ENB_RX_ERROR | DNET_INTR_ENB_RX_FIFOFULL | 653 DNET_INTR_ENB_TX_FIFOFULL | DNET_INTR_ENB_TX_DISCFRM | 654 DNET_INTR_ENB_RX_PKTRDY, INTR_ENB); 655} 656 657static int dnet_open(struct net_device *dev) 658{ 659 struct dnet *bp = netdev_priv(dev); 660 661 /* if the phy is not yet register, retry later */ 662 if (!bp->phy_dev) 663 return -EAGAIN; 664 665 if (!is_valid_ether_addr(dev->dev_addr)) 666 return -EADDRNOTAVAIL; 667 668 napi_enable(&bp->napi); 669 dnet_init_hw(bp); 670 671 phy_start_aneg(bp->phy_dev); 672 673 /* schedule a link state check */ 674 phy_start(bp->phy_dev); 675 676 netif_start_queue(dev); 677 678 return 0; 679} 680 681static int dnet_close(struct net_device *dev) 682{ 683 struct dnet *bp = netdev_priv(dev); 684 685 netif_stop_queue(dev); 686 napi_disable(&bp->napi); 687 688 if (bp->phy_dev) 689 phy_stop(bp->phy_dev); 690 691 dnet_reset_hw(bp); 692 netif_carrier_off(dev); 693 694 return 0; 695} 696 697static inline void dnet_print_pretty_hwstats(struct dnet_stats *hwstat) 698{ 699 pr_debug("%s\n", __func__); 700 pr_debug("----------------------------- RX statistics " 701 "-------------------------------\n"); 702 pr_debug("RX_PKT_IGNR_CNT %-8x\n", hwstat->rx_pkt_ignr); 703 pr_debug("RX_LEN_CHK_ERR_CNT %-8x\n", hwstat->rx_len_chk_err); 704 pr_debug("RX_LNG_FRM_CNT %-8x\n", hwstat->rx_lng_frm); 705 pr_debug("RX_SHRT_FRM_CNT %-8x\n", hwstat->rx_shrt_frm); 706 pr_debug("RX_IPG_VIOL_CNT %-8x\n", hwstat->rx_ipg_viol); 707 pr_debug("RX_CRC_ERR_CNT %-8x\n", hwstat->rx_crc_err); 708 pr_debug("RX_OK_PKT_CNT %-8x\n", hwstat->rx_ok_pkt); 709 pr_debug("RX_CTL_FRM_CNT %-8x\n", hwstat->rx_ctl_frm); 710 pr_debug("RX_PAUSE_FRM_CNT %-8x\n", hwstat->rx_pause_frm); 711 pr_debug("RX_MULTICAST_CNT %-8x\n", hwstat->rx_multicast); 712 pr_debug("RX_BROADCAST_CNT %-8x\n", hwstat->rx_broadcast); 713 pr_debug("RX_VLAN_TAG_CNT %-8x\n", hwstat->rx_vlan_tag); 714 pr_debug("RX_PRE_SHRINK_CNT %-8x\n", hwstat->rx_pre_shrink); 715 pr_debug("RX_DRIB_NIB_CNT %-8x\n", hwstat->rx_drib_nib); 716 pr_debug("RX_UNSUP_OPCD_CNT %-8x\n", hwstat->rx_unsup_opcd); 717 pr_debug("RX_BYTE_CNT %-8x\n", hwstat->rx_byte); 718 pr_debug("----------------------------- TX statistics " 719 "-------------------------------\n"); 720 pr_debug("TX_UNICAST_CNT %-8x\n", hwstat->tx_unicast); 721 pr_debug("TX_PAUSE_FRM_CNT %-8x\n", hwstat->tx_pause_frm); 722 pr_debug("TX_MULTICAST_CNT %-8x\n", hwstat->tx_multicast); 723 pr_debug("TX_BRDCAST_CNT %-8x\n", hwstat->tx_brdcast); 724 pr_debug("TX_VLAN_TAG_CNT %-8x\n", hwstat->tx_vlan_tag); 725 pr_debug("TX_BAD_FCS_CNT %-8x\n", hwstat->tx_bad_fcs); 726 pr_debug("TX_JUMBO_CNT %-8x\n", hwstat->tx_jumbo); 727 pr_debug("TX_BYTE_CNT %-8x\n", hwstat->tx_byte); 728} 729 730static struct net_device_stats *dnet_get_stats(struct net_device *dev) 731{ 732 733 struct dnet *bp = netdev_priv(dev); 734 struct net_device_stats *nstat = &dev->stats; 735 struct dnet_stats *hwstat = &bp->hw_stats; 736 737 /* read stats from hardware */ 738 dnet_update_stats(bp); 739 740 /* Convert HW stats into netdevice stats */ 741 nstat->rx_errors = (hwstat->rx_len_chk_err + 742 hwstat->rx_lng_frm + hwstat->rx_shrt_frm + 743 /* ignore IGP violation error 744 hwstat->rx_ipg_viol + */ 745 hwstat->rx_crc_err + 746 hwstat->rx_pre_shrink + 747 hwstat->rx_drib_nib + hwstat->rx_unsup_opcd); 748 nstat->tx_errors = hwstat->tx_bad_fcs; 749 nstat->rx_length_errors = (hwstat->rx_len_chk_err + 750 hwstat->rx_lng_frm + 751 hwstat->rx_shrt_frm + hwstat->rx_pre_shrink); 752 nstat->rx_crc_errors = hwstat->rx_crc_err; 753 nstat->rx_frame_errors = hwstat->rx_pre_shrink + hwstat->rx_drib_nib; 754 nstat->rx_packets = hwstat->rx_ok_pkt; 755 nstat->tx_packets = (hwstat->tx_unicast + 756 hwstat->tx_multicast + hwstat->tx_brdcast); 757 nstat->rx_bytes = hwstat->rx_byte; 758 nstat->tx_bytes = hwstat->tx_byte; 759 nstat->multicast = hwstat->rx_multicast; 760 nstat->rx_missed_errors = hwstat->rx_pkt_ignr; 761 762 dnet_print_pretty_hwstats(hwstat); 763 764 return nstat; 765} 766 767static int dnet_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 768{ 769 struct dnet *bp = netdev_priv(dev); 770 struct phy_device *phydev = bp->phy_dev; 771 772 if (!phydev) 773 return -ENODEV; 774 775 return phy_ethtool_gset(phydev, cmd); 776} 777 778static int dnet_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 779{ 780 struct dnet *bp = netdev_priv(dev); 781 struct phy_device *phydev = bp->phy_dev; 782 783 if (!phydev) 784 return -ENODEV; 785 786 return phy_ethtool_sset(phydev, cmd); 787} 788 789static int dnet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 790{ 791 struct dnet *bp = netdev_priv(dev); 792 struct phy_device *phydev = bp->phy_dev; 793 794 if (!netif_running(dev)) 795 return -EINVAL; 796 797 if (!phydev) 798 return -ENODEV; 799 800 return phy_mii_ioctl(phydev, rq, cmd); 801} 802 803static void dnet_get_drvinfo(struct net_device *dev, 804 struct ethtool_drvinfo *info) 805{ 806 strcpy(info->driver, DRV_NAME); 807 strcpy(info->version, DRV_VERSION); 808 strcpy(info->bus_info, "0"); 809} 810 811static const struct ethtool_ops dnet_ethtool_ops = { 812 .get_settings = dnet_get_settings, 813 .set_settings = dnet_set_settings, 814 .get_drvinfo = dnet_get_drvinfo, 815 .get_link = ethtool_op_get_link, 816}; 817 818static const struct net_device_ops dnet_netdev_ops = { 819 .ndo_open = dnet_open, 820 .ndo_stop = dnet_close, 821 .ndo_get_stats = dnet_get_stats, 822 .ndo_start_xmit = dnet_start_xmit, 823 .ndo_do_ioctl = dnet_ioctl, 824 .ndo_set_mac_address = eth_mac_addr, 825 .ndo_validate_addr = eth_validate_addr, 826 .ndo_change_mtu = eth_change_mtu, 827}; 828 829static int __devinit dnet_probe(struct platform_device *pdev) 830{ 831 struct resource *res; 832 struct net_device *dev; 833 struct dnet *bp; 834 struct phy_device *phydev; 835 int err = -ENXIO; 836 unsigned int mem_base, mem_size, irq; 837 838 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 839 if (!res) { 840 dev_err(&pdev->dev, "no mmio resource defined\n"); 841 goto err_out; 842 } 843 mem_base = res->start; 844 mem_size = resource_size(res); 845 irq = platform_get_irq(pdev, 0); 846 847 if (!request_mem_region(mem_base, mem_size, DRV_NAME)) { 848 dev_err(&pdev->dev, "no memory region available\n"); 849 err = -EBUSY; 850 goto err_out; 851 } 852 853 err = -ENOMEM; 854 dev = alloc_etherdev(sizeof(*bp)); 855 if (!dev) { 856 dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n"); 857 goto err_out_release_mem; 858 } 859 860 /* TODO: Actually, we have some interesting features... */ 861 dev->features |= 0; 862 863 bp = netdev_priv(dev); 864 bp->dev = dev; 865 866 SET_NETDEV_DEV(dev, &pdev->dev); 867 868 spin_lock_init(&bp->lock); 869 870 bp->regs = ioremap(mem_base, mem_size); 871 if (!bp->regs) { 872 dev_err(&pdev->dev, "failed to map registers, aborting.\n"); 873 err = -ENOMEM; 874 goto err_out_free_dev; 875 } 876 877 dev->irq = irq; 878 err = request_irq(dev->irq, dnet_interrupt, 0, DRV_NAME, dev); 879 if (err) { 880 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n", 881 irq, err); 882 goto err_out_iounmap; 883 } 884 885 dev->netdev_ops = &dnet_netdev_ops; 886 netif_napi_add(dev, &bp->napi, dnet_poll, 64); 887 dev->ethtool_ops = &dnet_ethtool_ops; 888 889 dev->base_addr = (unsigned long)bp->regs; 890 891 bp->capabilities = dnet_readl(bp, VERCAPS) & DNET_CAPS_MASK; 892 893 dnet_get_hwaddr(bp); 894 895 if (!is_valid_ether_addr(dev->dev_addr)) { 896 /* choose a random ethernet address */ 897 random_ether_addr(dev->dev_addr); 898 __dnet_set_hwaddr(bp); 899 } 900 901 err = register_netdev(dev); 902 if (err) { 903 dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); 904 goto err_out_free_irq; 905 } 906 907 /* register the PHY board fixup (for Marvell 88E1111) */ 908 err = phy_register_fixup_for_uid(0x01410cc0, 0xfffffff0, 909 dnet_phy_marvell_fixup); 910 /* we can live without it, so just issue a warning */ 911 if (err) 912 dev_warn(&pdev->dev, "Cannot register PHY board fixup.\n"); 913 914 err = dnet_mii_init(bp); 915 if (err) 916 goto err_out_unregister_netdev; 917 918 dev_info(&pdev->dev, "Dave DNET at 0x%p (0x%08x) irq %d %pM\n", 919 bp->regs, mem_base, dev->irq, dev->dev_addr); 920 dev_info(&pdev->dev, "has %smdio, %sirq, %sgigabit, %sdma\n", 921 (bp->capabilities & DNET_HAS_MDIO) ? "" : "no ", 922 (bp->capabilities & DNET_HAS_IRQ) ? "" : "no ", 923 (bp->capabilities & DNET_HAS_GIGABIT) ? "" : "no ", 924 (bp->capabilities & DNET_HAS_DMA) ? "" : "no "); 925 phydev = bp->phy_dev; 926 dev_info(&pdev->dev, "attached PHY driver [%s] " 927 "(mii_bus:phy_addr=%s, irq=%d)\n", 928 phydev->drv->name, dev_name(&phydev->dev), phydev->irq); 929 930 return 0; 931 932err_out_unregister_netdev: 933 unregister_netdev(dev); 934err_out_free_irq: 935 free_irq(dev->irq, dev); 936err_out_iounmap: 937 iounmap(bp->regs); 938err_out_free_dev: 939 free_netdev(dev); 940err_out_release_mem: 941 release_mem_region(mem_base, mem_size); 942err_out: 943 return err; 944} 945 946static int __devexit dnet_remove(struct platform_device *pdev) 947{ 948 949 struct net_device *dev; 950 struct dnet *bp; 951 952 dev = platform_get_drvdata(pdev); 953 954 if (dev) { 955 bp = netdev_priv(dev); 956 if (bp->phy_dev) 957 phy_disconnect(bp->phy_dev); 958 mdiobus_unregister(bp->mii_bus); 959 kfree(bp->mii_bus->irq); 960 mdiobus_free(bp->mii_bus); 961 unregister_netdev(dev); 962 free_irq(dev->irq, dev); 963 iounmap(bp->regs); 964 free_netdev(dev); 965 } 966 967 return 0; 968} 969 970static struct platform_driver dnet_driver = { 971 .probe = dnet_probe, 972 .remove = __devexit_p(dnet_remove), 973 .driver = { 974 .name = "dnet", 975 }, 976}; 977 978static int __init dnet_init(void) 979{ 980 return platform_driver_register(&dnet_driver); 981} 982 983static void __exit dnet_exit(void) 984{ 985 platform_driver_unregister(&dnet_driver); 986} 987 988module_init(dnet_init); 989module_exit(dnet_exit); 990 991MODULE_LICENSE("GPL"); 992MODULE_DESCRIPTION("Dave DNET Ethernet driver"); 993MODULE_AUTHOR("Ilya Yanok <yanok@emcraft.com>, " 994 "Matteo Vit <matteo.vit@dave.eu>"); 995