1/* 2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card 3 * and other Tigon based cards. 4 * 5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>. 6 * 7 * Thanks to Alteon and 3Com for providing hardware and documentation 8 * enabling me to write this driver. 9 * 10 * A mailing list for discussing the use of this driver has been 11 * setup, please subscribe to the lists if you have any questions 12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to 13 * see how to subscribe. 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * Additional credits: 21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace 22 * dump support. The trace dump support has not been 23 * integrated yet however. 24 * Troy Benjegerdes: Big Endian (PPC) patches. 25 * Nate Stahl: Better out of memory handling and stats support. 26 * Aman Singla: Nasty race between interrupt handler and tx code dealing 27 * with 'testing the tx_ret_csm and setting tx_full' 28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping 29 * infrastructure and Sparc support 30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the 31 * driver under Linux/Sparc64 32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards 33 * ETHTOOL_GDRVINFO support 34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx 35 * handler and close() cleanup. 36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether 37 * memory mapped IO is enabled to 38 * make the driver work on RS/6000. 39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem 40 * where the driver would disable 41 * bus master mode if it had to disable 42 * write and invalidate. 43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little 44 * endian systems. 45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and 46 * rx producer index when 47 * flushing the Jumbo ring. 48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the 49 * driver init path. 50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes. 51 */ 52 53#include <linux/module.h> 54#include <linux/moduleparam.h> 55#include <linux/types.h> 56#include <linux/errno.h> 57#include <linux/ioport.h> 58#include <linux/pci.h> 59#include <linux/dma-mapping.h> 60#include <linux/kernel.h> 61#include <linux/netdevice.h> 62#include <linux/etherdevice.h> 63#include <linux/skbuff.h> 64#include <linux/init.h> 65#include <linux/delay.h> 66#include <linux/mm.h> 67#include <linux/highmem.h> 68#include <linux/sockios.h> 69#include <linux/firmware.h> 70#include <linux/slab.h> 71 72#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) 73#include <linux/if_vlan.h> 74#endif 75 76#ifdef SIOCETHTOOL 77#include <linux/ethtool.h> 78#endif 79 80#include <net/sock.h> 81#include <net/ip.h> 82 83#include <asm/system.h> 84#include <asm/io.h> 85#include <asm/irq.h> 86#include <asm/byteorder.h> 87#include <asm/uaccess.h> 88 89 90#define DRV_NAME "acenic" 91 92#undef INDEX_DEBUG 93 94#ifdef CONFIG_ACENIC_OMIT_TIGON_I 95#define ACE_IS_TIGON_I(ap) 0 96#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES 97#else 98#define ACE_IS_TIGON_I(ap) (ap->version == 1) 99#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries 100#endif 101 102#ifndef PCI_VENDOR_ID_ALTEON 103#define PCI_VENDOR_ID_ALTEON 0x12ae 104#endif 105#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 106#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001 107#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002 108#endif 109#ifndef PCI_DEVICE_ID_3COM_3C985 110#define PCI_DEVICE_ID_3COM_3C985 0x0001 111#endif 112#ifndef PCI_VENDOR_ID_NETGEAR 113#define PCI_VENDOR_ID_NETGEAR 0x1385 114#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a 115#endif 116#ifndef PCI_DEVICE_ID_NETGEAR_GA620T 117#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a 118#endif 119 120 121/* 122 * Farallon used the DEC vendor ID by mistake and they seem not 123 * to care - stinky! 124 */ 125#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX 126#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a 127#endif 128#ifndef PCI_DEVICE_ID_FARALLON_PN9100T 129#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa 130#endif 131#ifndef PCI_VENDOR_ID_SGI 132#define PCI_VENDOR_ID_SGI 0x10a9 133#endif 134#ifndef PCI_DEVICE_ID_SGI_ACENIC 135#define PCI_DEVICE_ID_SGI_ACENIC 0x0009 136#endif 137 138static DEFINE_PCI_DEVICE_TABLE(acenic_pci_tbl) = { 139 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE, 140 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 141 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER, 142 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 143 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985, 144 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 145 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620, 146 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 147 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T, 148 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 149 /* 150 * Farallon used the DEC vendor ID on their cards incorrectly, 151 * then later Alteon's ID. 152 */ 153 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX, 154 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 155 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T, 156 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 157 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC, 158 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 159 { } 160}; 161MODULE_DEVICE_TABLE(pci, acenic_pci_tbl); 162 163#define ace_sync_irq(irq) synchronize_irq(irq) 164 165#ifndef offset_in_page 166#define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK) 167#endif 168 169#define ACE_MAX_MOD_PARMS 8 170#define BOARD_IDX_STATIC 0 171#define BOARD_IDX_OVERFLOW -1 172 173#if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \ 174 defined(NETIF_F_HW_VLAN_RX) 175#define ACENIC_DO_VLAN 1 176#define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST 177#else 178#define ACENIC_DO_VLAN 0 179#define ACE_RCB_VLAN_FLAG 0 180#endif 181 182#include "acenic.h" 183 184/* 185 * These must be defined before the firmware is included. 186 */ 187#define MAX_TEXT_LEN 96*1024 188#define MAX_RODATA_LEN 8*1024 189#define MAX_DATA_LEN 2*1024 190 191#ifndef tigon2FwReleaseLocal 192#define tigon2FwReleaseLocal 0 193#endif 194 195/* 196 * This driver currently supports Tigon I and Tigon II based cards 197 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear 198 * GA620. The driver should also work on the SGI, DEC and Farallon 199 * versions of the card, however I have not been able to test that 200 * myself. 201 * 202 * This card is really neat, it supports receive hardware checksumming 203 * and jumbo frames (up to 9000 bytes) and does a lot of work in the 204 * firmware. Also the programming interface is quite neat, except for 205 * the parts dealing with the i2c eeprom on the card ;-) 206 * 207 * Using jumbo frames: 208 * 209 * To enable jumbo frames, simply specify an mtu between 1500 and 9000 210 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time 211 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet 212 * interface number and <MTU> being the MTU value. 213 * 214 * Module parameters: 215 * 216 * When compiled as a loadable module, the driver allows for a number 217 * of module parameters to be specified. The driver supports the 218 * following module parameters: 219 * 220 * trace=<val> - Firmware trace level. This requires special traced 221 * firmware to replace the firmware supplied with 222 * the driver - for debugging purposes only. 223 * 224 * link=<val> - Link state. Normally you want to use the default link 225 * parameters set by the driver. This can be used to 226 * override these in case your switch doesn't negotiate 227 * the link properly. Valid values are: 228 * 0x0001 - Force half duplex link. 229 * 0x0002 - Do not negotiate line speed with the other end. 230 * 0x0010 - 10Mbit/sec link. 231 * 0x0020 - 100Mbit/sec link. 232 * 0x0040 - 1000Mbit/sec link. 233 * 0x0100 - Do not negotiate flow control. 234 * 0x0200 - Enable RX flow control Y 235 * 0x0400 - Enable TX flow control Y (Tigon II NICs only). 236 * Default value is 0x0270, ie. enable link+flow 237 * control negotiation. Negotiating the highest 238 * possible link speed with RX flow control enabled. 239 * 240 * When disabling link speed negotiation, only one link 241 * speed is allowed to be specified! 242 * 243 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed 244 * to wait for more packets to arive before 245 * interrupting the host, from the time the first 246 * packet arrives. 247 * 248 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed 249 * to wait for more packets to arive in the transmit ring, 250 * before interrupting the host, after transmitting the 251 * first packet in the ring. 252 * 253 * max_tx_desc=<val> - maximum number of transmit descriptors 254 * (packets) transmitted before interrupting the host. 255 * 256 * max_rx_desc=<val> - maximum number of receive descriptors 257 * (packets) received before interrupting the host. 258 * 259 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th 260 * increments of the NIC's on board memory to be used for 261 * transmit and receive buffers. For the 1MB NIC app. 800KB 262 * is available, on the 1/2MB NIC app. 300KB is available. 263 * 68KB will always be available as a minimum for both 264 * directions. The default value is a 50/50 split. 265 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate 266 * operations, default (1) is to always disable this as 267 * that is what Alteon does on NT. I have not been able 268 * to measure any real performance differences with 269 * this on my systems. Set <val>=0 if you want to 270 * enable these operations. 271 * 272 * If you use more than one NIC, specify the parameters for the 273 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to 274 * run tracing on NIC #2 but not on NIC #1 and #3. 275 * 276 * TODO: 277 * 278 * - Proper multicast support. 279 * - NIC dump support. 280 * - More tuning parameters. 281 * 282 * The mini ring is not used under Linux and I am not sure it makes sense 283 * to actually use it. 284 * 285 * New interrupt handler strategy: 286 * 287 * The old interrupt handler worked using the traditional method of 288 * replacing an skbuff with a new one when a packet arrives. However 289 * the rx rings do not need to contain a static number of buffer 290 * descriptors, thus it makes sense to move the memory allocation out 291 * of the main interrupt handler and do it in a bottom half handler 292 * and only allocate new buffers when the number of buffers in the 293 * ring is below a certain threshold. In order to avoid starving the 294 * NIC under heavy load it is however necessary to force allocation 295 * when hitting a minimum threshold. The strategy for alloction is as 296 * follows: 297 * 298 * RX_LOW_BUF_THRES - allocate buffers in the bottom half 299 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate 300 * the buffers in the interrupt handler 301 * RX_RING_THRES - maximum number of buffers in the rx ring 302 * RX_MINI_THRES - maximum number of buffers in the mini ring 303 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring 304 * 305 * One advantagous side effect of this allocation approach is that the 306 * entire rx processing can be done without holding any spin lock 307 * since the rx rings and registers are totally independent of the tx 308 * ring and its registers. This of course includes the kmalloc's of 309 * new skb's. Thus start_xmit can run in parallel with rx processing 310 * and the memory allocation on SMP systems. 311 * 312 * Note that running the skb reallocation in a bottom half opens up 313 * another can of races which needs to be handled properly. In 314 * particular it can happen that the interrupt handler tries to run 315 * the reallocation while the bottom half is either running on another 316 * CPU or was interrupted on the same CPU. To get around this the 317 * driver uses bitops to prevent the reallocation routines from being 318 * reentered. 319 * 320 * TX handling can also be done without holding any spin lock, wheee 321 * this is fun! since tx_ret_csm is only written to by the interrupt 322 * handler. The case to be aware of is when shutting down the device 323 * and cleaning up where it is necessary to make sure that 324 * start_xmit() is not running while this is happening. Well DaveM 325 * informs me that this case is already protected against ... bye bye 326 * Mr. Spin Lock, it was nice to know you. 327 * 328 * TX interrupts are now partly disabled so the NIC will only generate 329 * TX interrupts for the number of coal ticks, not for the number of 330 * TX packets in the queue. This should reduce the number of TX only, 331 * ie. when no RX processing is done, interrupts seen. 332 */ 333 334/* 335 * Threshold values for RX buffer allocation - the low water marks for 336 * when to start refilling the rings are set to 75% of the ring 337 * sizes. It seems to make sense to refill the rings entirely from the 338 * intrrupt handler once it gets below the panic threshold, that way 339 * we don't risk that the refilling is moved to another CPU when the 340 * one running the interrupt handler just got the slab code hot in its 341 * cache. 342 */ 343#define RX_RING_SIZE 72 344#define RX_MINI_SIZE 64 345#define RX_JUMBO_SIZE 48 346 347#define RX_PANIC_STD_THRES 16 348#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2 349#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4 350#define RX_PANIC_MINI_THRES 12 351#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2 352#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4 353#define RX_PANIC_JUMBO_THRES 6 354#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2 355#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4 356 357 358/* 359 * Size of the mini ring entries, basically these just should be big 360 * enough to take TCP ACKs 361 */ 362#define ACE_MINI_SIZE 100 363 364#define ACE_MINI_BUFSIZE ACE_MINI_SIZE 365#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4) 366#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4) 367 368/* 369 * There seems to be a magic difference in the effect between 995 and 996 370 * but little difference between 900 and 995 ... no idea why. 371 * 372 * There is now a default set of tuning parameters which is set, depending 373 * on whether or not the user enables Jumbo frames. It's assumed that if 374 * Jumbo frames are enabled, the user wants optimal tuning for that case. 375 */ 376#define DEF_TX_COAL 400 /* 996 */ 377#define DEF_TX_MAX_DESC 60 /* was 40 */ 378#define DEF_RX_COAL 120 /* 1000 */ 379#define DEF_RX_MAX_DESC 25 380#define DEF_TX_RATIO 21 /* 24 */ 381 382#define DEF_JUMBO_TX_COAL 20 383#define DEF_JUMBO_TX_MAX_DESC 60 384#define DEF_JUMBO_RX_COAL 30 385#define DEF_JUMBO_RX_MAX_DESC 6 386#define DEF_JUMBO_TX_RATIO 21 387 388#if tigon2FwReleaseLocal < 20001118 389/* 390 * Standard firmware and early modifications duplicate 391 * IRQ load without this flag (coal timer is never reset). 392 * Note that with this flag tx_coal should be less than 393 * time to xmit full tx ring. 394 * 400usec is not so bad for tx ring size of 128. 395 */ 396#define TX_COAL_INTS_ONLY 1 /* worth it */ 397#else 398/* 399 * With modified firmware, this is not necessary, but still useful. 400 */ 401#define TX_COAL_INTS_ONLY 1 402#endif 403 404#define DEF_TRACE 0 405#define DEF_STAT (2 * TICKS_PER_SEC) 406 407 408static int link_state[ACE_MAX_MOD_PARMS]; 409static int trace[ACE_MAX_MOD_PARMS]; 410static int tx_coal_tick[ACE_MAX_MOD_PARMS]; 411static int rx_coal_tick[ACE_MAX_MOD_PARMS]; 412static int max_tx_desc[ACE_MAX_MOD_PARMS]; 413static int max_rx_desc[ACE_MAX_MOD_PARMS]; 414static int tx_ratio[ACE_MAX_MOD_PARMS]; 415static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1}; 416 417MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>"); 418MODULE_LICENSE("GPL"); 419MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver"); 420#ifndef CONFIG_ACENIC_OMIT_TIGON_I 421MODULE_FIRMWARE("acenic/tg1.bin"); 422#endif 423MODULE_FIRMWARE("acenic/tg2.bin"); 424 425module_param_array_named(link, link_state, int, NULL, 0); 426module_param_array(trace, int, NULL, 0); 427module_param_array(tx_coal_tick, int, NULL, 0); 428module_param_array(max_tx_desc, int, NULL, 0); 429module_param_array(rx_coal_tick, int, NULL, 0); 430module_param_array(max_rx_desc, int, NULL, 0); 431module_param_array(tx_ratio, int, NULL, 0); 432MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state"); 433MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level"); 434MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives"); 435MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait"); 436MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives"); 437MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait"); 438MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)"); 439 440 441static const char version[] __devinitconst = 442 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n" 443 " http://home.cern.ch/~jes/gige/acenic.html\n"; 444 445static int ace_get_settings(struct net_device *, struct ethtool_cmd *); 446static int ace_set_settings(struct net_device *, struct ethtool_cmd *); 447static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *); 448 449static const struct ethtool_ops ace_ethtool_ops = { 450 .get_settings = ace_get_settings, 451 .set_settings = ace_set_settings, 452 .get_drvinfo = ace_get_drvinfo, 453}; 454 455static void ace_watchdog(struct net_device *dev); 456 457static const struct net_device_ops ace_netdev_ops = { 458 .ndo_open = ace_open, 459 .ndo_stop = ace_close, 460 .ndo_tx_timeout = ace_watchdog, 461 .ndo_get_stats = ace_get_stats, 462 .ndo_start_xmit = ace_start_xmit, 463 .ndo_set_multicast_list = ace_set_multicast_list, 464 .ndo_validate_addr = eth_validate_addr, 465 .ndo_set_mac_address = ace_set_mac_addr, 466 .ndo_change_mtu = ace_change_mtu, 467#if ACENIC_DO_VLAN 468 .ndo_vlan_rx_register = ace_vlan_rx_register, 469#endif 470}; 471 472static int __devinit acenic_probe_one(struct pci_dev *pdev, 473 const struct pci_device_id *id) 474{ 475 struct net_device *dev; 476 struct ace_private *ap; 477 static int boards_found; 478 479 dev = alloc_etherdev(sizeof(struct ace_private)); 480 if (dev == NULL) { 481 printk(KERN_ERR "acenic: Unable to allocate " 482 "net_device structure!\n"); 483 return -ENOMEM; 484 } 485 486 SET_NETDEV_DEV(dev, &pdev->dev); 487 488 ap = netdev_priv(dev); 489 ap->pdev = pdev; 490 ap->name = pci_name(pdev); 491 492 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; 493#if ACENIC_DO_VLAN 494 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 495#endif 496 497 dev->watchdog_timeo = 5*HZ; 498 499 dev->netdev_ops = &ace_netdev_ops; 500 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops); 501 502 /* we only display this string ONCE */ 503 if (!boards_found) 504 printk(version); 505 506 if (pci_enable_device(pdev)) 507 goto fail_free_netdev; 508 509 /* 510 * Enable master mode before we start playing with the 511 * pci_command word since pci_set_master() will modify 512 * it. 513 */ 514 pci_set_master(pdev); 515 516 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command); 517 518 /* OpenFirmware on Mac's does not set this - DOH.. */ 519 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) { 520 printk(KERN_INFO "%s: Enabling PCI Memory Mapped " 521 "access - was not enabled by BIOS/Firmware\n", 522 ap->name); 523 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY; 524 pci_write_config_word(ap->pdev, PCI_COMMAND, 525 ap->pci_command); 526 wmb(); 527 } 528 529 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency); 530 if (ap->pci_latency <= 0x40) { 531 ap->pci_latency = 0x40; 532 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency); 533 } 534 535 /* 536 * Remap the regs into kernel space - this is abuse of 537 * dev->base_addr since it was means for I/O port 538 * addresses but who gives a damn. 539 */ 540 dev->base_addr = pci_resource_start(pdev, 0); 541 ap->regs = ioremap(dev->base_addr, 0x4000); 542 if (!ap->regs) { 543 printk(KERN_ERR "%s: Unable to map I/O register, " 544 "AceNIC %i will be disabled.\n", 545 ap->name, boards_found); 546 goto fail_free_netdev; 547 } 548 549 switch(pdev->vendor) { 550 case PCI_VENDOR_ID_ALTEON: 551 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) { 552 printk(KERN_INFO "%s: Farallon PN9100-T ", 553 ap->name); 554 } else { 555 printk(KERN_INFO "%s: Alteon AceNIC ", 556 ap->name); 557 } 558 break; 559 case PCI_VENDOR_ID_3COM: 560 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name); 561 break; 562 case PCI_VENDOR_ID_NETGEAR: 563 printk(KERN_INFO "%s: NetGear GA620 ", ap->name); 564 break; 565 case PCI_VENDOR_ID_DEC: 566 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) { 567 printk(KERN_INFO "%s: Farallon PN9000-SX ", 568 ap->name); 569 break; 570 } 571 case PCI_VENDOR_ID_SGI: 572 printk(KERN_INFO "%s: SGI AceNIC ", ap->name); 573 break; 574 default: 575 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name); 576 break; 577 } 578 579 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr); 580 printk("irq %d\n", pdev->irq); 581 582#ifdef CONFIG_ACENIC_OMIT_TIGON_I 583 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) { 584 printk(KERN_ERR "%s: Driver compiled without Tigon I" 585 " support - NIC disabled\n", dev->name); 586 goto fail_uninit; 587 } 588#endif 589 590 if (ace_allocate_descriptors(dev)) 591 goto fail_free_netdev; 592 593#ifdef MODULE 594 if (boards_found >= ACE_MAX_MOD_PARMS) 595 ap->board_idx = BOARD_IDX_OVERFLOW; 596 else 597 ap->board_idx = boards_found; 598#else 599 ap->board_idx = BOARD_IDX_STATIC; 600#endif 601 602 if (ace_init(dev)) 603 goto fail_free_netdev; 604 605 if (register_netdev(dev)) { 606 printk(KERN_ERR "acenic: device registration failed\n"); 607 goto fail_uninit; 608 } 609 ap->name = dev->name; 610 611 if (ap->pci_using_dac) 612 dev->features |= NETIF_F_HIGHDMA; 613 614 pci_set_drvdata(pdev, dev); 615 616 boards_found++; 617 return 0; 618 619 fail_uninit: 620 ace_init_cleanup(dev); 621 fail_free_netdev: 622 free_netdev(dev); 623 return -ENODEV; 624} 625 626static void __devexit acenic_remove_one(struct pci_dev *pdev) 627{ 628 struct net_device *dev = pci_get_drvdata(pdev); 629 struct ace_private *ap = netdev_priv(dev); 630 struct ace_regs __iomem *regs = ap->regs; 631 short i; 632 633 unregister_netdev(dev); 634 635 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl); 636 if (ap->version >= 2) 637 writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl); 638 639 /* 640 * This clears any pending interrupts 641 */ 642 writel(1, ®s->Mb0Lo); 643 readl(®s->CpuCtrl); /* flush */ 644 645 /* 646 * Make sure no other CPUs are processing interrupts 647 * on the card before the buffers are being released. 648 * Otherwise one might experience some `interesting' 649 * effects. 650 * 651 * Then release the RX buffers - jumbo buffers were 652 * already released in ace_close(). 653 */ 654 ace_sync_irq(dev->irq); 655 656 for (i = 0; i < RX_STD_RING_ENTRIES; i++) { 657 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb; 658 659 if (skb) { 660 struct ring_info *ringp; 661 dma_addr_t mapping; 662 663 ringp = &ap->skb->rx_std_skbuff[i]; 664 mapping = dma_unmap_addr(ringp, mapping); 665 pci_unmap_page(ap->pdev, mapping, 666 ACE_STD_BUFSIZE, 667 PCI_DMA_FROMDEVICE); 668 669 ap->rx_std_ring[i].size = 0; 670 ap->skb->rx_std_skbuff[i].skb = NULL; 671 dev_kfree_skb(skb); 672 } 673 } 674 675 if (ap->version >= 2) { 676 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) { 677 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb; 678 679 if (skb) { 680 struct ring_info *ringp; 681 dma_addr_t mapping; 682 683 ringp = &ap->skb->rx_mini_skbuff[i]; 684 mapping = dma_unmap_addr(ringp,mapping); 685 pci_unmap_page(ap->pdev, mapping, 686 ACE_MINI_BUFSIZE, 687 PCI_DMA_FROMDEVICE); 688 689 ap->rx_mini_ring[i].size = 0; 690 ap->skb->rx_mini_skbuff[i].skb = NULL; 691 dev_kfree_skb(skb); 692 } 693 } 694 } 695 696 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) { 697 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb; 698 if (skb) { 699 struct ring_info *ringp; 700 dma_addr_t mapping; 701 702 ringp = &ap->skb->rx_jumbo_skbuff[i]; 703 mapping = dma_unmap_addr(ringp, mapping); 704 pci_unmap_page(ap->pdev, mapping, 705 ACE_JUMBO_BUFSIZE, 706 PCI_DMA_FROMDEVICE); 707 708 ap->rx_jumbo_ring[i].size = 0; 709 ap->skb->rx_jumbo_skbuff[i].skb = NULL; 710 dev_kfree_skb(skb); 711 } 712 } 713 714 ace_init_cleanup(dev); 715 free_netdev(dev); 716} 717 718static struct pci_driver acenic_pci_driver = { 719 .name = "acenic", 720 .id_table = acenic_pci_tbl, 721 .probe = acenic_probe_one, 722 .remove = __devexit_p(acenic_remove_one), 723}; 724 725static int __init acenic_init(void) 726{ 727 return pci_register_driver(&acenic_pci_driver); 728} 729 730static void __exit acenic_exit(void) 731{ 732 pci_unregister_driver(&acenic_pci_driver); 733} 734 735module_init(acenic_init); 736module_exit(acenic_exit); 737 738static void ace_free_descriptors(struct net_device *dev) 739{ 740 struct ace_private *ap = netdev_priv(dev); 741 int size; 742 743 if (ap->rx_std_ring != NULL) { 744 size = (sizeof(struct rx_desc) * 745 (RX_STD_RING_ENTRIES + 746 RX_JUMBO_RING_ENTRIES + 747 RX_MINI_RING_ENTRIES + 748 RX_RETURN_RING_ENTRIES)); 749 pci_free_consistent(ap->pdev, size, ap->rx_std_ring, 750 ap->rx_ring_base_dma); 751 ap->rx_std_ring = NULL; 752 ap->rx_jumbo_ring = NULL; 753 ap->rx_mini_ring = NULL; 754 ap->rx_return_ring = NULL; 755 } 756 if (ap->evt_ring != NULL) { 757 size = (sizeof(struct event) * EVT_RING_ENTRIES); 758 pci_free_consistent(ap->pdev, size, ap->evt_ring, 759 ap->evt_ring_dma); 760 ap->evt_ring = NULL; 761 } 762 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) { 763 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES); 764 pci_free_consistent(ap->pdev, size, ap->tx_ring, 765 ap->tx_ring_dma); 766 } 767 ap->tx_ring = NULL; 768 769 if (ap->evt_prd != NULL) { 770 pci_free_consistent(ap->pdev, sizeof(u32), 771 (void *)ap->evt_prd, ap->evt_prd_dma); 772 ap->evt_prd = NULL; 773 } 774 if (ap->rx_ret_prd != NULL) { 775 pci_free_consistent(ap->pdev, sizeof(u32), 776 (void *)ap->rx_ret_prd, 777 ap->rx_ret_prd_dma); 778 ap->rx_ret_prd = NULL; 779 } 780 if (ap->tx_csm != NULL) { 781 pci_free_consistent(ap->pdev, sizeof(u32), 782 (void *)ap->tx_csm, ap->tx_csm_dma); 783 ap->tx_csm = NULL; 784 } 785} 786 787 788static int ace_allocate_descriptors(struct net_device *dev) 789{ 790 struct ace_private *ap = netdev_priv(dev); 791 int size; 792 793 size = (sizeof(struct rx_desc) * 794 (RX_STD_RING_ENTRIES + 795 RX_JUMBO_RING_ENTRIES + 796 RX_MINI_RING_ENTRIES + 797 RX_RETURN_RING_ENTRIES)); 798 799 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size, 800 &ap->rx_ring_base_dma); 801 if (ap->rx_std_ring == NULL) 802 goto fail; 803 804 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES; 805 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES; 806 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES; 807 808 size = (sizeof(struct event) * EVT_RING_ENTRIES); 809 810 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma); 811 812 if (ap->evt_ring == NULL) 813 goto fail; 814 815 /* 816 * Only allocate a host TX ring for the Tigon II, the Tigon I 817 * has to use PCI registers for this ;-( 818 */ 819 if (!ACE_IS_TIGON_I(ap)) { 820 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES); 821 822 ap->tx_ring = pci_alloc_consistent(ap->pdev, size, 823 &ap->tx_ring_dma); 824 825 if (ap->tx_ring == NULL) 826 goto fail; 827 } 828 829 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32), 830 &ap->evt_prd_dma); 831 if (ap->evt_prd == NULL) 832 goto fail; 833 834 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32), 835 &ap->rx_ret_prd_dma); 836 if (ap->rx_ret_prd == NULL) 837 goto fail; 838 839 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32), 840 &ap->tx_csm_dma); 841 if (ap->tx_csm == NULL) 842 goto fail; 843 844 return 0; 845 846fail: 847 /* Clean up. */ 848 ace_init_cleanup(dev); 849 return 1; 850} 851 852 853/* 854 * Generic cleanup handling data allocated during init. Used when the 855 * module is unloaded or if an error occurs during initialization 856 */ 857static void ace_init_cleanup(struct net_device *dev) 858{ 859 struct ace_private *ap; 860 861 ap = netdev_priv(dev); 862 863 ace_free_descriptors(dev); 864 865 if (ap->info) 866 pci_free_consistent(ap->pdev, sizeof(struct ace_info), 867 ap->info, ap->info_dma); 868 kfree(ap->skb); 869 kfree(ap->trace_buf); 870 871 if (dev->irq) 872 free_irq(dev->irq, dev); 873 874 iounmap(ap->regs); 875} 876 877 878/* 879 * Commands are considered to be slow. 880 */ 881static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd) 882{ 883 u32 idx; 884 885 idx = readl(®s->CmdPrd); 886 887 writel(*(u32 *)(cmd), ®s->CmdRng[idx]); 888 idx = (idx + 1) % CMD_RING_ENTRIES; 889 890 writel(idx, ®s->CmdPrd); 891} 892 893 894static int __devinit ace_init(struct net_device *dev) 895{ 896 struct ace_private *ap; 897 struct ace_regs __iomem *regs; 898 struct ace_info *info = NULL; 899 struct pci_dev *pdev; 900 unsigned long myjif; 901 u64 tmp_ptr; 902 u32 tig_ver, mac1, mac2, tmp, pci_state; 903 int board_idx, ecode = 0; 904 short i; 905 unsigned char cache_size; 906 907 ap = netdev_priv(dev); 908 regs = ap->regs; 909 910 board_idx = ap->board_idx; 911 912 /* 913 * aman@sgi.com - its useful to do a NIC reset here to 914 * address the `Firmware not running' problem subsequent 915 * to any crashes involving the NIC 916 */ 917 writel(HW_RESET | (HW_RESET << 24), ®s->HostCtrl); 918 readl(®s->HostCtrl); /* PCI write posting */ 919 udelay(5); 920 921 /* 922 * Don't access any other registers before this point! 923 */ 924#ifdef __BIG_ENDIAN 925 /* 926 * This will most likely need BYTE_SWAP once we switch 927 * to using __raw_writel() 928 */ 929 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)), 930 ®s->HostCtrl); 931#else 932 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)), 933 ®s->HostCtrl); 934#endif 935 readl(®s->HostCtrl); /* PCI write posting */ 936 937 /* 938 * Stop the NIC CPU and clear pending interrupts 939 */ 940 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl); 941 readl(®s->CpuCtrl); /* PCI write posting */ 942 writel(0, ®s->Mb0Lo); 943 944 tig_ver = readl(®s->HostCtrl) >> 28; 945 946 switch(tig_ver){ 947#ifndef CONFIG_ACENIC_OMIT_TIGON_I 948 case 4: 949 case 5: 950 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ", 951 tig_ver, ap->firmware_major, ap->firmware_minor, 952 ap->firmware_fix); 953 writel(0, ®s->LocalCtrl); 954 ap->version = 1; 955 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES; 956 break; 957#endif 958 case 6: 959 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ", 960 tig_ver, ap->firmware_major, ap->firmware_minor, 961 ap->firmware_fix); 962 writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl); 963 readl(®s->CpuBCtrl); /* PCI write posting */ 964 /* 965 * The SRAM bank size does _not_ indicate the amount 966 * of memory on the card, it controls the _bank_ size! 967 * Ie. a 1MB AceNIC will have two banks of 512KB. 968 */ 969 writel(SRAM_BANK_512K, ®s->LocalCtrl); 970 writel(SYNC_SRAM_TIMING, ®s->MiscCfg); 971 ap->version = 2; 972 ap->tx_ring_entries = MAX_TX_RING_ENTRIES; 973 break; 974 default: 975 printk(KERN_WARNING " Unsupported Tigon version detected " 976 "(%i)\n", tig_ver); 977 ecode = -ENODEV; 978 goto init_error; 979 } 980 981 /* 982 * ModeStat _must_ be set after the SRAM settings as this change 983 * seems to corrupt the ModeStat and possible other registers. 984 * The SRAM settings survive resets and setting it to the same 985 * value a second time works as well. This is what caused the 986 * `Firmware not running' problem on the Tigon II. 987 */ 988#ifdef __BIG_ENDIAN 989 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD | 990 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, ®s->ModeStat); 991#else 992 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | 993 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, ®s->ModeStat); 994#endif 995 readl(®s->ModeStat); /* PCI write posting */ 996 997 mac1 = 0; 998 for(i = 0; i < 4; i++) { 999 int t; 1000 1001 mac1 = mac1 << 8; 1002 t = read_eeprom_byte(dev, 0x8c+i); 1003 if (t < 0) { 1004 ecode = -EIO; 1005 goto init_error; 1006 } else 1007 mac1 |= (t & 0xff); 1008 } 1009 mac2 = 0; 1010 for(i = 4; i < 8; i++) { 1011 int t; 1012 1013 mac2 = mac2 << 8; 1014 t = read_eeprom_byte(dev, 0x8c+i); 1015 if (t < 0) { 1016 ecode = -EIO; 1017 goto init_error; 1018 } else 1019 mac2 |= (t & 0xff); 1020 } 1021 1022 writel(mac1, ®s->MacAddrHi); 1023 writel(mac2, ®s->MacAddrLo); 1024 1025 dev->dev_addr[0] = (mac1 >> 8) & 0xff; 1026 dev->dev_addr[1] = mac1 & 0xff; 1027 dev->dev_addr[2] = (mac2 >> 24) & 0xff; 1028 dev->dev_addr[3] = (mac2 >> 16) & 0xff; 1029 dev->dev_addr[4] = (mac2 >> 8) & 0xff; 1030 dev->dev_addr[5] = mac2 & 0xff; 1031 1032 printk("MAC: %pM\n", dev->dev_addr); 1033 1034 /* 1035 * Looks like this is necessary to deal with on all architectures, 1036 * even this %$#%$# N440BX Intel based thing doesn't get it right. 1037 * Ie. having two NICs in the machine, one will have the cache 1038 * line set at boot time, the other will not. 1039 */ 1040 pdev = ap->pdev; 1041 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size); 1042 cache_size <<= 2; 1043 if (cache_size != SMP_CACHE_BYTES) { 1044 printk(KERN_INFO " PCI cache line size set incorrectly " 1045 "(%i bytes) by BIOS/FW, ", cache_size); 1046 if (cache_size > SMP_CACHE_BYTES) 1047 printk("expecting %i\n", SMP_CACHE_BYTES); 1048 else { 1049 printk("correcting to %i\n", SMP_CACHE_BYTES); 1050 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 1051 SMP_CACHE_BYTES >> 2); 1052 } 1053 } 1054 1055 pci_state = readl(®s->PciState); 1056 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, " 1057 "latency: %i clks\n", 1058 (pci_state & PCI_32BIT) ? 32 : 64, 1059 (pci_state & PCI_66MHZ) ? 66 : 33, 1060 ap->pci_latency); 1061 1062 /* 1063 * Set the max DMA transfer size. Seems that for most systems 1064 * the performance is better when no MAX parameter is 1065 * set. However for systems enabling PCI write and invalidate, 1066 * DMA writes must be set to the L1 cache line size to get 1067 * optimal performance. 1068 * 1069 * The default is now to turn the PCI write and invalidate off 1070 * - that is what Alteon does for NT. 1071 */ 1072 tmp = READ_CMD_MEM | WRITE_CMD_MEM; 1073 if (ap->version >= 2) { 1074 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ)); 1075 /* 1076 * Tuning parameters only supported for 8 cards 1077 */ 1078 if (board_idx == BOARD_IDX_OVERFLOW || 1079 dis_pci_mem_inval[board_idx]) { 1080 if (ap->pci_command & PCI_COMMAND_INVALIDATE) { 1081 ap->pci_command &= ~PCI_COMMAND_INVALIDATE; 1082 pci_write_config_word(pdev, PCI_COMMAND, 1083 ap->pci_command); 1084 printk(KERN_INFO " Disabling PCI memory " 1085 "write and invalidate\n"); 1086 } 1087 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) { 1088 printk(KERN_INFO " PCI memory write & invalidate " 1089 "enabled by BIOS, enabling counter measures\n"); 1090 1091 switch(SMP_CACHE_BYTES) { 1092 case 16: 1093 tmp |= DMA_WRITE_MAX_16; 1094 break; 1095 case 32: 1096 tmp |= DMA_WRITE_MAX_32; 1097 break; 1098 case 64: 1099 tmp |= DMA_WRITE_MAX_64; 1100 break; 1101 case 128: 1102 tmp |= DMA_WRITE_MAX_128; 1103 break; 1104 default: 1105 printk(KERN_INFO " Cache line size %i not " 1106 "supported, PCI write and invalidate " 1107 "disabled\n", SMP_CACHE_BYTES); 1108 ap->pci_command &= ~PCI_COMMAND_INVALIDATE; 1109 pci_write_config_word(pdev, PCI_COMMAND, 1110 ap->pci_command); 1111 } 1112 } 1113 } 1114 1115#ifdef __sparc__ 1116 /* 1117 * On this platform, we know what the best dma settings 1118 * are. We use 64-byte maximum bursts, because if we 1119 * burst larger than the cache line size (or even cross 1120 * a 64byte boundary in a single burst) the UltraSparc 1121 * PCI controller will disconnect at 64-byte multiples. 1122 * 1123 * Read-multiple will be properly enabled above, and when 1124 * set will give the PCI controller proper hints about 1125 * prefetching. 1126 */ 1127 tmp &= ~DMA_READ_WRITE_MASK; 1128 tmp |= DMA_READ_MAX_64; 1129 tmp |= DMA_WRITE_MAX_64; 1130#endif 1131#ifdef __alpha__ 1132 tmp &= ~DMA_READ_WRITE_MASK; 1133 tmp |= DMA_READ_MAX_128; 1134 /* 1135 * All the docs say MUST NOT. Well, I did. 1136 * Nothing terrible happens, if we load wrong size. 1137 * Bit w&i still works better! 1138 */ 1139 tmp |= DMA_WRITE_MAX_128; 1140#endif 1141 writel(tmp, ®s->PciState); 1142 1143 1144 /* 1145 * Configure DMA attributes. 1146 */ 1147 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 1148 ap->pci_using_dac = 1; 1149 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 1150 ap->pci_using_dac = 0; 1151 } else { 1152 ecode = -ENODEV; 1153 goto init_error; 1154 } 1155 1156 /* 1157 * Initialize the generic info block and the command+event rings 1158 * and the control blocks for the transmit and receive rings 1159 * as they need to be setup once and for all. 1160 */ 1161 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info), 1162 &ap->info_dma))) { 1163 ecode = -EAGAIN; 1164 goto init_error; 1165 } 1166 ap->info = info; 1167 1168 /* 1169 * Get the memory for the skb rings. 1170 */ 1171 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) { 1172 ecode = -EAGAIN; 1173 goto init_error; 1174 } 1175 1176 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED, 1177 DRV_NAME, dev); 1178 if (ecode) { 1179 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n", 1180 DRV_NAME, pdev->irq); 1181 goto init_error; 1182 } else 1183 dev->irq = pdev->irq; 1184 1185#ifdef INDEX_DEBUG 1186 spin_lock_init(&ap->debug_lock); 1187 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1; 1188 ap->last_std_rx = 0; 1189 ap->last_mini_rx = 0; 1190#endif 1191 1192 memset(ap->info, 0, sizeof(struct ace_info)); 1193 memset(ap->skb, 0, sizeof(struct ace_skb)); 1194 1195 ecode = ace_load_firmware(dev); 1196 if (ecode) 1197 goto init_error; 1198 1199 ap->fw_running = 0; 1200 1201 tmp_ptr = ap->info_dma; 1202 writel(tmp_ptr >> 32, ®s->InfoPtrHi); 1203 writel(tmp_ptr & 0xffffffff, ®s->InfoPtrLo); 1204 1205 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event)); 1206 1207 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma); 1208 info->evt_ctrl.flags = 0; 1209 1210 *(ap->evt_prd) = 0; 1211 wmb(); 1212 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma); 1213 writel(0, ®s->EvtCsm); 1214 1215 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100); 1216 info->cmd_ctrl.flags = 0; 1217 info->cmd_ctrl.max_len = 0; 1218 1219 for (i = 0; i < CMD_RING_ENTRIES; i++) 1220 writel(0, ®s->CmdRng[i]); 1221 1222 writel(0, ®s->CmdPrd); 1223 writel(0, ®s->CmdCsm); 1224 1225 tmp_ptr = ap->info_dma; 1226 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats); 1227 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr); 1228 1229 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma); 1230 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE; 1231 info->rx_std_ctrl.flags = 1232 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG; 1233 1234 memset(ap->rx_std_ring, 0, 1235 RX_STD_RING_ENTRIES * sizeof(struct rx_desc)); 1236 1237 for (i = 0; i < RX_STD_RING_ENTRIES; i++) 1238 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM; 1239 1240 ap->rx_std_skbprd = 0; 1241 atomic_set(&ap->cur_rx_bufs, 0); 1242 1243 set_aceaddr(&info->rx_jumbo_ctrl.rngptr, 1244 (ap->rx_ring_base_dma + 1245 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES))); 1246 info->rx_jumbo_ctrl.max_len = 0; 1247 info->rx_jumbo_ctrl.flags = 1248 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG; 1249 1250 memset(ap->rx_jumbo_ring, 0, 1251 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc)); 1252 1253 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) 1254 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO; 1255 1256 ap->rx_jumbo_skbprd = 0; 1257 atomic_set(&ap->cur_jumbo_bufs, 0); 1258 1259 memset(ap->rx_mini_ring, 0, 1260 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc)); 1261 1262 if (ap->version >= 2) { 1263 set_aceaddr(&info->rx_mini_ctrl.rngptr, 1264 (ap->rx_ring_base_dma + 1265 (sizeof(struct rx_desc) * 1266 (RX_STD_RING_ENTRIES + 1267 RX_JUMBO_RING_ENTRIES)))); 1268 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE; 1269 info->rx_mini_ctrl.flags = 1270 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG; 1271 1272 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) 1273 ap->rx_mini_ring[i].flags = 1274 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI; 1275 } else { 1276 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0); 1277 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE; 1278 info->rx_mini_ctrl.max_len = 0; 1279 } 1280 1281 ap->rx_mini_skbprd = 0; 1282 atomic_set(&ap->cur_mini_bufs, 0); 1283 1284 set_aceaddr(&info->rx_return_ctrl.rngptr, 1285 (ap->rx_ring_base_dma + 1286 (sizeof(struct rx_desc) * 1287 (RX_STD_RING_ENTRIES + 1288 RX_JUMBO_RING_ENTRIES + 1289 RX_MINI_RING_ENTRIES)))); 1290 info->rx_return_ctrl.flags = 0; 1291 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES; 1292 1293 memset(ap->rx_return_ring, 0, 1294 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc)); 1295 1296 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma); 1297 *(ap->rx_ret_prd) = 0; 1298 1299 writel(TX_RING_BASE, ®s->WinBase); 1300 1301 if (ACE_IS_TIGON_I(ap)) { 1302 ap->tx_ring = (__force struct tx_desc *) regs->Window; 1303 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES 1304 * sizeof(struct tx_desc)) / sizeof(u32); i++) 1305 writel(0, (__force void __iomem *)ap->tx_ring + i * 4); 1306 1307 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE); 1308 } else { 1309 memset(ap->tx_ring, 0, 1310 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc)); 1311 1312 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma); 1313 } 1314 1315 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap); 1316 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG; 1317 1318 /* 1319 * The Tigon I does not like having the TX ring in host memory ;-( 1320 */ 1321 if (!ACE_IS_TIGON_I(ap)) 1322 tmp |= RCB_FLG_TX_HOST_RING; 1323#if TX_COAL_INTS_ONLY 1324 tmp |= RCB_FLG_COAL_INT_ONLY; 1325#endif 1326 info->tx_ctrl.flags = tmp; 1327 1328 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma); 1329 1330 /* 1331 * Potential item for tuning parameter 1332 */ 1333 writel(DMA_THRESH_8W, ®s->DmaReadCfg); 1334 writel(DMA_THRESH_8W, ®s->DmaWriteCfg); 1335 1336 writel(0, ®s->MaskInt); 1337 writel(1, ®s->IfIdx); 1338 1339 writel(DEF_STAT, ®s->TuneStatTicks); 1340 writel(DEF_TRACE, ®s->TuneTrace); 1341 1342 ace_set_rxtx_parms(dev, 0); 1343 1344 if (board_idx == BOARD_IDX_OVERFLOW) { 1345 printk(KERN_WARNING "%s: more than %i NICs detected, " 1346 "ignoring module parameters!\n", 1347 ap->name, ACE_MAX_MOD_PARMS); 1348 } else if (board_idx >= 0) { 1349 if (tx_coal_tick[board_idx]) 1350 writel(tx_coal_tick[board_idx], 1351 ®s->TuneTxCoalTicks); 1352 if (max_tx_desc[board_idx]) 1353 writel(max_tx_desc[board_idx], ®s->TuneMaxTxDesc); 1354 1355 if (rx_coal_tick[board_idx]) 1356 writel(rx_coal_tick[board_idx], 1357 ®s->TuneRxCoalTicks); 1358 if (max_rx_desc[board_idx]) 1359 writel(max_rx_desc[board_idx], ®s->TuneMaxRxDesc); 1360 1361 if (trace[board_idx]) 1362 writel(trace[board_idx], ®s->TuneTrace); 1363 1364 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64)) 1365 writel(tx_ratio[board_idx], ®s->TxBufRat); 1366 } 1367 1368 /* 1369 * Default link parameters 1370 */ 1371 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB | 1372 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE; 1373 if(ap->version >= 2) 1374 tmp |= LNK_TX_FLOW_CTL_Y; 1375 1376 /* 1377 * Override link default parameters 1378 */ 1379 if ((board_idx >= 0) && link_state[board_idx]) { 1380 int option = link_state[board_idx]; 1381 1382 tmp = LNK_ENABLE; 1383 1384 if (option & 0x01) { 1385 printk(KERN_INFO "%s: Setting half duplex link\n", 1386 ap->name); 1387 tmp &= ~LNK_FULL_DUPLEX; 1388 } 1389 if (option & 0x02) 1390 tmp &= ~LNK_NEGOTIATE; 1391 if (option & 0x10) 1392 tmp |= LNK_10MB; 1393 if (option & 0x20) 1394 tmp |= LNK_100MB; 1395 if (option & 0x40) 1396 tmp |= LNK_1000MB; 1397 if ((option & 0x70) == 0) { 1398 printk(KERN_WARNING "%s: No media speed specified, " 1399 "forcing auto negotiation\n", ap->name); 1400 tmp |= LNK_NEGOTIATE | LNK_1000MB | 1401 LNK_100MB | LNK_10MB; 1402 } 1403 if ((option & 0x100) == 0) 1404 tmp |= LNK_NEG_FCTL; 1405 else 1406 printk(KERN_INFO "%s: Disabling flow control " 1407 "negotiation\n", ap->name); 1408 if (option & 0x200) 1409 tmp |= LNK_RX_FLOW_CTL_Y; 1410 if ((option & 0x400) && (ap->version >= 2)) { 1411 printk(KERN_INFO "%s: Enabling TX flow control\n", 1412 ap->name); 1413 tmp |= LNK_TX_FLOW_CTL_Y; 1414 } 1415 } 1416 1417 ap->link = tmp; 1418 writel(tmp, ®s->TuneLink); 1419 if (ap->version >= 2) 1420 writel(tmp, ®s->TuneFastLink); 1421 1422 writel(ap->firmware_start, ®s->Pc); 1423 1424 writel(0, ®s->Mb0Lo); 1425 1426 /* 1427 * Set tx_csm before we start receiving interrupts, otherwise 1428 * the interrupt handler might think it is supposed to process 1429 * tx ints before we are up and running, which may cause a null 1430 * pointer access in the int handler. 1431 */ 1432 ap->cur_rx = 0; 1433 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0; 1434 1435 wmb(); 1436 ace_set_txprd(regs, ap, 0); 1437 writel(0, ®s->RxRetCsm); 1438 1439 /* 1440 * Enable DMA engine now. 1441 * If we do this sooner, Mckinley box pukes. 1442 * I assume it's because Tigon II DMA engine wants to check 1443 * *something* even before the CPU is started. 1444 */ 1445 writel(1, ®s->AssistState); /* enable DMA */ 1446 1447 /* 1448 * Start the NIC CPU 1449 */ 1450 writel(readl(®s->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), ®s->CpuCtrl); 1451 readl(®s->CpuCtrl); 1452 1453 /* 1454 * Wait for the firmware to spin up - max 3 seconds. 1455 */ 1456 myjif = jiffies + 3 * HZ; 1457 while (time_before(jiffies, myjif) && !ap->fw_running) 1458 cpu_relax(); 1459 1460 if (!ap->fw_running) { 1461 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name); 1462 1463 ace_dump_trace(ap); 1464 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl); 1465 readl(®s->CpuCtrl); 1466 1467 /* aman@sgi.com - account for badly behaving firmware/NIC: 1468 * - have observed that the NIC may continue to generate 1469 * interrupts for some reason; attempt to stop it - halt 1470 * second CPU for Tigon II cards, and also clear Mb0 1471 * - if we're a module, we'll fail to load if this was 1472 * the only GbE card in the system => if the kernel does 1473 * see an interrupt from the NIC, code to handle it is 1474 * gone and OOps! - so free_irq also 1475 */ 1476 if (ap->version >= 2) 1477 writel(readl(®s->CpuBCtrl) | CPU_HALT, 1478 ®s->CpuBCtrl); 1479 writel(0, ®s->Mb0Lo); 1480 readl(®s->Mb0Lo); 1481 1482 ecode = -EBUSY; 1483 goto init_error; 1484 } 1485 1486 /* 1487 * We load the ring here as there seem to be no way to tell the 1488 * firmware to wipe the ring without re-initializing it. 1489 */ 1490 if (!test_and_set_bit(0, &ap->std_refill_busy)) 1491 ace_load_std_rx_ring(ap, RX_RING_SIZE); 1492 else 1493 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n", 1494 ap->name); 1495 if (ap->version >= 2) { 1496 if (!test_and_set_bit(0, &ap->mini_refill_busy)) 1497 ace_load_mini_rx_ring(ap, RX_MINI_SIZE); 1498 else 1499 printk(KERN_ERR "%s: Someone is busy refilling " 1500 "the RX mini ring\n", ap->name); 1501 } 1502 return 0; 1503 1504 init_error: 1505 ace_init_cleanup(dev); 1506 return ecode; 1507} 1508 1509 1510static void ace_set_rxtx_parms(struct net_device *dev, int jumbo) 1511{ 1512 struct ace_private *ap = netdev_priv(dev); 1513 struct ace_regs __iomem *regs = ap->regs; 1514 int board_idx = ap->board_idx; 1515 1516 if (board_idx >= 0) { 1517 if (!jumbo) { 1518 if (!tx_coal_tick[board_idx]) 1519 writel(DEF_TX_COAL, ®s->TuneTxCoalTicks); 1520 if (!max_tx_desc[board_idx]) 1521 writel(DEF_TX_MAX_DESC, ®s->TuneMaxTxDesc); 1522 if (!rx_coal_tick[board_idx]) 1523 writel(DEF_RX_COAL, ®s->TuneRxCoalTicks); 1524 if (!max_rx_desc[board_idx]) 1525 writel(DEF_RX_MAX_DESC, ®s->TuneMaxRxDesc); 1526 if (!tx_ratio[board_idx]) 1527 writel(DEF_TX_RATIO, ®s->TxBufRat); 1528 } else { 1529 if (!tx_coal_tick[board_idx]) 1530 writel(DEF_JUMBO_TX_COAL, 1531 ®s->TuneTxCoalTicks); 1532 if (!max_tx_desc[board_idx]) 1533 writel(DEF_JUMBO_TX_MAX_DESC, 1534 ®s->TuneMaxTxDesc); 1535 if (!rx_coal_tick[board_idx]) 1536 writel(DEF_JUMBO_RX_COAL, 1537 ®s->TuneRxCoalTicks); 1538 if (!max_rx_desc[board_idx]) 1539 writel(DEF_JUMBO_RX_MAX_DESC, 1540 ®s->TuneMaxRxDesc); 1541 if (!tx_ratio[board_idx]) 1542 writel(DEF_JUMBO_TX_RATIO, ®s->TxBufRat); 1543 } 1544 } 1545} 1546 1547 1548static void ace_watchdog(struct net_device *data) 1549{ 1550 struct net_device *dev = data; 1551 struct ace_private *ap = netdev_priv(dev); 1552 struct ace_regs __iomem *regs = ap->regs; 1553 1554 /* 1555 * We haven't received a stats update event for more than 2.5 1556 * seconds and there is data in the transmit queue, thus we 1557 * asume the card is stuck. 1558 */ 1559 if (*ap->tx_csm != ap->tx_ret_csm) { 1560 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n", 1561 dev->name, (unsigned int)readl(®s->HostCtrl)); 1562 /* This can happen due to ieee flow control. */ 1563 } else { 1564 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n", 1565 dev->name); 1566 } 1567} 1568 1569 1570static void ace_tasklet(unsigned long dev) 1571{ 1572 struct ace_private *ap = netdev_priv((struct net_device *)dev); 1573 int cur_size; 1574 1575 cur_size = atomic_read(&ap->cur_rx_bufs); 1576 if ((cur_size < RX_LOW_STD_THRES) && 1577 !test_and_set_bit(0, &ap->std_refill_busy)) { 1578#ifdef DEBUG 1579 printk("refilling buffers (current %i)\n", cur_size); 1580#endif 1581 ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size); 1582 } 1583 1584 if (ap->version >= 2) { 1585 cur_size = atomic_read(&ap->cur_mini_bufs); 1586 if ((cur_size < RX_LOW_MINI_THRES) && 1587 !test_and_set_bit(0, &ap->mini_refill_busy)) { 1588#ifdef DEBUG 1589 printk("refilling mini buffers (current %i)\n", 1590 cur_size); 1591#endif 1592 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size); 1593 } 1594 } 1595 1596 cur_size = atomic_read(&ap->cur_jumbo_bufs); 1597 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) && 1598 !test_and_set_bit(0, &ap->jumbo_refill_busy)) { 1599#ifdef DEBUG 1600 printk("refilling jumbo buffers (current %i)\n", cur_size); 1601#endif 1602 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size); 1603 } 1604 ap->tasklet_pending = 0; 1605} 1606 1607 1608/* 1609 * Copy the contents of the NIC's trace buffer to kernel memory. 1610 */ 1611static void ace_dump_trace(struct ace_private *ap) 1612{ 1613} 1614 1615 1616/* 1617 * Load the standard rx ring. 1618 * 1619 * Loading rings is safe without holding the spin lock since this is 1620 * done only before the device is enabled, thus no interrupts are 1621 * generated and by the interrupt handler/tasklet handler. 1622 */ 1623static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs) 1624{ 1625 struct ace_regs __iomem *regs = ap->regs; 1626 short i, idx; 1627 1628 1629 prefetchw(&ap->cur_rx_bufs); 1630 1631 idx = ap->rx_std_skbprd; 1632 1633 for (i = 0; i < nr_bufs; i++) { 1634 struct sk_buff *skb; 1635 struct rx_desc *rd; 1636 dma_addr_t mapping; 1637 1638 skb = alloc_skb(ACE_STD_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC); 1639 if (!skb) 1640 break; 1641 1642 skb_reserve(skb, NET_IP_ALIGN); 1643 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data), 1644 offset_in_page(skb->data), 1645 ACE_STD_BUFSIZE, 1646 PCI_DMA_FROMDEVICE); 1647 ap->skb->rx_std_skbuff[idx].skb = skb; 1648 dma_unmap_addr_set(&ap->skb->rx_std_skbuff[idx], 1649 mapping, mapping); 1650 1651 rd = &ap->rx_std_ring[idx]; 1652 set_aceaddr(&rd->addr, mapping); 1653 rd->size = ACE_STD_BUFSIZE; 1654 rd->idx = idx; 1655 idx = (idx + 1) % RX_STD_RING_ENTRIES; 1656 } 1657 1658 if (!i) 1659 goto error_out; 1660 1661 atomic_add(i, &ap->cur_rx_bufs); 1662 ap->rx_std_skbprd = idx; 1663 1664 if (ACE_IS_TIGON_I(ap)) { 1665 struct cmd cmd; 1666 cmd.evt = C_SET_RX_PRD_IDX; 1667 cmd.code = 0; 1668 cmd.idx = ap->rx_std_skbprd; 1669 ace_issue_cmd(regs, &cmd); 1670 } else { 1671 writel(idx, ®s->RxStdPrd); 1672 wmb(); 1673 } 1674 1675 out: 1676 clear_bit(0, &ap->std_refill_busy); 1677 return; 1678 1679 error_out: 1680 printk(KERN_INFO "Out of memory when allocating " 1681 "standard receive buffers\n"); 1682 goto out; 1683} 1684 1685 1686static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs) 1687{ 1688 struct ace_regs __iomem *regs = ap->regs; 1689 short i, idx; 1690 1691 prefetchw(&ap->cur_mini_bufs); 1692 1693 idx = ap->rx_mini_skbprd; 1694 for (i = 0; i < nr_bufs; i++) { 1695 struct sk_buff *skb; 1696 struct rx_desc *rd; 1697 dma_addr_t mapping; 1698 1699 skb = alloc_skb(ACE_MINI_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC); 1700 if (!skb) 1701 break; 1702 1703 skb_reserve(skb, NET_IP_ALIGN); 1704 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data), 1705 offset_in_page(skb->data), 1706 ACE_MINI_BUFSIZE, 1707 PCI_DMA_FROMDEVICE); 1708 ap->skb->rx_mini_skbuff[idx].skb = skb; 1709 dma_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx], 1710 mapping, mapping); 1711 1712 rd = &ap->rx_mini_ring[idx]; 1713 set_aceaddr(&rd->addr, mapping); 1714 rd->size = ACE_MINI_BUFSIZE; 1715 rd->idx = idx; 1716 idx = (idx + 1) % RX_MINI_RING_ENTRIES; 1717 } 1718 1719 if (!i) 1720 goto error_out; 1721 1722 atomic_add(i, &ap->cur_mini_bufs); 1723 1724 ap->rx_mini_skbprd = idx; 1725 1726 writel(idx, ®s->RxMiniPrd); 1727 wmb(); 1728 1729 out: 1730 clear_bit(0, &ap->mini_refill_busy); 1731 return; 1732 error_out: 1733 printk(KERN_INFO "Out of memory when allocating " 1734 "mini receive buffers\n"); 1735 goto out; 1736} 1737 1738 1739/* 1740 * Load the jumbo rx ring, this may happen at any time if the MTU 1741 * is changed to a value > 1500. 1742 */ 1743static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs) 1744{ 1745 struct ace_regs __iomem *regs = ap->regs; 1746 short i, idx; 1747 1748 idx = ap->rx_jumbo_skbprd; 1749 1750 for (i = 0; i < nr_bufs; i++) { 1751 struct sk_buff *skb; 1752 struct rx_desc *rd; 1753 dma_addr_t mapping; 1754 1755 skb = alloc_skb(ACE_JUMBO_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC); 1756 if (!skb) 1757 break; 1758 1759 skb_reserve(skb, NET_IP_ALIGN); 1760 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data), 1761 offset_in_page(skb->data), 1762 ACE_JUMBO_BUFSIZE, 1763 PCI_DMA_FROMDEVICE); 1764 ap->skb->rx_jumbo_skbuff[idx].skb = skb; 1765 dma_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx], 1766 mapping, mapping); 1767 1768 rd = &ap->rx_jumbo_ring[idx]; 1769 set_aceaddr(&rd->addr, mapping); 1770 rd->size = ACE_JUMBO_BUFSIZE; 1771 rd->idx = idx; 1772 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES; 1773 } 1774 1775 if (!i) 1776 goto error_out; 1777 1778 atomic_add(i, &ap->cur_jumbo_bufs); 1779 ap->rx_jumbo_skbprd = idx; 1780 1781 if (ACE_IS_TIGON_I(ap)) { 1782 struct cmd cmd; 1783 cmd.evt = C_SET_RX_JUMBO_PRD_IDX; 1784 cmd.code = 0; 1785 cmd.idx = ap->rx_jumbo_skbprd; 1786 ace_issue_cmd(regs, &cmd); 1787 } else { 1788 writel(idx, ®s->RxJumboPrd); 1789 wmb(); 1790 } 1791 1792 out: 1793 clear_bit(0, &ap->jumbo_refill_busy); 1794 return; 1795 error_out: 1796 if (net_ratelimit()) 1797 printk(KERN_INFO "Out of memory when allocating " 1798 "jumbo receive buffers\n"); 1799 goto out; 1800} 1801 1802 1803/* 1804 * All events are considered to be slow (RX/TX ints do not generate 1805 * events) and are handled here, outside the main interrupt handler, 1806 * to reduce the size of the handler. 1807 */ 1808static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd) 1809{ 1810 struct ace_private *ap; 1811 1812 ap = netdev_priv(dev); 1813 1814 while (evtcsm != evtprd) { 1815 switch (ap->evt_ring[evtcsm].evt) { 1816 case E_FW_RUNNING: 1817 printk(KERN_INFO "%s: Firmware up and running\n", 1818 ap->name); 1819 ap->fw_running = 1; 1820 wmb(); 1821 break; 1822 case E_STATS_UPDATED: 1823 break; 1824 case E_LNK_STATE: 1825 { 1826 u16 code = ap->evt_ring[evtcsm].code; 1827 switch (code) { 1828 case E_C_LINK_UP: 1829 { 1830 u32 state = readl(&ap->regs->GigLnkState); 1831 printk(KERN_WARNING "%s: Optical link UP " 1832 "(%s Duplex, Flow Control: %s%s)\n", 1833 ap->name, 1834 state & LNK_FULL_DUPLEX ? "Full":"Half", 1835 state & LNK_TX_FLOW_CTL_Y ? "TX " : "", 1836 state & LNK_RX_FLOW_CTL_Y ? "RX" : ""); 1837 break; 1838 } 1839 case E_C_LINK_DOWN: 1840 printk(KERN_WARNING "%s: Optical link DOWN\n", 1841 ap->name); 1842 break; 1843 case E_C_LINK_10_100: 1844 printk(KERN_WARNING "%s: 10/100BaseT link " 1845 "UP\n", ap->name); 1846 break; 1847 default: 1848 printk(KERN_ERR "%s: Unknown optical link " 1849 "state %02x\n", ap->name, code); 1850 } 1851 break; 1852 } 1853 case E_ERROR: 1854 switch(ap->evt_ring[evtcsm].code) { 1855 case E_C_ERR_INVAL_CMD: 1856 printk(KERN_ERR "%s: invalid command error\n", 1857 ap->name); 1858 break; 1859 case E_C_ERR_UNIMP_CMD: 1860 printk(KERN_ERR "%s: unimplemented command " 1861 "error\n", ap->name); 1862 break; 1863 case E_C_ERR_BAD_CFG: 1864 printk(KERN_ERR "%s: bad config error\n", 1865 ap->name); 1866 break; 1867 default: 1868 printk(KERN_ERR "%s: unknown error %02x\n", 1869 ap->name, ap->evt_ring[evtcsm].code); 1870 } 1871 break; 1872 case E_RESET_JUMBO_RNG: 1873 { 1874 int i; 1875 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) { 1876 if (ap->skb->rx_jumbo_skbuff[i].skb) { 1877 ap->rx_jumbo_ring[i].size = 0; 1878 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0); 1879 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb); 1880 ap->skb->rx_jumbo_skbuff[i].skb = NULL; 1881 } 1882 } 1883 1884 if (ACE_IS_TIGON_I(ap)) { 1885 struct cmd cmd; 1886 cmd.evt = C_SET_RX_JUMBO_PRD_IDX; 1887 cmd.code = 0; 1888 cmd.idx = 0; 1889 ace_issue_cmd(ap->regs, &cmd); 1890 } else { 1891 writel(0, &((ap->regs)->RxJumboPrd)); 1892 wmb(); 1893 } 1894 1895 ap->jumbo = 0; 1896 ap->rx_jumbo_skbprd = 0; 1897 printk(KERN_INFO "%s: Jumbo ring flushed\n", 1898 ap->name); 1899 clear_bit(0, &ap->jumbo_refill_busy); 1900 break; 1901 } 1902 default: 1903 printk(KERN_ERR "%s: Unhandled event 0x%02x\n", 1904 ap->name, ap->evt_ring[evtcsm].evt); 1905 } 1906 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES; 1907 } 1908 1909 return evtcsm; 1910} 1911 1912 1913static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm) 1914{ 1915 struct ace_private *ap = netdev_priv(dev); 1916 u32 idx; 1917 int mini_count = 0, std_count = 0; 1918 1919 idx = rxretcsm; 1920 1921 prefetchw(&ap->cur_rx_bufs); 1922 prefetchw(&ap->cur_mini_bufs); 1923 1924 while (idx != rxretprd) { 1925 struct ring_info *rip; 1926 struct sk_buff *skb; 1927 struct rx_desc *rxdesc, *retdesc; 1928 u32 skbidx; 1929 int bd_flags, desc_type, mapsize; 1930 u16 csum; 1931 1932 1933 /* make sure the rx descriptor isn't read before rxretprd */ 1934 if (idx == rxretcsm) 1935 rmb(); 1936 1937 retdesc = &ap->rx_return_ring[idx]; 1938 skbidx = retdesc->idx; 1939 bd_flags = retdesc->flags; 1940 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI); 1941 1942 switch(desc_type) { 1943 /* 1944 * Normal frames do not have any flags set 1945 * 1946 * Mini and normal frames arrive frequently, 1947 * so use a local counter to avoid doing 1948 * atomic operations for each packet arriving. 1949 */ 1950 case 0: 1951 rip = &ap->skb->rx_std_skbuff[skbidx]; 1952 mapsize = ACE_STD_BUFSIZE; 1953 rxdesc = &ap->rx_std_ring[skbidx]; 1954 std_count++; 1955 break; 1956 case BD_FLG_JUMBO: 1957 rip = &ap->skb->rx_jumbo_skbuff[skbidx]; 1958 mapsize = ACE_JUMBO_BUFSIZE; 1959 rxdesc = &ap->rx_jumbo_ring[skbidx]; 1960 atomic_dec(&ap->cur_jumbo_bufs); 1961 break; 1962 case BD_FLG_MINI: 1963 rip = &ap->skb->rx_mini_skbuff[skbidx]; 1964 mapsize = ACE_MINI_BUFSIZE; 1965 rxdesc = &ap->rx_mini_ring[skbidx]; 1966 mini_count++; 1967 break; 1968 default: 1969 printk(KERN_INFO "%s: unknown frame type (0x%02x) " 1970 "returned by NIC\n", dev->name, 1971 retdesc->flags); 1972 goto error; 1973 } 1974 1975 skb = rip->skb; 1976 rip->skb = NULL; 1977 pci_unmap_page(ap->pdev, 1978 dma_unmap_addr(rip, mapping), 1979 mapsize, 1980 PCI_DMA_FROMDEVICE); 1981 skb_put(skb, retdesc->size); 1982 1983 /* 1984 * Fly baby, fly! 1985 */ 1986 csum = retdesc->tcp_udp_csum; 1987 1988 skb->protocol = eth_type_trans(skb, dev); 1989 1990 /* 1991 * Instead of forcing the poor tigon mips cpu to calculate 1992 * pseudo hdr checksum, we do this ourselves. 1993 */ 1994 if (bd_flags & BD_FLG_TCP_UDP_SUM) { 1995 skb->csum = htons(csum); 1996 skb->ip_summed = CHECKSUM_COMPLETE; 1997 } else { 1998 skb->ip_summed = CHECKSUM_NONE; 1999 } 2000 2001 /* send it up */ 2002#if ACENIC_DO_VLAN 2003 if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) { 2004 vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan); 2005 } else 2006#endif 2007 netif_rx(skb); 2008 2009 dev->stats.rx_packets++; 2010 dev->stats.rx_bytes += retdesc->size; 2011 2012 idx = (idx + 1) % RX_RETURN_RING_ENTRIES; 2013 } 2014 2015 atomic_sub(std_count, &ap->cur_rx_bufs); 2016 if (!ACE_IS_TIGON_I(ap)) 2017 atomic_sub(mini_count, &ap->cur_mini_bufs); 2018 2019 out: 2020 /* 2021 * According to the documentation RxRetCsm is obsolete with 2022 * the 12.3.x Firmware - my Tigon I NICs seem to disagree! 2023 */ 2024 if (ACE_IS_TIGON_I(ap)) { 2025 writel(idx, &ap->regs->RxRetCsm); 2026 } 2027 ap->cur_rx = idx; 2028 2029 return; 2030 error: 2031 idx = rxretprd; 2032 goto out; 2033} 2034 2035 2036static inline void ace_tx_int(struct net_device *dev, 2037 u32 txcsm, u32 idx) 2038{ 2039 struct ace_private *ap = netdev_priv(dev); 2040 2041 do { 2042 struct sk_buff *skb; 2043 struct tx_ring_info *info; 2044 2045 info = ap->skb->tx_skbuff + idx; 2046 skb = info->skb; 2047 2048 if (dma_unmap_len(info, maplen)) { 2049 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping), 2050 dma_unmap_len(info, maplen), 2051 PCI_DMA_TODEVICE); 2052 dma_unmap_len_set(info, maplen, 0); 2053 } 2054 2055 if (skb) { 2056 dev->stats.tx_packets++; 2057 dev->stats.tx_bytes += skb->len; 2058 dev_kfree_skb_irq(skb); 2059 info->skb = NULL; 2060 } 2061 2062 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap); 2063 } while (idx != txcsm); 2064 2065 if (netif_queue_stopped(dev)) 2066 netif_wake_queue(dev); 2067 2068 wmb(); 2069 ap->tx_ret_csm = txcsm; 2070 2071} 2072 2073 2074static irqreturn_t ace_interrupt(int irq, void *dev_id) 2075{ 2076 struct net_device *dev = (struct net_device *)dev_id; 2077 struct ace_private *ap = netdev_priv(dev); 2078 struct ace_regs __iomem *regs = ap->regs; 2079 u32 idx; 2080 u32 txcsm, rxretcsm, rxretprd; 2081 u32 evtcsm, evtprd; 2082 2083 /* 2084 * In case of PCI shared interrupts or spurious interrupts, 2085 * we want to make sure it is actually our interrupt before 2086 * spending any time in here. 2087 */ 2088 if (!(readl(®s->HostCtrl) & IN_INT)) 2089 return IRQ_NONE; 2090 2091 /* 2092 * ACK intr now. Otherwise we will lose updates to rx_ret_prd, 2093 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before 2094 * writel(0, ®s->Mb0Lo). 2095 * 2096 * "IRQ avoidance" recommended in docs applies to IRQs served 2097 * threads and it is wrong even for that case. 2098 */ 2099 writel(0, ®s->Mb0Lo); 2100 readl(®s->Mb0Lo); 2101 2102 /* 2103 * There is no conflict between transmit handling in 2104 * start_xmit and receive processing, thus there is no reason 2105 * to take a spin lock for RX handling. Wait until we start 2106 * working on the other stuff - hey we don't need a spin lock 2107 * anymore. 2108 */ 2109 rxretprd = *ap->rx_ret_prd; 2110 rxretcsm = ap->cur_rx; 2111 2112 if (rxretprd != rxretcsm) 2113 ace_rx_int(dev, rxretprd, rxretcsm); 2114 2115 txcsm = *ap->tx_csm; 2116 idx = ap->tx_ret_csm; 2117 2118 if (txcsm != idx) { 2119 /* 2120 * If each skb takes only one descriptor this check degenerates 2121 * to identity, because new space has just been opened. 2122 * But if skbs are fragmented we must check that this index 2123 * update releases enough of space, otherwise we just 2124 * wait for device to make more work. 2125 */ 2126 if (!tx_ring_full(ap, txcsm, ap->tx_prd)) 2127 ace_tx_int(dev, txcsm, idx); 2128 } 2129 2130 evtcsm = readl(®s->EvtCsm); 2131 evtprd = *ap->evt_prd; 2132 2133 if (evtcsm != evtprd) { 2134 evtcsm = ace_handle_event(dev, evtcsm, evtprd); 2135 writel(evtcsm, ®s->EvtCsm); 2136 } 2137 2138 /* 2139 * This has to go last in the interrupt handler and run with 2140 * the spin lock released ... what lock? 2141 */ 2142 if (netif_running(dev)) { 2143 int cur_size; 2144 int run_tasklet = 0; 2145 2146 cur_size = atomic_read(&ap->cur_rx_bufs); 2147 if (cur_size < RX_LOW_STD_THRES) { 2148 if ((cur_size < RX_PANIC_STD_THRES) && 2149 !test_and_set_bit(0, &ap->std_refill_busy)) { 2150#ifdef DEBUG 2151 printk("low on std buffers %i\n", cur_size); 2152#endif 2153 ace_load_std_rx_ring(ap, 2154 RX_RING_SIZE - cur_size); 2155 } else 2156 run_tasklet = 1; 2157 } 2158 2159 if (!ACE_IS_TIGON_I(ap)) { 2160 cur_size = atomic_read(&ap->cur_mini_bufs); 2161 if (cur_size < RX_LOW_MINI_THRES) { 2162 if ((cur_size < RX_PANIC_MINI_THRES) && 2163 !test_and_set_bit(0, 2164 &ap->mini_refill_busy)) { 2165#ifdef DEBUG 2166 printk("low on mini buffers %i\n", 2167 cur_size); 2168#endif 2169 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size); 2170 } else 2171 run_tasklet = 1; 2172 } 2173 } 2174 2175 if (ap->jumbo) { 2176 cur_size = atomic_read(&ap->cur_jumbo_bufs); 2177 if (cur_size < RX_LOW_JUMBO_THRES) { 2178 if ((cur_size < RX_PANIC_JUMBO_THRES) && 2179 !test_and_set_bit(0, 2180 &ap->jumbo_refill_busy)){ 2181#ifdef DEBUG 2182 printk("low on jumbo buffers %i\n", 2183 cur_size); 2184#endif 2185 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size); 2186 } else 2187 run_tasklet = 1; 2188 } 2189 } 2190 if (run_tasklet && !ap->tasklet_pending) { 2191 ap->tasklet_pending = 1; 2192 tasklet_schedule(&ap->ace_tasklet); 2193 } 2194 } 2195 2196 return IRQ_HANDLED; 2197} 2198 2199 2200#if ACENIC_DO_VLAN 2201static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) 2202{ 2203 struct ace_private *ap = netdev_priv(dev); 2204 unsigned long flags; 2205 2206 local_irq_save(flags); 2207 ace_mask_irq(dev); 2208 2209 ap->vlgrp = grp; 2210 2211 ace_unmask_irq(dev); 2212 local_irq_restore(flags); 2213} 2214#endif /* ACENIC_DO_VLAN */ 2215 2216 2217static int ace_open(struct net_device *dev) 2218{ 2219 struct ace_private *ap = netdev_priv(dev); 2220 struct ace_regs __iomem *regs = ap->regs; 2221 struct cmd cmd; 2222 2223 if (!(ap->fw_running)) { 2224 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name); 2225 return -EBUSY; 2226 } 2227 2228 writel(dev->mtu + ETH_HLEN + 4, ®s->IfMtu); 2229 2230 cmd.evt = C_CLEAR_STATS; 2231 cmd.code = 0; 2232 cmd.idx = 0; 2233 ace_issue_cmd(regs, &cmd); 2234 2235 cmd.evt = C_HOST_STATE; 2236 cmd.code = C_C_STACK_UP; 2237 cmd.idx = 0; 2238 ace_issue_cmd(regs, &cmd); 2239 2240 if (ap->jumbo && 2241 !test_and_set_bit(0, &ap->jumbo_refill_busy)) 2242 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE); 2243 2244 if (dev->flags & IFF_PROMISC) { 2245 cmd.evt = C_SET_PROMISC_MODE; 2246 cmd.code = C_C_PROMISC_ENABLE; 2247 cmd.idx = 0; 2248 ace_issue_cmd(regs, &cmd); 2249 2250 ap->promisc = 1; 2251 }else 2252 ap->promisc = 0; 2253 ap->mcast_all = 0; 2254 2255 2256 netif_start_queue(dev); 2257 2258 /* 2259 * Setup the bottom half rx ring refill handler 2260 */ 2261 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev); 2262 return 0; 2263} 2264 2265 2266static int ace_close(struct net_device *dev) 2267{ 2268 struct ace_private *ap = netdev_priv(dev); 2269 struct ace_regs __iomem *regs = ap->regs; 2270 struct cmd cmd; 2271 unsigned long flags; 2272 short i; 2273 2274 /* 2275 * Without (or before) releasing irq and stopping hardware, this 2276 * is an absolute non-sense, by the way. It will be reset instantly 2277 * by the first irq. 2278 */ 2279 netif_stop_queue(dev); 2280 2281 2282 if (ap->promisc) { 2283 cmd.evt = C_SET_PROMISC_MODE; 2284 cmd.code = C_C_PROMISC_DISABLE; 2285 cmd.idx = 0; 2286 ace_issue_cmd(regs, &cmd); 2287 ap->promisc = 0; 2288 } 2289 2290 cmd.evt = C_HOST_STATE; 2291 cmd.code = C_C_STACK_DOWN; 2292 cmd.idx = 0; 2293 ace_issue_cmd(regs, &cmd); 2294 2295 tasklet_kill(&ap->ace_tasklet); 2296 2297 /* 2298 * Make sure one CPU is not processing packets while 2299 * buffers are being released by another. 2300 */ 2301 2302 local_irq_save(flags); 2303 ace_mask_irq(dev); 2304 2305 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) { 2306 struct sk_buff *skb; 2307 struct tx_ring_info *info; 2308 2309 info = ap->skb->tx_skbuff + i; 2310 skb = info->skb; 2311 2312 if (dma_unmap_len(info, maplen)) { 2313 if (ACE_IS_TIGON_I(ap)) { 2314 /* NB: TIGON_1 is special, tx_ring is in io space */ 2315 struct tx_desc __iomem *tx; 2316 tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i]; 2317 writel(0, &tx->addr.addrhi); 2318 writel(0, &tx->addr.addrlo); 2319 writel(0, &tx->flagsize); 2320 } else 2321 memset(ap->tx_ring + i, 0, 2322 sizeof(struct tx_desc)); 2323 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping), 2324 dma_unmap_len(info, maplen), 2325 PCI_DMA_TODEVICE); 2326 dma_unmap_len_set(info, maplen, 0); 2327 } 2328 if (skb) { 2329 dev_kfree_skb(skb); 2330 info->skb = NULL; 2331 } 2332 } 2333 2334 if (ap->jumbo) { 2335 cmd.evt = C_RESET_JUMBO_RNG; 2336 cmd.code = 0; 2337 cmd.idx = 0; 2338 ace_issue_cmd(regs, &cmd); 2339 } 2340 2341 ace_unmask_irq(dev); 2342 local_irq_restore(flags); 2343 2344 return 0; 2345} 2346 2347 2348static inline dma_addr_t 2349ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb, 2350 struct sk_buff *tail, u32 idx) 2351{ 2352 dma_addr_t mapping; 2353 struct tx_ring_info *info; 2354 2355 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data), 2356 offset_in_page(skb->data), 2357 skb->len, PCI_DMA_TODEVICE); 2358 2359 info = ap->skb->tx_skbuff + idx; 2360 info->skb = tail; 2361 dma_unmap_addr_set(info, mapping, mapping); 2362 dma_unmap_len_set(info, maplen, skb->len); 2363 return mapping; 2364} 2365 2366 2367static inline void 2368ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr, 2369 u32 flagsize, u32 vlan_tag) 2370{ 2371#if !USE_TX_COAL_NOW 2372 flagsize &= ~BD_FLG_COAL_NOW; 2373#endif 2374 2375 if (ACE_IS_TIGON_I(ap)) { 2376 struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc; 2377 writel(addr >> 32, &io->addr.addrhi); 2378 writel(addr & 0xffffffff, &io->addr.addrlo); 2379 writel(flagsize, &io->flagsize); 2380#if ACENIC_DO_VLAN 2381 writel(vlan_tag, &io->vlanres); 2382#endif 2383 } else { 2384 desc->addr.addrhi = addr >> 32; 2385 desc->addr.addrlo = addr; 2386 desc->flagsize = flagsize; 2387#if ACENIC_DO_VLAN 2388 desc->vlanres = vlan_tag; 2389#endif 2390 } 2391} 2392 2393 2394static netdev_tx_t ace_start_xmit(struct sk_buff *skb, 2395 struct net_device *dev) 2396{ 2397 struct ace_private *ap = netdev_priv(dev); 2398 struct ace_regs __iomem *regs = ap->regs; 2399 struct tx_desc *desc; 2400 u32 idx, flagsize; 2401 unsigned long maxjiff = jiffies + 3*HZ; 2402 2403restart: 2404 idx = ap->tx_prd; 2405 2406 if (tx_ring_full(ap, ap->tx_ret_csm, idx)) 2407 goto overflow; 2408 2409 if (!skb_shinfo(skb)->nr_frags) { 2410 dma_addr_t mapping; 2411 u32 vlan_tag = 0; 2412 2413 mapping = ace_map_tx_skb(ap, skb, skb, idx); 2414 flagsize = (skb->len << 16) | (BD_FLG_END); 2415 if (skb->ip_summed == CHECKSUM_PARTIAL) 2416 flagsize |= BD_FLG_TCP_UDP_SUM; 2417#if ACENIC_DO_VLAN 2418 if (vlan_tx_tag_present(skb)) { 2419 flagsize |= BD_FLG_VLAN_TAG; 2420 vlan_tag = vlan_tx_tag_get(skb); 2421 } 2422#endif 2423 desc = ap->tx_ring + idx; 2424 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap); 2425 2426 /* Look at ace_tx_int for explanations. */ 2427 if (tx_ring_full(ap, ap->tx_ret_csm, idx)) 2428 flagsize |= BD_FLG_COAL_NOW; 2429 2430 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag); 2431 } else { 2432 dma_addr_t mapping; 2433 u32 vlan_tag = 0; 2434 int i, len = 0; 2435 2436 mapping = ace_map_tx_skb(ap, skb, NULL, idx); 2437 flagsize = (skb_headlen(skb) << 16); 2438 if (skb->ip_summed == CHECKSUM_PARTIAL) 2439 flagsize |= BD_FLG_TCP_UDP_SUM; 2440#if ACENIC_DO_VLAN 2441 if (vlan_tx_tag_present(skb)) { 2442 flagsize |= BD_FLG_VLAN_TAG; 2443 vlan_tag = vlan_tx_tag_get(skb); 2444 } 2445#endif 2446 2447 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag); 2448 2449 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap); 2450 2451 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2452 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2453 struct tx_ring_info *info; 2454 2455 len += frag->size; 2456 info = ap->skb->tx_skbuff + idx; 2457 desc = ap->tx_ring + idx; 2458 2459 mapping = pci_map_page(ap->pdev, frag->page, 2460 frag->page_offset, frag->size, 2461 PCI_DMA_TODEVICE); 2462 2463 flagsize = (frag->size << 16); 2464 if (skb->ip_summed == CHECKSUM_PARTIAL) 2465 flagsize |= BD_FLG_TCP_UDP_SUM; 2466 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap); 2467 2468 if (i == skb_shinfo(skb)->nr_frags - 1) { 2469 flagsize |= BD_FLG_END; 2470 if (tx_ring_full(ap, ap->tx_ret_csm, idx)) 2471 flagsize |= BD_FLG_COAL_NOW; 2472 2473 /* 2474 * Only the last fragment frees 2475 * the skb! 2476 */ 2477 info->skb = skb; 2478 } else { 2479 info->skb = NULL; 2480 } 2481 dma_unmap_addr_set(info, mapping, mapping); 2482 dma_unmap_len_set(info, maplen, frag->size); 2483 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag); 2484 } 2485 } 2486 2487 wmb(); 2488 ap->tx_prd = idx; 2489 ace_set_txprd(regs, ap, idx); 2490 2491 if (flagsize & BD_FLG_COAL_NOW) { 2492 netif_stop_queue(dev); 2493 2494 /* 2495 * A TX-descriptor producer (an IRQ) might have gotten 2496 * inbetween, making the ring free again. Since xmit is 2497 * serialized, this is the only situation we have to 2498 * re-test. 2499 */ 2500 if (!tx_ring_full(ap, ap->tx_ret_csm, idx)) 2501 netif_wake_queue(dev); 2502 } 2503 2504 return NETDEV_TX_OK; 2505 2506overflow: 2507 /* 2508 * This race condition is unavoidable with lock-free drivers. 2509 * We wake up the queue _before_ tx_prd is advanced, so that we can 2510 * enter hard_start_xmit too early, while tx ring still looks closed. 2511 * This happens ~1-4 times per 100000 packets, so that we can allow 2512 * to loop syncing to other CPU. Probably, we need an additional 2513 * wmb() in ace_tx_intr as well. 2514 * 2515 * Note that this race is relieved by reserving one more entry 2516 * in tx ring than it is necessary (see original non-SG driver). 2517 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which 2518 * is already overkill. 2519 * 2520 * Alternative is to return with 1 not throttling queue. In this 2521 * case loop becomes longer, no more useful effects. 2522 */ 2523 if (time_before(jiffies, maxjiff)) { 2524 barrier(); 2525 cpu_relax(); 2526 goto restart; 2527 } 2528 2529 /* The ring is stuck full. */ 2530 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name); 2531 return NETDEV_TX_BUSY; 2532} 2533 2534 2535static int ace_change_mtu(struct net_device *dev, int new_mtu) 2536{ 2537 struct ace_private *ap = netdev_priv(dev); 2538 struct ace_regs __iomem *regs = ap->regs; 2539 2540 if (new_mtu > ACE_JUMBO_MTU) 2541 return -EINVAL; 2542 2543 writel(new_mtu + ETH_HLEN + 4, ®s->IfMtu); 2544 dev->mtu = new_mtu; 2545 2546 if (new_mtu > ACE_STD_MTU) { 2547 if (!(ap->jumbo)) { 2548 printk(KERN_INFO "%s: Enabling Jumbo frame " 2549 "support\n", dev->name); 2550 ap->jumbo = 1; 2551 if (!test_and_set_bit(0, &ap->jumbo_refill_busy)) 2552 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE); 2553 ace_set_rxtx_parms(dev, 1); 2554 } 2555 } else { 2556 while (test_and_set_bit(0, &ap->jumbo_refill_busy)); 2557 ace_sync_irq(dev->irq); 2558 ace_set_rxtx_parms(dev, 0); 2559 if (ap->jumbo) { 2560 struct cmd cmd; 2561 2562 cmd.evt = C_RESET_JUMBO_RNG; 2563 cmd.code = 0; 2564 cmd.idx = 0; 2565 ace_issue_cmd(regs, &cmd); 2566 } 2567 } 2568 2569 return 0; 2570} 2571 2572static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 2573{ 2574 struct ace_private *ap = netdev_priv(dev); 2575 struct ace_regs __iomem *regs = ap->regs; 2576 u32 link; 2577 2578 memset(ecmd, 0, sizeof(struct ethtool_cmd)); 2579 ecmd->supported = 2580 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | 2581 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | 2582 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | 2583 SUPPORTED_Autoneg | SUPPORTED_FIBRE); 2584 2585 ecmd->port = PORT_FIBRE; 2586 ecmd->transceiver = XCVR_INTERNAL; 2587 2588 link = readl(®s->GigLnkState); 2589 if (link & LNK_1000MB) 2590 ecmd->speed = SPEED_1000; 2591 else { 2592 link = readl(®s->FastLnkState); 2593 if (link & LNK_100MB) 2594 ecmd->speed = SPEED_100; 2595 else if (link & LNK_10MB) 2596 ecmd->speed = SPEED_10; 2597 else 2598 ecmd->speed = 0; 2599 } 2600 if (link & LNK_FULL_DUPLEX) 2601 ecmd->duplex = DUPLEX_FULL; 2602 else 2603 ecmd->duplex = DUPLEX_HALF; 2604 2605 if (link & LNK_NEGOTIATE) 2606 ecmd->autoneg = AUTONEG_ENABLE; 2607 else 2608 ecmd->autoneg = AUTONEG_DISABLE; 2609 2610 ecmd->maxtxpkt = readl(®s->TuneMaxTxDesc); 2611 ecmd->maxrxpkt = readl(®s->TuneMaxRxDesc); 2612 2613 return 0; 2614} 2615 2616static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 2617{ 2618 struct ace_private *ap = netdev_priv(dev); 2619 struct ace_regs __iomem *regs = ap->regs; 2620 u32 link, speed; 2621 2622 link = readl(®s->GigLnkState); 2623 if (link & LNK_1000MB) 2624 speed = SPEED_1000; 2625 else { 2626 link = readl(®s->FastLnkState); 2627 if (link & LNK_100MB) 2628 speed = SPEED_100; 2629 else if (link & LNK_10MB) 2630 speed = SPEED_10; 2631 else 2632 speed = SPEED_100; 2633 } 2634 2635 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB | 2636 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL; 2637 if (!ACE_IS_TIGON_I(ap)) 2638 link |= LNK_TX_FLOW_CTL_Y; 2639 if (ecmd->autoneg == AUTONEG_ENABLE) 2640 link |= LNK_NEGOTIATE; 2641 if (ecmd->speed != speed) { 2642 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB); 2643 switch (speed) { 2644 case SPEED_1000: 2645 link |= LNK_1000MB; 2646 break; 2647 case SPEED_100: 2648 link |= LNK_100MB; 2649 break; 2650 case SPEED_10: 2651 link |= LNK_10MB; 2652 break; 2653 } 2654 } 2655 2656 if (ecmd->duplex == DUPLEX_FULL) 2657 link |= LNK_FULL_DUPLEX; 2658 2659 if (link != ap->link) { 2660 struct cmd cmd; 2661 printk(KERN_INFO "%s: Renegotiating link state\n", 2662 dev->name); 2663 2664 ap->link = link; 2665 writel(link, ®s->TuneLink); 2666 if (!ACE_IS_TIGON_I(ap)) 2667 writel(link, ®s->TuneFastLink); 2668 wmb(); 2669 2670 cmd.evt = C_LNK_NEGOTIATION; 2671 cmd.code = 0; 2672 cmd.idx = 0; 2673 ace_issue_cmd(regs, &cmd); 2674 } 2675 return 0; 2676} 2677 2678static void ace_get_drvinfo(struct net_device *dev, 2679 struct ethtool_drvinfo *info) 2680{ 2681 struct ace_private *ap = netdev_priv(dev); 2682 2683 strlcpy(info->driver, "acenic", sizeof(info->driver)); 2684 snprintf(info->version, sizeof(info->version), "%i.%i.%i", 2685 ap->firmware_major, ap->firmware_minor, 2686 ap->firmware_fix); 2687 2688 if (ap->pdev) 2689 strlcpy(info->bus_info, pci_name(ap->pdev), 2690 sizeof(info->bus_info)); 2691 2692} 2693 2694/* 2695 * Set the hardware MAC address. 2696 */ 2697static int ace_set_mac_addr(struct net_device *dev, void *p) 2698{ 2699 struct ace_private *ap = netdev_priv(dev); 2700 struct ace_regs __iomem *regs = ap->regs; 2701 struct sockaddr *addr=p; 2702 u8 *da; 2703 struct cmd cmd; 2704 2705 if(netif_running(dev)) 2706 return -EBUSY; 2707 2708 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len); 2709 2710 da = (u8 *)dev->dev_addr; 2711 2712 writel(da[0] << 8 | da[1], ®s->MacAddrHi); 2713 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5], 2714 ®s->MacAddrLo); 2715 2716 cmd.evt = C_SET_MAC_ADDR; 2717 cmd.code = 0; 2718 cmd.idx = 0; 2719 ace_issue_cmd(regs, &cmd); 2720 2721 return 0; 2722} 2723 2724 2725static void ace_set_multicast_list(struct net_device *dev) 2726{ 2727 struct ace_private *ap = netdev_priv(dev); 2728 struct ace_regs __iomem *regs = ap->regs; 2729 struct cmd cmd; 2730 2731 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) { 2732 cmd.evt = C_SET_MULTICAST_MODE; 2733 cmd.code = C_C_MCAST_ENABLE; 2734 cmd.idx = 0; 2735 ace_issue_cmd(regs, &cmd); 2736 ap->mcast_all = 1; 2737 } else if (ap->mcast_all) { 2738 cmd.evt = C_SET_MULTICAST_MODE; 2739 cmd.code = C_C_MCAST_DISABLE; 2740 cmd.idx = 0; 2741 ace_issue_cmd(regs, &cmd); 2742 ap->mcast_all = 0; 2743 } 2744 2745 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) { 2746 cmd.evt = C_SET_PROMISC_MODE; 2747 cmd.code = C_C_PROMISC_ENABLE; 2748 cmd.idx = 0; 2749 ace_issue_cmd(regs, &cmd); 2750 ap->promisc = 1; 2751 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) { 2752 cmd.evt = C_SET_PROMISC_MODE; 2753 cmd.code = C_C_PROMISC_DISABLE; 2754 cmd.idx = 0; 2755 ace_issue_cmd(regs, &cmd); 2756 ap->promisc = 0; 2757 } 2758 2759 /* 2760 * For the time being multicast relies on the upper layers 2761 * filtering it properly. The Firmware does not allow one to 2762 * set the entire multicast list at a time and keeping track of 2763 * it here is going to be messy. 2764 */ 2765 if (!netdev_mc_empty(dev) && !ap->mcast_all) { 2766 cmd.evt = C_SET_MULTICAST_MODE; 2767 cmd.code = C_C_MCAST_ENABLE; 2768 cmd.idx = 0; 2769 ace_issue_cmd(regs, &cmd); 2770 }else if (!ap->mcast_all) { 2771 cmd.evt = C_SET_MULTICAST_MODE; 2772 cmd.code = C_C_MCAST_DISABLE; 2773 cmd.idx = 0; 2774 ace_issue_cmd(regs, &cmd); 2775 } 2776} 2777 2778 2779static struct net_device_stats *ace_get_stats(struct net_device *dev) 2780{ 2781 struct ace_private *ap = netdev_priv(dev); 2782 struct ace_mac_stats __iomem *mac_stats = 2783 (struct ace_mac_stats __iomem *)ap->regs->Stats; 2784 2785 dev->stats.rx_missed_errors = readl(&mac_stats->drop_space); 2786 dev->stats.multicast = readl(&mac_stats->kept_mc); 2787 dev->stats.collisions = readl(&mac_stats->coll); 2788 2789 return &dev->stats; 2790} 2791 2792 2793static void __devinit ace_copy(struct ace_regs __iomem *regs, const __be32 *src, 2794 u32 dest, int size) 2795{ 2796 void __iomem *tdest; 2797 short tsize, i; 2798 2799 if (size <= 0) 2800 return; 2801 2802 while (size > 0) { 2803 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1), 2804 min_t(u32, size, ACE_WINDOW_SIZE)); 2805 tdest = (void __iomem *) ®s->Window + 2806 (dest & (ACE_WINDOW_SIZE - 1)); 2807 writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase); 2808 for (i = 0; i < (tsize / 4); i++) { 2809 /* Firmware is big-endian */ 2810 writel(be32_to_cpup(src), tdest); 2811 src++; 2812 tdest += 4; 2813 dest += 4; 2814 size -= 4; 2815 } 2816 } 2817} 2818 2819 2820static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size) 2821{ 2822 void __iomem *tdest; 2823 short tsize = 0, i; 2824 2825 if (size <= 0) 2826 return; 2827 2828 while (size > 0) { 2829 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1), 2830 min_t(u32, size, ACE_WINDOW_SIZE)); 2831 tdest = (void __iomem *) ®s->Window + 2832 (dest & (ACE_WINDOW_SIZE - 1)); 2833 writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase); 2834 2835 for (i = 0; i < (tsize / 4); i++) { 2836 writel(0, tdest + i*4); 2837 } 2838 2839 dest += tsize; 2840 size -= tsize; 2841 } 2842} 2843 2844 2845/* 2846 * Download the firmware into the SRAM on the NIC 2847 * 2848 * This operation requires the NIC to be halted and is performed with 2849 * interrupts disabled and with the spinlock hold. 2850 */ 2851static int __devinit ace_load_firmware(struct net_device *dev) 2852{ 2853 const struct firmware *fw; 2854 const char *fw_name = "acenic/tg2.bin"; 2855 struct ace_private *ap = netdev_priv(dev); 2856 struct ace_regs __iomem *regs = ap->regs; 2857 const __be32 *fw_data; 2858 u32 load_addr; 2859 int ret; 2860 2861 if (!(readl(®s->CpuCtrl) & CPU_HALTED)) { 2862 printk(KERN_ERR "%s: trying to download firmware while the " 2863 "CPU is running!\n", ap->name); 2864 return -EFAULT; 2865 } 2866 2867 if (ACE_IS_TIGON_I(ap)) 2868 fw_name = "acenic/tg1.bin"; 2869 2870 ret = request_firmware(&fw, fw_name, &ap->pdev->dev); 2871 if (ret) { 2872 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n", 2873 ap->name, fw_name); 2874 return ret; 2875 } 2876 2877 fw_data = (void *)fw->data; 2878 2879 /* Firmware blob starts with version numbers, followed by 2880 load and start address. Remainder is the blob to be loaded 2881 contiguously from load address. We don't bother to represent 2882 the BSS/SBSS sections any more, since we were clearing the 2883 whole thing anyway. */ 2884 ap->firmware_major = fw->data[0]; 2885 ap->firmware_minor = fw->data[1]; 2886 ap->firmware_fix = fw->data[2]; 2887 2888 ap->firmware_start = be32_to_cpu(fw_data[1]); 2889 if (ap->firmware_start < 0x4000 || ap->firmware_start >= 0x80000) { 2890 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n", 2891 ap->name, ap->firmware_start, fw_name); 2892 ret = -EINVAL; 2893 goto out; 2894 } 2895 2896 load_addr = be32_to_cpu(fw_data[2]); 2897 if (load_addr < 0x4000 || load_addr >= 0x80000) { 2898 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n", 2899 ap->name, load_addr, fw_name); 2900 ret = -EINVAL; 2901 goto out; 2902 } 2903 2904 /* 2905 * Do not try to clear more than 512KiB or we end up seeing 2906 * funny things on NICs with only 512KiB SRAM 2907 */ 2908 ace_clear(regs, 0x2000, 0x80000-0x2000); 2909 ace_copy(regs, &fw_data[3], load_addr, fw->size-12); 2910 out: 2911 release_firmware(fw); 2912 return ret; 2913} 2914 2915 2916/* 2917 * The eeprom on the AceNIC is an Atmel i2c EEPROM. 2918 * 2919 * Accessing the EEPROM is `interesting' to say the least - don't read 2920 * this code right after dinner. 2921 * 2922 * This is all about black magic and bit-banging the device .... I 2923 * wonder in what hospital they have put the guy who designed the i2c 2924 * specs. 2925 * 2926 * Oh yes, this is only the beginning! 2927 * 2928 * Thanks to Stevarino Webinski for helping tracking down the bugs in the 2929 * code i2c readout code by beta testing all my hacks. 2930 */ 2931static void __devinit eeprom_start(struct ace_regs __iomem *regs) 2932{ 2933 u32 local; 2934 2935 readl(®s->LocalCtrl); 2936 udelay(ACE_SHORT_DELAY); 2937 local = readl(®s->LocalCtrl); 2938 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE; 2939 writel(local, ®s->LocalCtrl); 2940 readl(®s->LocalCtrl); 2941 mb(); 2942 udelay(ACE_SHORT_DELAY); 2943 local |= EEPROM_CLK_OUT; 2944 writel(local, ®s->LocalCtrl); 2945 readl(®s->LocalCtrl); 2946 mb(); 2947 udelay(ACE_SHORT_DELAY); 2948 local &= ~EEPROM_DATA_OUT; 2949 writel(local, ®s->LocalCtrl); 2950 readl(®s->LocalCtrl); 2951 mb(); 2952 udelay(ACE_SHORT_DELAY); 2953 local &= ~EEPROM_CLK_OUT; 2954 writel(local, ®s->LocalCtrl); 2955 readl(®s->LocalCtrl); 2956 mb(); 2957} 2958 2959 2960static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic) 2961{ 2962 short i; 2963 u32 local; 2964 2965 udelay(ACE_SHORT_DELAY); 2966 local = readl(®s->LocalCtrl); 2967 local &= ~EEPROM_DATA_OUT; 2968 local |= EEPROM_WRITE_ENABLE; 2969 writel(local, ®s->LocalCtrl); 2970 readl(®s->LocalCtrl); 2971 mb(); 2972 2973 for (i = 0; i < 8; i++, magic <<= 1) { 2974 udelay(ACE_SHORT_DELAY); 2975 if (magic & 0x80) 2976 local |= EEPROM_DATA_OUT; 2977 else 2978 local &= ~EEPROM_DATA_OUT; 2979 writel(local, ®s->LocalCtrl); 2980 readl(®s->LocalCtrl); 2981 mb(); 2982 2983 udelay(ACE_SHORT_DELAY); 2984 local |= EEPROM_CLK_OUT; 2985 writel(local, ®s->LocalCtrl); 2986 readl(®s->LocalCtrl); 2987 mb(); 2988 udelay(ACE_SHORT_DELAY); 2989 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT); 2990 writel(local, ®s->LocalCtrl); 2991 readl(®s->LocalCtrl); 2992 mb(); 2993 } 2994} 2995 2996 2997static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs) 2998{ 2999 int state; 3000 u32 local; 3001 3002 local = readl(®s->LocalCtrl); 3003 local &= ~EEPROM_WRITE_ENABLE; 3004 writel(local, ®s->LocalCtrl); 3005 readl(®s->LocalCtrl); 3006 mb(); 3007 udelay(ACE_LONG_DELAY); 3008 local |= EEPROM_CLK_OUT; 3009 writel(local, ®s->LocalCtrl); 3010 readl(®s->LocalCtrl); 3011 mb(); 3012 udelay(ACE_SHORT_DELAY); 3013 /* sample data in middle of high clk */ 3014 state = (readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0; 3015 udelay(ACE_SHORT_DELAY); 3016 mb(); 3017 writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl); 3018 readl(®s->LocalCtrl); 3019 mb(); 3020 3021 return state; 3022} 3023 3024 3025static void __devinit eeprom_stop(struct ace_regs __iomem *regs) 3026{ 3027 u32 local; 3028 3029 udelay(ACE_SHORT_DELAY); 3030 local = readl(®s->LocalCtrl); 3031 local |= EEPROM_WRITE_ENABLE; 3032 writel(local, ®s->LocalCtrl); 3033 readl(®s->LocalCtrl); 3034 mb(); 3035 udelay(ACE_SHORT_DELAY); 3036 local &= ~EEPROM_DATA_OUT; 3037 writel(local, ®s->LocalCtrl); 3038 readl(®s->LocalCtrl); 3039 mb(); 3040 udelay(ACE_SHORT_DELAY); 3041 local |= EEPROM_CLK_OUT; 3042 writel(local, ®s->LocalCtrl); 3043 readl(®s->LocalCtrl); 3044 mb(); 3045 udelay(ACE_SHORT_DELAY); 3046 local |= EEPROM_DATA_OUT; 3047 writel(local, ®s->LocalCtrl); 3048 readl(®s->LocalCtrl); 3049 mb(); 3050 udelay(ACE_LONG_DELAY); 3051 local &= ~EEPROM_CLK_OUT; 3052 writel(local, ®s->LocalCtrl); 3053 mb(); 3054} 3055 3056 3057/* 3058 * Read a whole byte from the EEPROM. 3059 */ 3060static int __devinit read_eeprom_byte(struct net_device *dev, 3061 unsigned long offset) 3062{ 3063 struct ace_private *ap = netdev_priv(dev); 3064 struct ace_regs __iomem *regs = ap->regs; 3065 unsigned long flags; 3066 u32 local; 3067 int result = 0; 3068 short i; 3069 3070 /* 3071 * Don't take interrupts on this CPU will bit banging 3072 * the %#%#@$ I2C device 3073 */ 3074 local_irq_save(flags); 3075 3076 eeprom_start(regs); 3077 3078 eeprom_prep(regs, EEPROM_WRITE_SELECT); 3079 if (eeprom_check_ack(regs)) { 3080 local_irq_restore(flags); 3081 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name); 3082 result = -EIO; 3083 goto eeprom_read_error; 3084 } 3085 3086 eeprom_prep(regs, (offset >> 8) & 0xff); 3087 if (eeprom_check_ack(regs)) { 3088 local_irq_restore(flags); 3089 printk(KERN_ERR "%s: Unable to set address byte 0\n", 3090 ap->name); 3091 result = -EIO; 3092 goto eeprom_read_error; 3093 } 3094 3095 eeprom_prep(regs, offset & 0xff); 3096 if (eeprom_check_ack(regs)) { 3097 local_irq_restore(flags); 3098 printk(KERN_ERR "%s: Unable to set address byte 1\n", 3099 ap->name); 3100 result = -EIO; 3101 goto eeprom_read_error; 3102 } 3103 3104 eeprom_start(regs); 3105 eeprom_prep(regs, EEPROM_READ_SELECT); 3106 if (eeprom_check_ack(regs)) { 3107 local_irq_restore(flags); 3108 printk(KERN_ERR "%s: Unable to set READ_SELECT\n", 3109 ap->name); 3110 result = -EIO; 3111 goto eeprom_read_error; 3112 } 3113 3114 for (i = 0; i < 8; i++) { 3115 local = readl(®s->LocalCtrl); 3116 local &= ~EEPROM_WRITE_ENABLE; 3117 writel(local, ®s->LocalCtrl); 3118 readl(®s->LocalCtrl); 3119 udelay(ACE_LONG_DELAY); 3120 mb(); 3121 local |= EEPROM_CLK_OUT; 3122 writel(local, ®s->LocalCtrl); 3123 readl(®s->LocalCtrl); 3124 mb(); 3125 udelay(ACE_SHORT_DELAY); 3126 /* sample data mid high clk */ 3127 result = (result << 1) | 3128 ((readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0); 3129 udelay(ACE_SHORT_DELAY); 3130 mb(); 3131 local = readl(®s->LocalCtrl); 3132 local &= ~EEPROM_CLK_OUT; 3133 writel(local, ®s->LocalCtrl); 3134 readl(®s->LocalCtrl); 3135 udelay(ACE_SHORT_DELAY); 3136 mb(); 3137 if (i == 7) { 3138 local |= EEPROM_WRITE_ENABLE; 3139 writel(local, ®s->LocalCtrl); 3140 readl(®s->LocalCtrl); 3141 mb(); 3142 udelay(ACE_SHORT_DELAY); 3143 } 3144 } 3145 3146 local |= EEPROM_DATA_OUT; 3147 writel(local, ®s->LocalCtrl); 3148 readl(®s->LocalCtrl); 3149 mb(); 3150 udelay(ACE_SHORT_DELAY); 3151 writel(readl(®s->LocalCtrl) | EEPROM_CLK_OUT, ®s->LocalCtrl); 3152 readl(®s->LocalCtrl); 3153 udelay(ACE_LONG_DELAY); 3154 writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl); 3155 readl(®s->LocalCtrl); 3156 mb(); 3157 udelay(ACE_SHORT_DELAY); 3158 eeprom_stop(regs); 3159 3160 local_irq_restore(flags); 3161 out: 3162 return result; 3163 3164 eeprom_read_error: 3165 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n", 3166 ap->name, offset); 3167 goto out; 3168} 3169