1/* 2 * NAND Flash Controller Device Driver 3 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 * 18 */ 19 20#include <linux/mtd/nand.h> 21 22#define DEVICE_RESET 0x0 23#define DEVICE_RESET__BANK0 0x0001 24#define DEVICE_RESET__BANK1 0x0002 25#define DEVICE_RESET__BANK2 0x0004 26#define DEVICE_RESET__BANK3 0x0008 27 28#define TRANSFER_SPARE_REG 0x10 29#define TRANSFER_SPARE_REG__FLAG 0x0001 30 31#define LOAD_WAIT_CNT 0x20 32#define LOAD_WAIT_CNT__VALUE 0xffff 33 34#define PROGRAM_WAIT_CNT 0x30 35#define PROGRAM_WAIT_CNT__VALUE 0xffff 36 37#define ERASE_WAIT_CNT 0x40 38#define ERASE_WAIT_CNT__VALUE 0xffff 39 40#define INT_MON_CYCCNT 0x50 41#define INT_MON_CYCCNT__VALUE 0xffff 42 43#define RB_PIN_ENABLED 0x60 44#define RB_PIN_ENABLED__BANK0 0x0001 45#define RB_PIN_ENABLED__BANK1 0x0002 46#define RB_PIN_ENABLED__BANK2 0x0004 47#define RB_PIN_ENABLED__BANK3 0x0008 48 49#define MULTIPLANE_OPERATION 0x70 50#define MULTIPLANE_OPERATION__FLAG 0x0001 51 52#define MULTIPLANE_READ_ENABLE 0x80 53#define MULTIPLANE_READ_ENABLE__FLAG 0x0001 54 55#define COPYBACK_DISABLE 0x90 56#define COPYBACK_DISABLE__FLAG 0x0001 57 58#define CACHE_WRITE_ENABLE 0xa0 59#define CACHE_WRITE_ENABLE__FLAG 0x0001 60 61#define CACHE_READ_ENABLE 0xb0 62#define CACHE_READ_ENABLE__FLAG 0x0001 63 64#define PREFETCH_MODE 0xc0 65#define PREFETCH_MODE__PREFETCH_EN 0x0001 66#define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0 67 68#define CHIP_ENABLE_DONT_CARE 0xd0 69#define CHIP_EN_DONT_CARE__FLAG 0x01 70 71#define ECC_ENABLE 0xe0 72#define ECC_ENABLE__FLAG 0x0001 73 74#define GLOBAL_INT_ENABLE 0xf0 75#define GLOBAL_INT_EN_FLAG 0x01 76 77#define WE_2_RE 0x100 78#define WE_2_RE__VALUE 0x003f 79 80#define ADDR_2_DATA 0x110 81#define ADDR_2_DATA__VALUE 0x003f 82 83#define RE_2_WE 0x120 84#define RE_2_WE__VALUE 0x003f 85 86#define ACC_CLKS 0x130 87#define ACC_CLKS__VALUE 0x000f 88 89#define NUMBER_OF_PLANES 0x140 90#define NUMBER_OF_PLANES__VALUE 0x0007 91 92#define PAGES_PER_BLOCK 0x150 93#define PAGES_PER_BLOCK__VALUE 0xffff 94 95#define DEVICE_WIDTH 0x160 96#define DEVICE_WIDTH__VALUE 0x0003 97 98#define DEVICE_MAIN_AREA_SIZE 0x170 99#define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff 100 101#define DEVICE_SPARE_AREA_SIZE 0x180 102#define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff 103 104#define TWO_ROW_ADDR_CYCLES 0x190 105#define TWO_ROW_ADDR_CYCLES__FLAG 0x0001 106 107#define MULTIPLANE_ADDR_RESTRICT 0x1a0 108#define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001 109 110#define ECC_CORRECTION 0x1b0 111#define ECC_CORRECTION__VALUE 0x001f 112 113#define READ_MODE 0x1c0 114#define READ_MODE__VALUE 0x000f 115 116#define WRITE_MODE 0x1d0 117#define WRITE_MODE__VALUE 0x000f 118 119#define COPYBACK_MODE 0x1e0 120#define COPYBACK_MODE__VALUE 0x000f 121 122#define RDWR_EN_LO_CNT 0x1f0 123#define RDWR_EN_LO_CNT__VALUE 0x001f 124 125#define RDWR_EN_HI_CNT 0x200 126#define RDWR_EN_HI_CNT__VALUE 0x001f 127 128#define MAX_RD_DELAY 0x210 129#define MAX_RD_DELAY__VALUE 0x000f 130 131#define CS_SETUP_CNT 0x220 132#define CS_SETUP_CNT__VALUE 0x001f 133 134#define SPARE_AREA_SKIP_BYTES 0x230 135#define SPARE_AREA_SKIP_BYTES__VALUE 0x003f 136 137#define SPARE_AREA_MARKER 0x240 138#define SPARE_AREA_MARKER__VALUE 0xffff 139 140#define DEVICES_CONNECTED 0x250 141#define DEVICES_CONNECTED__VALUE 0x0007 142 143#define DIE_MASK 0x260 144#define DIE_MASK__VALUE 0x00ff 145 146#define FIRST_BLOCK_OF_NEXT_PLANE 0x270 147#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff 148 149#define WRITE_PROTECT 0x280 150#define WRITE_PROTECT__FLAG 0x0001 151 152#define RE_2_RE 0x290 153#define RE_2_RE__VALUE 0x003f 154 155#define MANUFACTURER_ID 0x300 156#define MANUFACTURER_ID__VALUE 0x00ff 157 158#define DEVICE_ID 0x310 159#define DEVICE_ID__VALUE 0x00ff 160 161#define DEVICE_PARAM_0 0x320 162#define DEVICE_PARAM_0__VALUE 0x00ff 163 164#define DEVICE_PARAM_1 0x330 165#define DEVICE_PARAM_1__VALUE 0x00ff 166 167#define DEVICE_PARAM_2 0x340 168#define DEVICE_PARAM_2__VALUE 0x00ff 169 170#define LOGICAL_PAGE_DATA_SIZE 0x350 171#define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff 172 173#define LOGICAL_PAGE_SPARE_SIZE 0x360 174#define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff 175 176#define REVISION 0x370 177#define REVISION__VALUE 0xffff 178 179#define ONFI_DEVICE_FEATURES 0x380 180#define ONFI_DEVICE_FEATURES__VALUE 0x003f 181 182#define ONFI_OPTIONAL_COMMANDS 0x390 183#define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f 184 185#define ONFI_TIMING_MODE 0x3a0 186#define ONFI_TIMING_MODE__VALUE 0x003f 187 188#define ONFI_PGM_CACHE_TIMING_MODE 0x3b0 189#define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f 190 191#define ONFI_DEVICE_NO_OF_LUNS 0x3c0 192#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff 193#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100 194 195#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0 196#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff 197 198#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0 199#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff 200 201#define FEATURES 0x3f0 202#define FEATURES__N_BANKS 0x0003 203#define FEATURES__ECC_MAX_ERR 0x003c 204#define FEATURES__DMA 0x0040 205#define FEATURES__CMD_DMA 0x0080 206#define FEATURES__PARTITION 0x0100 207#define FEATURES__XDMA_SIDEBAND 0x0200 208#define FEATURES__GPREG 0x0400 209#define FEATURES__INDEX_ADDR 0x0800 210 211#define TRANSFER_MODE 0x400 212#define TRANSFER_MODE__VALUE 0x0003 213 214#define INTR_STATUS0 0x410 215#define INTR_STATUS0__ECC_TRANSACTION_DONE 0x0001 216#define INTR_STATUS0__ECC_ERR 0x0002 217#define INTR_STATUS0__DMA_CMD_COMP 0x0004 218#define INTR_STATUS0__TIME_OUT 0x0008 219#define INTR_STATUS0__PROGRAM_FAIL 0x0010 220#define INTR_STATUS0__ERASE_FAIL 0x0020 221#define INTR_STATUS0__LOAD_COMP 0x0040 222#define INTR_STATUS0__PROGRAM_COMP 0x0080 223#define INTR_STATUS0__ERASE_COMP 0x0100 224#define INTR_STATUS0__PIPE_CPYBCK_CMD_COMP 0x0200 225#define INTR_STATUS0__LOCKED_BLK 0x0400 226#define INTR_STATUS0__UNSUP_CMD 0x0800 227#define INTR_STATUS0__INT_ACT 0x1000 228#define INTR_STATUS0__RST_COMP 0x2000 229#define INTR_STATUS0__PIPE_CMD_ERR 0x4000 230#define INTR_STATUS0__PAGE_XFER_INC 0x8000 231 232#define INTR_EN0 0x420 233#define INTR_EN0__ECC_TRANSACTION_DONE 0x0001 234#define INTR_EN0__ECC_ERR 0x0002 235#define INTR_EN0__DMA_CMD_COMP 0x0004 236#define INTR_EN0__TIME_OUT 0x0008 237#define INTR_EN0__PROGRAM_FAIL 0x0010 238#define INTR_EN0__ERASE_FAIL 0x0020 239#define INTR_EN0__LOAD_COMP 0x0040 240#define INTR_EN0__PROGRAM_COMP 0x0080 241#define INTR_EN0__ERASE_COMP 0x0100 242#define INTR_EN0__PIPE_CPYBCK_CMD_COMP 0x0200 243#define INTR_EN0__LOCKED_BLK 0x0400 244#define INTR_EN0__UNSUP_CMD 0x0800 245#define INTR_EN0__INT_ACT 0x1000 246#define INTR_EN0__RST_COMP 0x2000 247#define INTR_EN0__PIPE_CMD_ERR 0x4000 248#define INTR_EN0__PAGE_XFER_INC 0x8000 249 250#define PAGE_CNT0 0x430 251#define PAGE_CNT0__VALUE 0x00ff 252 253#define ERR_PAGE_ADDR0 0x440 254#define ERR_PAGE_ADDR0__VALUE 0xffff 255 256#define ERR_BLOCK_ADDR0 0x450 257#define ERR_BLOCK_ADDR0__VALUE 0xffff 258 259#define INTR_STATUS1 0x460 260#define INTR_STATUS1__ECC_TRANSACTION_DONE 0x0001 261#define INTR_STATUS1__ECC_ERR 0x0002 262#define INTR_STATUS1__DMA_CMD_COMP 0x0004 263#define INTR_STATUS1__TIME_OUT 0x0008 264#define INTR_STATUS1__PROGRAM_FAIL 0x0010 265#define INTR_STATUS1__ERASE_FAIL 0x0020 266#define INTR_STATUS1__LOAD_COMP 0x0040 267#define INTR_STATUS1__PROGRAM_COMP 0x0080 268#define INTR_STATUS1__ERASE_COMP 0x0100 269#define INTR_STATUS1__PIPE_CPYBCK_CMD_COMP 0x0200 270#define INTR_STATUS1__LOCKED_BLK 0x0400 271#define INTR_STATUS1__UNSUP_CMD 0x0800 272#define INTR_STATUS1__INT_ACT 0x1000 273#define INTR_STATUS1__RST_COMP 0x2000 274#define INTR_STATUS1__PIPE_CMD_ERR 0x4000 275#define INTR_STATUS1__PAGE_XFER_INC 0x8000 276 277#define INTR_EN1 0x470 278#define INTR_EN1__ECC_TRANSACTION_DONE 0x0001 279#define INTR_EN1__ECC_ERR 0x0002 280#define INTR_EN1__DMA_CMD_COMP 0x0004 281#define INTR_EN1__TIME_OUT 0x0008 282#define INTR_EN1__PROGRAM_FAIL 0x0010 283#define INTR_EN1__ERASE_FAIL 0x0020 284#define INTR_EN1__LOAD_COMP 0x0040 285#define INTR_EN1__PROGRAM_COMP 0x0080 286#define INTR_EN1__ERASE_COMP 0x0100 287#define INTR_EN1__PIPE_CPYBCK_CMD_COMP 0x0200 288#define INTR_EN1__LOCKED_BLK 0x0400 289#define INTR_EN1__UNSUP_CMD 0x0800 290#define INTR_EN1__INT_ACT 0x1000 291#define INTR_EN1__RST_COMP 0x2000 292#define INTR_EN1__PIPE_CMD_ERR 0x4000 293#define INTR_EN1__PAGE_XFER_INC 0x8000 294 295#define PAGE_CNT1 0x480 296#define PAGE_CNT1__VALUE 0x00ff 297 298#define ERR_PAGE_ADDR1 0x490 299#define ERR_PAGE_ADDR1__VALUE 0xffff 300 301#define ERR_BLOCK_ADDR1 0x4a0 302#define ERR_BLOCK_ADDR1__VALUE 0xffff 303 304#define INTR_STATUS2 0x4b0 305#define INTR_STATUS2__ECC_TRANSACTION_DONE 0x0001 306#define INTR_STATUS2__ECC_ERR 0x0002 307#define INTR_STATUS2__DMA_CMD_COMP 0x0004 308#define INTR_STATUS2__TIME_OUT 0x0008 309#define INTR_STATUS2__PROGRAM_FAIL 0x0010 310#define INTR_STATUS2__ERASE_FAIL 0x0020 311#define INTR_STATUS2__LOAD_COMP 0x0040 312#define INTR_STATUS2__PROGRAM_COMP 0x0080 313#define INTR_STATUS2__ERASE_COMP 0x0100 314#define INTR_STATUS2__PIPE_CPYBCK_CMD_COMP 0x0200 315#define INTR_STATUS2__LOCKED_BLK 0x0400 316#define INTR_STATUS2__UNSUP_CMD 0x0800 317#define INTR_STATUS2__INT_ACT 0x1000 318#define INTR_STATUS2__RST_COMP 0x2000 319#define INTR_STATUS2__PIPE_CMD_ERR 0x4000 320#define INTR_STATUS2__PAGE_XFER_INC 0x8000 321 322#define INTR_EN2 0x4c0 323#define INTR_EN2__ECC_TRANSACTION_DONE 0x0001 324#define INTR_EN2__ECC_ERR 0x0002 325#define INTR_EN2__DMA_CMD_COMP 0x0004 326#define INTR_EN2__TIME_OUT 0x0008 327#define INTR_EN2__PROGRAM_FAIL 0x0010 328#define INTR_EN2__ERASE_FAIL 0x0020 329#define INTR_EN2__LOAD_COMP 0x0040 330#define INTR_EN2__PROGRAM_COMP 0x0080 331#define INTR_EN2__ERASE_COMP 0x0100 332#define INTR_EN2__PIPE_CPYBCK_CMD_COMP 0x0200 333#define INTR_EN2__LOCKED_BLK 0x0400 334#define INTR_EN2__UNSUP_CMD 0x0800 335#define INTR_EN2__INT_ACT 0x1000 336#define INTR_EN2__RST_COMP 0x2000 337#define INTR_EN2__PIPE_CMD_ERR 0x4000 338#define INTR_EN2__PAGE_XFER_INC 0x8000 339 340#define PAGE_CNT2 0x4d0 341#define PAGE_CNT2__VALUE 0x00ff 342 343#define ERR_PAGE_ADDR2 0x4e0 344#define ERR_PAGE_ADDR2__VALUE 0xffff 345 346#define ERR_BLOCK_ADDR2 0x4f0 347#define ERR_BLOCK_ADDR2__VALUE 0xffff 348 349#define INTR_STATUS3 0x500 350#define INTR_STATUS3__ECC_TRANSACTION_DONE 0x0001 351#define INTR_STATUS3__ECC_ERR 0x0002 352#define INTR_STATUS3__DMA_CMD_COMP 0x0004 353#define INTR_STATUS3__TIME_OUT 0x0008 354#define INTR_STATUS3__PROGRAM_FAIL 0x0010 355#define INTR_STATUS3__ERASE_FAIL 0x0020 356#define INTR_STATUS3__LOAD_COMP 0x0040 357#define INTR_STATUS3__PROGRAM_COMP 0x0080 358#define INTR_STATUS3__ERASE_COMP 0x0100 359#define INTR_STATUS3__PIPE_CPYBCK_CMD_COMP 0x0200 360#define INTR_STATUS3__LOCKED_BLK 0x0400 361#define INTR_STATUS3__UNSUP_CMD 0x0800 362#define INTR_STATUS3__INT_ACT 0x1000 363#define INTR_STATUS3__RST_COMP 0x2000 364#define INTR_STATUS3__PIPE_CMD_ERR 0x4000 365#define INTR_STATUS3__PAGE_XFER_INC 0x8000 366 367#define INTR_EN3 0x510 368#define INTR_EN3__ECC_TRANSACTION_DONE 0x0001 369#define INTR_EN3__ECC_ERR 0x0002 370#define INTR_EN3__DMA_CMD_COMP 0x0004 371#define INTR_EN3__TIME_OUT 0x0008 372#define INTR_EN3__PROGRAM_FAIL 0x0010 373#define INTR_EN3__ERASE_FAIL 0x0020 374#define INTR_EN3__LOAD_COMP 0x0040 375#define INTR_EN3__PROGRAM_COMP 0x0080 376#define INTR_EN3__ERASE_COMP 0x0100 377#define INTR_EN3__PIPE_CPYBCK_CMD_COMP 0x0200 378#define INTR_EN3__LOCKED_BLK 0x0400 379#define INTR_EN3__UNSUP_CMD 0x0800 380#define INTR_EN3__INT_ACT 0x1000 381#define INTR_EN3__RST_COMP 0x2000 382#define INTR_EN3__PIPE_CMD_ERR 0x4000 383#define INTR_EN3__PAGE_XFER_INC 0x8000 384 385#define PAGE_CNT3 0x520 386#define PAGE_CNT3__VALUE 0x00ff 387 388#define ERR_PAGE_ADDR3 0x530 389#define ERR_PAGE_ADDR3__VALUE 0xffff 390 391#define ERR_BLOCK_ADDR3 0x540 392#define ERR_BLOCK_ADDR3__VALUE 0xffff 393 394#define DATA_INTR 0x550 395#define DATA_INTR__WRITE_SPACE_AV 0x0001 396#define DATA_INTR__READ_DATA_AV 0x0002 397 398#define DATA_INTR_EN 0x560 399#define DATA_INTR_EN__WRITE_SPACE_AV 0x0001 400#define DATA_INTR_EN__READ_DATA_AV 0x0002 401 402#define GPREG_0 0x570 403#define GPREG_0__VALUE 0xffff 404 405#define GPREG_1 0x580 406#define GPREG_1__VALUE 0xffff 407 408#define GPREG_2 0x590 409#define GPREG_2__VALUE 0xffff 410 411#define GPREG_3 0x5a0 412#define GPREG_3__VALUE 0xffff 413 414#define ECC_THRESHOLD 0x600 415#define ECC_THRESHOLD__VALUE 0x03ff 416 417#define ECC_ERROR_BLOCK_ADDRESS 0x610 418#define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff 419 420#define ECC_ERROR_PAGE_ADDRESS 0x620 421#define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff 422#define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000 423 424#define ECC_ERROR_ADDRESS 0x630 425#define ECC_ERROR_ADDRESS__OFFSET 0x0fff 426#define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000 427 428#define ERR_CORRECTION_INFO 0x640 429#define ERR_CORRECTION_INFO__BYTEMASK 0x00ff 430#define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00 431#define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000 432#define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000 433 434#define DMA_ENABLE 0x700 435#define DMA_ENABLE__FLAG 0x0001 436 437#define IGNORE_ECC_DONE 0x710 438#define IGNORE_ECC_DONE__FLAG 0x0001 439 440#define DMA_INTR 0x720 441#define DMA_INTR__TARGET_ERROR 0x0001 442#define DMA_INTR__DESC_COMP_CHANNEL0 0x0002 443#define DMA_INTR__DESC_COMP_CHANNEL1 0x0004 444#define DMA_INTR__DESC_COMP_CHANNEL2 0x0008 445#define DMA_INTR__DESC_COMP_CHANNEL3 0x0010 446#define DMA_INTR__MEMCOPY_DESC_COMP 0x0020 447 448#define DMA_INTR_EN 0x730 449#define DMA_INTR_EN__TARGET_ERROR 0x0001 450#define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002 451#define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004 452#define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008 453#define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010 454#define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020 455 456#define TARGET_ERR_ADDR_LO 0x740 457#define TARGET_ERR_ADDR_LO__VALUE 0xffff 458 459#define TARGET_ERR_ADDR_HI 0x750 460#define TARGET_ERR_ADDR_HI__VALUE 0xffff 461 462#define CHNL_ACTIVE 0x760 463#define CHNL_ACTIVE__CHANNEL0 0x0001 464#define CHNL_ACTIVE__CHANNEL1 0x0002 465#define CHNL_ACTIVE__CHANNEL2 0x0004 466#define CHNL_ACTIVE__CHANNEL3 0x0008 467 468#define ACTIVE_SRC_ID 0x800 469#define ACTIVE_SRC_ID__VALUE 0x00ff 470 471#define PTN_INTR 0x810 472#define PTN_INTR__CONFIG_ERROR 0x0001 473#define PTN_INTR__ACCESS_ERROR_BANK0 0x0002 474#define PTN_INTR__ACCESS_ERROR_BANK1 0x0004 475#define PTN_INTR__ACCESS_ERROR_BANK2 0x0008 476#define PTN_INTR__ACCESS_ERROR_BANK3 0x0010 477#define PTN_INTR__REG_ACCESS_ERROR 0x0020 478 479#define PTN_INTR_EN 0x820 480#define PTN_INTR_EN__CONFIG_ERROR 0x0001 481#define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002 482#define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004 483#define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008 484#define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010 485#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020 486 487#define PERM_SRC_ID_0 0x830 488#define PERM_SRC_ID_0__SRCID 0x00ff 489#define PERM_SRC_ID_0__DIRECT_ACCESS_ACTIVE 0x0800 490#define PERM_SRC_ID_0__WRITE_ACTIVE 0x2000 491#define PERM_SRC_ID_0__READ_ACTIVE 0x4000 492#define PERM_SRC_ID_0__PARTITION_VALID 0x8000 493 494#define MIN_BLK_ADDR_0 0x840 495#define MIN_BLK_ADDR_0__VALUE 0xffff 496 497#define MAX_BLK_ADDR_0 0x850 498#define MAX_BLK_ADDR_0__VALUE 0xffff 499 500#define MIN_MAX_BANK_0 0x860 501#define MIN_MAX_BANK_0__MIN_VALUE 0x0003 502#define MIN_MAX_BANK_0__MAX_VALUE 0x000c 503 504#define PERM_SRC_ID_1 0x870 505#define PERM_SRC_ID_1__SRCID 0x00ff 506#define PERM_SRC_ID_1__DIRECT_ACCESS_ACTIVE 0x0800 507#define PERM_SRC_ID_1__WRITE_ACTIVE 0x2000 508#define PERM_SRC_ID_1__READ_ACTIVE 0x4000 509#define PERM_SRC_ID_1__PARTITION_VALID 0x8000 510 511#define MIN_BLK_ADDR_1 0x880 512#define MIN_BLK_ADDR_1__VALUE 0xffff 513 514#define MAX_BLK_ADDR_1 0x890 515#define MAX_BLK_ADDR_1__VALUE 0xffff 516 517#define MIN_MAX_BANK_1 0x8a0 518#define MIN_MAX_BANK_1__MIN_VALUE 0x0003 519#define MIN_MAX_BANK_1__MAX_VALUE 0x000c 520 521#define PERM_SRC_ID_2 0x8b0 522#define PERM_SRC_ID_2__SRCID 0x00ff 523#define PERM_SRC_ID_2__DIRECT_ACCESS_ACTIVE 0x0800 524#define PERM_SRC_ID_2__WRITE_ACTIVE 0x2000 525#define PERM_SRC_ID_2__READ_ACTIVE 0x4000 526#define PERM_SRC_ID_2__PARTITION_VALID 0x8000 527 528#define MIN_BLK_ADDR_2 0x8c0 529#define MIN_BLK_ADDR_2__VALUE 0xffff 530 531#define MAX_BLK_ADDR_2 0x8d0 532#define MAX_BLK_ADDR_2__VALUE 0xffff 533 534#define MIN_MAX_BANK_2 0x8e0 535#define MIN_MAX_BANK_2__MIN_VALUE 0x0003 536#define MIN_MAX_BANK_2__MAX_VALUE 0x000c 537 538#define PERM_SRC_ID_3 0x8f0 539#define PERM_SRC_ID_3__SRCID 0x00ff 540#define PERM_SRC_ID_3__DIRECT_ACCESS_ACTIVE 0x0800 541#define PERM_SRC_ID_3__WRITE_ACTIVE 0x2000 542#define PERM_SRC_ID_3__READ_ACTIVE 0x4000 543#define PERM_SRC_ID_3__PARTITION_VALID 0x8000 544 545#define MIN_BLK_ADDR_3 0x900 546#define MIN_BLK_ADDR_3__VALUE 0xffff 547 548#define MAX_BLK_ADDR_3 0x910 549#define MAX_BLK_ADDR_3__VALUE 0xffff 550 551#define MIN_MAX_BANK_3 0x920 552#define MIN_MAX_BANK_3__MIN_VALUE 0x0003 553#define MIN_MAX_BANK_3__MAX_VALUE 0x000c 554 555#define PERM_SRC_ID_4 0x930 556#define PERM_SRC_ID_4__SRCID 0x00ff 557#define PERM_SRC_ID_4__DIRECT_ACCESS_ACTIVE 0x0800 558#define PERM_SRC_ID_4__WRITE_ACTIVE 0x2000 559#define PERM_SRC_ID_4__READ_ACTIVE 0x4000 560#define PERM_SRC_ID_4__PARTITION_VALID 0x8000 561 562#define MIN_BLK_ADDR_4 0x940 563#define MIN_BLK_ADDR_4__VALUE 0xffff 564 565#define MAX_BLK_ADDR_4 0x950 566#define MAX_BLK_ADDR_4__VALUE 0xffff 567 568#define MIN_MAX_BANK_4 0x960 569#define MIN_MAX_BANK_4__MIN_VALUE 0x0003 570#define MIN_MAX_BANK_4__MAX_VALUE 0x000c 571 572#define PERM_SRC_ID_5 0x970 573#define PERM_SRC_ID_5__SRCID 0x00ff 574#define PERM_SRC_ID_5__DIRECT_ACCESS_ACTIVE 0x0800 575#define PERM_SRC_ID_5__WRITE_ACTIVE 0x2000 576#define PERM_SRC_ID_5__READ_ACTIVE 0x4000 577#define PERM_SRC_ID_5__PARTITION_VALID 0x8000 578 579#define MIN_BLK_ADDR_5 0x980 580#define MIN_BLK_ADDR_5__VALUE 0xffff 581 582#define MAX_BLK_ADDR_5 0x990 583#define MAX_BLK_ADDR_5__VALUE 0xffff 584 585#define MIN_MAX_BANK_5 0x9a0 586#define MIN_MAX_BANK_5__MIN_VALUE 0x0003 587#define MIN_MAX_BANK_5__MAX_VALUE 0x000c 588 589#define PERM_SRC_ID_6 0x9b0 590#define PERM_SRC_ID_6__SRCID 0x00ff 591#define PERM_SRC_ID_6__DIRECT_ACCESS_ACTIVE 0x0800 592#define PERM_SRC_ID_6__WRITE_ACTIVE 0x2000 593#define PERM_SRC_ID_6__READ_ACTIVE 0x4000 594#define PERM_SRC_ID_6__PARTITION_VALID 0x8000 595 596#define MIN_BLK_ADDR_6 0x9c0 597#define MIN_BLK_ADDR_6__VALUE 0xffff 598 599#define MAX_BLK_ADDR_6 0x9d0 600#define MAX_BLK_ADDR_6__VALUE 0xffff 601 602#define MIN_MAX_BANK_6 0x9e0 603#define MIN_MAX_BANK_6__MIN_VALUE 0x0003 604#define MIN_MAX_BANK_6__MAX_VALUE 0x000c 605 606#define PERM_SRC_ID_7 0x9f0 607#define PERM_SRC_ID_7__SRCID 0x00ff 608#define PERM_SRC_ID_7__DIRECT_ACCESS_ACTIVE 0x0800 609#define PERM_SRC_ID_7__WRITE_ACTIVE 0x2000 610#define PERM_SRC_ID_7__READ_ACTIVE 0x4000 611#define PERM_SRC_ID_7__PARTITION_VALID 0x8000 612 613#define MIN_BLK_ADDR_7 0xa00 614#define MIN_BLK_ADDR_7__VALUE 0xffff 615 616#define MAX_BLK_ADDR_7 0xa10 617#define MAX_BLK_ADDR_7__VALUE 0xffff 618 619#define MIN_MAX_BANK_7 0xa20 620#define MIN_MAX_BANK_7__MIN_VALUE 0x0003 621#define MIN_MAX_BANK_7__MAX_VALUE 0x000c 622 623/* ffsdefs.h */ 624#define CLEAR 0 /*use this to clear a field instead of "fail"*/ 625#define SET 1 /*use this to set a field instead of "pass"*/ 626#define FAIL 1 /*failed flag*/ 627#define PASS 0 /*success flag*/ 628#define ERR -1 /*error flag*/ 629 630/* lld.h */ 631#define GOOD_BLOCK 0 632#define DEFECTIVE_BLOCK 1 633#define READ_ERROR 2 634 635#define CLK_X 5 636#define CLK_MULTI 4 637 638/* spectraswconfig.h */ 639#define CMD_DMA 0 640 641#define SPECTRA_PARTITION_ID 0 642/**** Block Table and Reserved Block Parameters *****/ 643#define SPECTRA_START_BLOCK 3 644#define NUM_FREE_BLOCKS_GATE 30 645 646/* KBV - Updated to LNW scratch register address */ 647#define SCRATCH_REG_ADDR CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR 648#define SCRATCH_REG_SIZE 64 649 650#define GLOB_HWCTL_DEFAULT_BLKS 2048 651 652#define SUPPORT_15BITECC 1 653#define SUPPORT_8BITECC 1 654 655#define CUSTOM_CONF_PARAMS 0 656 657#define ONFI_BLOOM_TIME 1 658#define MODE5_WORKAROUND 0 659 660/* lld_nand.h */ 661/* 662 * NAND Flash Controller Device Driver 663 * Copyright (c) 2009, Intel Corporation and its suppliers. 664 * 665 * This program is free software; you can redistribute it and/or modify it 666 * under the terms and conditions of the GNU General Public License, 667 * version 2, as published by the Free Software Foundation. 668 * 669 * This program is distributed in the hope it will be useful, but WITHOUT 670 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 671 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 672 * more details. 673 * 674 * You should have received a copy of the GNU General Public License along with 675 * this program; if not, write to the Free Software Foundation, Inc., 676 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 677 * 678 */ 679 680#ifndef _LLD_NAND_ 681#define _LLD_NAND_ 682 683#define MODE_00 0x00000000 684#define MODE_01 0x04000000 685#define MODE_10 0x08000000 686#define MODE_11 0x0C000000 687 688 689#define DATA_TRANSFER_MODE 0 690#define PROTECTION_PER_BLOCK 1 691#define LOAD_WAIT_COUNT 2 692#define PROGRAM_WAIT_COUNT 3 693#define ERASE_WAIT_COUNT 4 694#define INT_MONITOR_CYCLE_COUNT 5 695#define READ_BUSY_PIN_ENABLED 6 696#define MULTIPLANE_OPERATION_SUPPORT 7 697#define PRE_FETCH_MODE 8 698#define CE_DONT_CARE_SUPPORT 9 699#define COPYBACK_SUPPORT 10 700#define CACHE_WRITE_SUPPORT 11 701#define CACHE_READ_SUPPORT 12 702#define NUM_PAGES_IN_BLOCK 13 703#define ECC_ENABLE_SELECT 14 704#define WRITE_ENABLE_2_READ_ENABLE 15 705#define ADDRESS_2_DATA 16 706#define READ_ENABLE_2_WRITE_ENABLE 17 707#define TWO_ROW_ADDRESS_CYCLES 18 708#define MULTIPLANE_ADDRESS_RESTRICT 19 709#define ACC_CLOCKS 20 710#define READ_WRITE_ENABLE_LOW_COUNT 21 711#define READ_WRITE_ENABLE_HIGH_COUNT 22 712 713#define ECC_SECTOR_SIZE 512 714#define LLD_MAX_FLASH_BANKS 4 715 716#define DENALI_BUF_SIZE (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) 717 718struct nand_buf { 719 int head; 720 int tail; 721 uint8_t buf[DENALI_BUF_SIZE]; 722 dma_addr_t dma_buf; 723}; 724 725#define INTEL_CE4100 1 726#define INTEL_MRST 2 727 728struct denali_nand_info { 729 struct mtd_info mtd; 730 struct nand_chip nand; 731 int flash_bank; /* currently selected chip */ 732 int status; 733 int platform; 734 struct nand_buf buf; 735 struct pci_dev *dev; 736 int total_used_banks; 737 uint32_t block; /* stored for future use */ 738 uint16_t page; 739 void __iomem *flash_reg; /* Mapped io reg base address */ 740 void __iomem *flash_mem; /* Mapped io reg base address */ 741 742 /* elements used by ISR */ 743 struct completion complete; 744 spinlock_t irq_lock; 745 uint32_t irq_status; 746 int irq_debug_array[32]; 747 int idx; 748 749 uint32_t devnum; /* represent how many nands connected */ 750 uint32_t fwblks; /* represent how many blocks FW used */ 751 uint32_t totalblks; 752 uint32_t blksperchip; 753 uint32_t bbtskipbytes; 754}; 755 756#endif /*_LLD_NAND_*/ 757