1/* 2 * davinci_nand.c - NAND Flash Driver for DaVinci family chips 3 * 4 * Copyright �� 2006 Texas Instruments. 5 * 6 * Port to 2.6.23 Copyright �� 2008 by: 7 * Sander Huijsen <Shuijsen@optelecom-nkf.com> 8 * Troy Kisky <troy.kisky@boundarydevices.com> 9 * Dirk Behme <Dirk.Behme@gmail.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 */ 25 26#include <linux/kernel.h> 27#include <linux/init.h> 28#include <linux/module.h> 29#include <linux/platform_device.h> 30#include <linux/err.h> 31#include <linux/clk.h> 32#include <linux/io.h> 33#include <linux/mtd/nand.h> 34#include <linux/mtd/partitions.h> 35#include <linux/slab.h> 36 37#include <mach/nand.h> 38 39#include <asm/mach-types.h> 40 41 42/* 43 * This is a device driver for the NAND flash controller found on the 44 * various DaVinci family chips. It handles up to four SoC chipselects, 45 * and some flavors of secondary chipselect (e.g. based on A12) as used 46 * with multichip packages. 47 * 48 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC 49 * available on chips like the DM355 and OMAP-L137 and needed with the 50 * more error-prone MLC NAND chips. 51 * 52 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY 53 * outputs in a "wire-AND" configuration, with no per-chip signals. 54 */ 55struct davinci_nand_info { 56 struct mtd_info mtd; 57 struct nand_chip chip; 58 struct nand_ecclayout ecclayout; 59 60 struct device *dev; 61 struct clk *clk; 62 bool partitioned; 63 64 bool is_readmode; 65 66 void __iomem *base; 67 void __iomem *vaddr; 68 69 uint32_t ioaddr; 70 uint32_t current_cs; 71 72 uint32_t mask_chipsel; 73 uint32_t mask_ale; 74 uint32_t mask_cle; 75 76 uint32_t core_chipsel; 77}; 78 79static DEFINE_SPINLOCK(davinci_nand_lock); 80static bool ecc4_busy; 81 82#define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd) 83 84 85static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info, 86 int offset) 87{ 88 return __raw_readl(info->base + offset); 89} 90 91static inline void davinci_nand_writel(struct davinci_nand_info *info, 92 int offset, unsigned long value) 93{ 94 __raw_writel(value, info->base + offset); 95} 96 97/*----------------------------------------------------------------------*/ 98 99/* 100 * Access to hardware control lines: ALE, CLE, secondary chipselect. 101 */ 102 103static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, 104 unsigned int ctrl) 105{ 106 struct davinci_nand_info *info = to_davinci_nand(mtd); 107 uint32_t addr = info->current_cs; 108 struct nand_chip *nand = mtd->priv; 109 110 /* Did the control lines change? */ 111 if (ctrl & NAND_CTRL_CHANGE) { 112 if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE) 113 addr |= info->mask_cle; 114 else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE) 115 addr |= info->mask_ale; 116 117 nand->IO_ADDR_W = (void __iomem __force *)addr; 118 } 119 120 if (cmd != NAND_CMD_NONE) 121 iowrite8(cmd, nand->IO_ADDR_W); 122} 123 124static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) 125{ 126 struct davinci_nand_info *info = to_davinci_nand(mtd); 127 uint32_t addr = info->ioaddr; 128 129 /* maybe kick in a second chipselect */ 130 if (chip > 0) 131 addr |= info->mask_chipsel; 132 info->current_cs = addr; 133 134 info->chip.IO_ADDR_W = (void __iomem __force *)addr; 135 info->chip.IO_ADDR_R = info->chip.IO_ADDR_W; 136} 137 138/*----------------------------------------------------------------------*/ 139 140/* 141 * 1-bit hardware ECC ... context maintained for each core chipselect 142 */ 143 144static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd) 145{ 146 struct davinci_nand_info *info = to_davinci_nand(mtd); 147 148 return davinci_nand_readl(info, NANDF1ECC_OFFSET 149 + 4 * info->core_chipsel); 150} 151 152static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode) 153{ 154 struct davinci_nand_info *info; 155 uint32_t nandcfr; 156 unsigned long flags; 157 158 info = to_davinci_nand(mtd); 159 160 /* Reset ECC hardware */ 161 nand_davinci_readecc_1bit(mtd); 162 163 spin_lock_irqsave(&davinci_nand_lock, flags); 164 165 /* Restart ECC hardware */ 166 nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET); 167 nandcfr |= BIT(8 + info->core_chipsel); 168 davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr); 169 170 spin_unlock_irqrestore(&davinci_nand_lock, flags); 171} 172 173/* 174 * Read hardware ECC value and pack into three bytes 175 */ 176static int nand_davinci_calculate_1bit(struct mtd_info *mtd, 177 const u_char *dat, u_char *ecc_code) 178{ 179 unsigned int ecc_val = nand_davinci_readecc_1bit(mtd); 180 unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4); 181 182 /* invert so that erased block ecc is correct */ 183 ecc24 = ~ecc24; 184 ecc_code[0] = (u_char)(ecc24); 185 ecc_code[1] = (u_char)(ecc24 >> 8); 186 ecc_code[2] = (u_char)(ecc24 >> 16); 187 188 return 0; 189} 190 191static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat, 192 u_char *read_ecc, u_char *calc_ecc) 193{ 194 struct nand_chip *chip = mtd->priv; 195 uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) | 196 (read_ecc[2] << 16); 197 uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) | 198 (calc_ecc[2] << 16); 199 uint32_t diff = eccCalc ^ eccNand; 200 201 if (diff) { 202 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) { 203 /* Correctable error */ 204 if ((diff >> (12 + 3)) < chip->ecc.size) { 205 dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7); 206 return 1; 207 } else { 208 return -1; 209 } 210 } else if (!(diff & (diff - 1))) { 211 /* Single bit ECC error in the ECC itself, 212 * nothing to fix */ 213 return 1; 214 } else { 215 /* Uncorrectable error */ 216 return -1; 217 } 218 219 } 220 return 0; 221} 222 223/*----------------------------------------------------------------------*/ 224 225/* 226 * 4-bit hardware ECC ... context maintained over entire AEMIF 227 * 228 * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME 229 * since that forces use of a problematic "infix OOB" layout. 230 * Among other things, it trashes manufacturer bad block markers. 231 * Also, and specific to this hardware, it ECC-protects the "prepad" 232 * in the OOB ... while having ECC protection for parts of OOB would 233 * seem useful, the current MTD stack sometimes wants to update the 234 * OOB without recomputing ECC. 235 */ 236 237static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode) 238{ 239 struct davinci_nand_info *info = to_davinci_nand(mtd); 240 unsigned long flags; 241 u32 val; 242 243 spin_lock_irqsave(&davinci_nand_lock, flags); 244 245 /* Start 4-bit ECC calculation for read/write */ 246 val = davinci_nand_readl(info, NANDFCR_OFFSET); 247 val &= ~(0x03 << 4); 248 val |= (info->core_chipsel << 4) | BIT(12); 249 davinci_nand_writel(info, NANDFCR_OFFSET, val); 250 251 info->is_readmode = (mode == NAND_ECC_READ); 252 253 spin_unlock_irqrestore(&davinci_nand_lock, flags); 254} 255 256/* Read raw ECC code after writing to NAND. */ 257static void 258nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4]) 259{ 260 const u32 mask = 0x03ff03ff; 261 262 code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask; 263 code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask; 264 code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask; 265 code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask; 266} 267 268/* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */ 269static int nand_davinci_calculate_4bit(struct mtd_info *mtd, 270 const u_char *dat, u_char *ecc_code) 271{ 272 struct davinci_nand_info *info = to_davinci_nand(mtd); 273 u32 raw_ecc[4], *p; 274 unsigned i; 275 276 /* After a read, terminate ECC calculation by a dummy read 277 * of some 4-bit ECC register. ECC covers everything that 278 * was read; correct() just uses the hardware state, so 279 * ecc_code is not needed. 280 */ 281 if (info->is_readmode) { 282 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET); 283 return 0; 284 } 285 286 /* Pack eight raw 10-bit ecc values into ten bytes, making 287 * two passes which each convert four values (in upper and 288 * lower halves of two 32-bit words) into five bytes. The 289 * ROM boot loader uses this same packing scheme. 290 */ 291 nand_davinci_readecc_4bit(info, raw_ecc); 292 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) { 293 *ecc_code++ = p[0] & 0xff; 294 *ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc); 295 *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0); 296 *ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0); 297 *ecc_code++ = (p[1] >> 18) & 0xff; 298 } 299 300 return 0; 301} 302 303/* Correct up to 4 bits in data we just read, using state left in the 304 * hardware plus the ecc_code computed when it was first written. 305 */ 306static int nand_davinci_correct_4bit(struct mtd_info *mtd, 307 u_char *data, u_char *ecc_code, u_char *null) 308{ 309 int i; 310 struct davinci_nand_info *info = to_davinci_nand(mtd); 311 unsigned short ecc10[8]; 312 unsigned short *ecc16; 313 u32 syndrome[4]; 314 u32 ecc_state; 315 unsigned num_errors, corrected; 316 unsigned long timeo = jiffies + msecs_to_jiffies(100); 317 318 /* All bytes 0xff? It's an erased page; ignore its ECC. */ 319 for (i = 0; i < 10; i++) { 320 if (ecc_code[i] != 0xff) 321 goto compare; 322 } 323 return 0; 324 325compare: 326 /* Unpack ten bytes into eight 10 bit values. We know we're 327 * little-endian, and use type punning for less shifting/masking. 328 */ 329 if (WARN_ON(0x01 & (unsigned) ecc_code)) 330 return -EINVAL; 331 ecc16 = (unsigned short *)ecc_code; 332 333 ecc10[0] = (ecc16[0] >> 0) & 0x3ff; 334 ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0); 335 ecc10[2] = (ecc16[1] >> 4) & 0x3ff; 336 ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc); 337 ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300); 338 ecc10[5] = (ecc16[3] >> 2) & 0x3ff; 339 ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0); 340 ecc10[7] = (ecc16[4] >> 6) & 0x3ff; 341 342 /* Tell ECC controller about the expected ECC codes. */ 343 for (i = 7; i >= 0; i--) 344 davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]); 345 346 /* Allow time for syndrome calculation ... then read it. 347 * A syndrome of all zeroes 0 means no detected errors. 348 */ 349 davinci_nand_readl(info, NANDFSR_OFFSET); 350 nand_davinci_readecc_4bit(info, syndrome); 351 if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3])) 352 return 0; 353 354 /* 355 * Clear any previous address calculation by doing a dummy read of an 356 * error address register. 357 */ 358 davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET); 359 360 /* Start address calculation, and wait for it to complete. 361 * We _could_ start reading more data while this is working, 362 * to speed up the overall page read. 363 */ 364 davinci_nand_writel(info, NANDFCR_OFFSET, 365 davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13)); 366 367 /* 368 * ECC_STATE field reads 0x3 (Error correction complete) immediately 369 * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately 370 * begin trying to poll for the state, you may fall right out of your 371 * loop without any of the correction calculations having taken place. 372 * The recommendation from the hardware team is to wait till ECC_STATE 373 * reads less than 4, which means ECC HW has entered correction state. 374 */ 375 do { 376 ecc_state = (davinci_nand_readl(info, 377 NANDFSR_OFFSET) >> 8) & 0x0f; 378 cpu_relax(); 379 } while ((ecc_state < 4) && time_before(jiffies, timeo)); 380 381 for (;;) { 382 u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET); 383 384 switch ((fsr >> 8) & 0x0f) { 385 case 0: /* no error, should not happen */ 386 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET); 387 return 0; 388 case 1: /* five or more errors detected */ 389 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET); 390 return -EIO; 391 case 2: /* error addresses computed */ 392 case 3: 393 num_errors = 1 + ((fsr >> 16) & 0x03); 394 goto correct; 395 default: /* still working on it */ 396 cpu_relax(); 397 continue; 398 } 399 } 400 401correct: 402 /* correct each error */ 403 for (i = 0, corrected = 0; i < num_errors; i++) { 404 int error_address, error_value; 405 406 if (i > 1) { 407 error_address = davinci_nand_readl(info, 408 NAND_ERR_ADD2_OFFSET); 409 error_value = davinci_nand_readl(info, 410 NAND_ERR_ERRVAL2_OFFSET); 411 } else { 412 error_address = davinci_nand_readl(info, 413 NAND_ERR_ADD1_OFFSET); 414 error_value = davinci_nand_readl(info, 415 NAND_ERR_ERRVAL1_OFFSET); 416 } 417 418 if (i & 1) { 419 error_address >>= 16; 420 error_value >>= 16; 421 } 422 error_address &= 0x3ff; 423 error_address = (512 + 7) - error_address; 424 425 if (error_address < 512) { 426 data[error_address] ^= error_value; 427 corrected++; 428 } 429 } 430 431 return corrected; 432} 433 434/*----------------------------------------------------------------------*/ 435 436/* 437 * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's 438 * how these chips are normally wired. This translates to both 8 and 16 439 * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4). 440 * 441 * For now we assume that configuration, or any other one which ignores 442 * the two LSBs for NAND access ... so we can issue 32-bit reads/writes 443 * and have that transparently morphed into multiple NAND operations. 444 */ 445static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 446{ 447 struct nand_chip *chip = mtd->priv; 448 449 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0) 450 ioread32_rep(chip->IO_ADDR_R, buf, len >> 2); 451 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0) 452 ioread16_rep(chip->IO_ADDR_R, buf, len >> 1); 453 else 454 ioread8_rep(chip->IO_ADDR_R, buf, len); 455} 456 457static void nand_davinci_write_buf(struct mtd_info *mtd, 458 const uint8_t *buf, int len) 459{ 460 struct nand_chip *chip = mtd->priv; 461 462 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0) 463 iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2); 464 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0) 465 iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1); 466 else 467 iowrite8_rep(chip->IO_ADDR_R, buf, len); 468} 469 470/* 471 * Check hardware register for wait status. Returns 1 if device is ready, 472 * 0 if it is still busy. 473 */ 474static int nand_davinci_dev_ready(struct mtd_info *mtd) 475{ 476 struct davinci_nand_info *info = to_davinci_nand(mtd); 477 478 return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0); 479} 480 481static void __init nand_dm6446evm_flash_init(struct davinci_nand_info *info) 482{ 483 uint32_t regval, a1cr; 484 485 /* 486 * NAND FLASH timings @ PLL1 == 459 MHz 487 * - AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz 488 * - AEMIF.CLK period = 1/76.5 MHz = 13.1 ns 489 */ 490 regval = 0 491 | (0 << 31) /* selectStrobe */ 492 | (0 << 30) /* extWait (never with NAND) */ 493 | (1 << 26) /* writeSetup 10 ns */ 494 | (3 << 20) /* writeStrobe 40 ns */ 495 | (1 << 17) /* writeHold 10 ns */ 496 | (0 << 13) /* readSetup 10 ns */ 497 | (3 << 7) /* readStrobe 60 ns */ 498 | (0 << 4) /* readHold 10 ns */ 499 | (3 << 2) /* turnAround ?? ns */ 500 | (0 << 0) /* asyncSize 8-bit bus */ 501 ; 502 a1cr = davinci_nand_readl(info, A1CR_OFFSET); 503 if (a1cr != regval) { 504 dev_dbg(info->dev, "Warning: NAND config: Set A1CR " \ 505 "reg to 0x%08x, was 0x%08x, should be done by " \ 506 "bootloader.\n", regval, a1cr); 507 davinci_nand_writel(info, A1CR_OFFSET, regval); 508 } 509} 510 511/*----------------------------------------------------------------------*/ 512 513/* An ECC layout for using 4-bit ECC with small-page flash, storing 514 * ten ECC bytes plus the manufacturer's bad block marker byte, and 515 * and not overlapping the default BBT markers. 516 */ 517static struct nand_ecclayout hwecc4_small __initconst = { 518 .eccbytes = 10, 519 .eccpos = { 0, 1, 2, 3, 4, 520 /* offset 5 holds the badblock marker */ 521 6, 7, 522 13, 14, 15, }, 523 .oobfree = { 524 {.offset = 8, .length = 5, }, 525 {.offset = 16, }, 526 }, 527}; 528 529/* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash, 530 * storing ten ECC bytes plus the manufacturer's bad block marker byte, 531 * and not overlapping the default BBT markers. 532 */ 533static struct nand_ecclayout hwecc4_2048 __initconst = { 534 .eccbytes = 40, 535 .eccpos = { 536 /* at the end of spare sector */ 537 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 538 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 539 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 540 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 541 }, 542 .oobfree = { 543 /* 2 bytes at offset 0 hold manufacturer badblock markers */ 544 {.offset = 2, .length = 22, }, 545 /* 5 bytes at offset 8 hold BBT markers */ 546 /* 8 bytes at offset 16 hold JFFS2 clean markers */ 547 }, 548}; 549 550static int __init nand_davinci_probe(struct platform_device *pdev) 551{ 552 struct davinci_nand_pdata *pdata = pdev->dev.platform_data; 553 struct davinci_nand_info *info; 554 struct resource *res1; 555 struct resource *res2; 556 void __iomem *vaddr; 557 void __iomem *base; 558 int ret; 559 uint32_t val; 560 nand_ecc_modes_t ecc_mode; 561 562 /* insist on board-specific configuration */ 563 if (!pdata) 564 return -ENODEV; 565 566 /* which external chipselect will we be managing? */ 567 if (pdev->id < 0 || pdev->id > 3) 568 return -ENODEV; 569 570 info = kzalloc(sizeof(*info), GFP_KERNEL); 571 if (!info) { 572 dev_err(&pdev->dev, "unable to allocate memory\n"); 573 ret = -ENOMEM; 574 goto err_nomem; 575 } 576 577 platform_set_drvdata(pdev, info); 578 579 res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0); 580 res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); 581 if (!res1 || !res2) { 582 dev_err(&pdev->dev, "resource missing\n"); 583 ret = -EINVAL; 584 goto err_nomem; 585 } 586 587 vaddr = ioremap(res1->start, resource_size(res1)); 588 base = ioremap(res2->start, resource_size(res2)); 589 if (!vaddr || !base) { 590 dev_err(&pdev->dev, "ioremap failed\n"); 591 ret = -EINVAL; 592 goto err_ioremap; 593 } 594 595 info->dev = &pdev->dev; 596 info->base = base; 597 info->vaddr = vaddr; 598 599 info->mtd.priv = &info->chip; 600 info->mtd.name = dev_name(&pdev->dev); 601 info->mtd.owner = THIS_MODULE; 602 603 info->mtd.dev.parent = &pdev->dev; 604 605 info->chip.IO_ADDR_R = vaddr; 606 info->chip.IO_ADDR_W = vaddr; 607 info->chip.chip_delay = 0; 608 info->chip.select_chip = nand_davinci_select_chip; 609 610 /* options such as NAND_USE_FLASH_BBT or 16-bit widths */ 611 info->chip.options = pdata->options; 612 info->chip.bbt_td = pdata->bbt_td; 613 info->chip.bbt_md = pdata->bbt_md; 614 615 info->ioaddr = (uint32_t __force) vaddr; 616 617 info->current_cs = info->ioaddr; 618 info->core_chipsel = pdev->id; 619 info->mask_chipsel = pdata->mask_chipsel; 620 621 /* use nandboot-capable ALE/CLE masks by default */ 622 info->mask_ale = pdata->mask_ale ? : MASK_ALE; 623 info->mask_cle = pdata->mask_cle ? : MASK_CLE; 624 625 /* Set address of hardware control function */ 626 info->chip.cmd_ctrl = nand_davinci_hwcontrol; 627 info->chip.dev_ready = nand_davinci_dev_ready; 628 629 /* Speed up buffer I/O */ 630 info->chip.read_buf = nand_davinci_read_buf; 631 info->chip.write_buf = nand_davinci_write_buf; 632 633 /* Use board-specific ECC config */ 634 ecc_mode = pdata->ecc_mode; 635 636 ret = -EINVAL; 637 switch (ecc_mode) { 638 case NAND_ECC_NONE: 639 case NAND_ECC_SOFT: 640 pdata->ecc_bits = 0; 641 break; 642 case NAND_ECC_HW: 643 if (pdata->ecc_bits == 4) { 644 /* No sanity checks: CPUs must support this, 645 * and the chips may not use NAND_BUSWIDTH_16. 646 */ 647 648 /* No sharing 4-bit hardware between chipselects yet */ 649 spin_lock_irq(&davinci_nand_lock); 650 if (ecc4_busy) 651 ret = -EBUSY; 652 else 653 ecc4_busy = true; 654 spin_unlock_irq(&davinci_nand_lock); 655 656 if (ret == -EBUSY) 657 goto err_ecc; 658 659 info->chip.ecc.calculate = nand_davinci_calculate_4bit; 660 info->chip.ecc.correct = nand_davinci_correct_4bit; 661 info->chip.ecc.hwctl = nand_davinci_hwctl_4bit; 662 info->chip.ecc.bytes = 10; 663 } else { 664 info->chip.ecc.calculate = nand_davinci_calculate_1bit; 665 info->chip.ecc.correct = nand_davinci_correct_1bit; 666 info->chip.ecc.hwctl = nand_davinci_hwctl_1bit; 667 info->chip.ecc.bytes = 3; 668 } 669 info->chip.ecc.size = 512; 670 break; 671 default: 672 ret = -EINVAL; 673 goto err_ecc; 674 } 675 info->chip.ecc.mode = ecc_mode; 676 677 info->clk = clk_get(&pdev->dev, "aemif"); 678 if (IS_ERR(info->clk)) { 679 ret = PTR_ERR(info->clk); 680 dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret); 681 goto err_clk; 682 } 683 684 ret = clk_enable(info->clk); 685 if (ret < 0) { 686 dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n", 687 ret); 688 goto err_clk_enable; 689 } 690 691 /* EMIF timings should normally be set by the boot loader, 692 * especially after boot-from-NAND. The *only* reason to 693 * have this special casing for the DM6446 EVM is to work 694 * with boot-from-NOR ... with CS0 manually re-jumpered 695 * (after startup) so it addresses the NAND flash, not NOR. 696 * Even for dev boards, that's unusually rude... 697 */ 698 if (machine_is_davinci_evm()) 699 nand_dm6446evm_flash_init(info); 700 701 spin_lock_irq(&davinci_nand_lock); 702 703 /* put CSxNAND into NAND mode */ 704 val = davinci_nand_readl(info, NANDFCR_OFFSET); 705 val |= BIT(info->core_chipsel); 706 davinci_nand_writel(info, NANDFCR_OFFSET, val); 707 708 spin_unlock_irq(&davinci_nand_lock); 709 710 /* Scan to find existence of the device(s) */ 711 ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1, NULL); 712 if (ret < 0) { 713 dev_dbg(&pdev->dev, "no NAND chip(s) found\n"); 714 goto err_scan; 715 } 716 717 /* Update ECC layout if needed ... for 1-bit HW ECC, the default 718 * is OK, but it allocates 6 bytes when only 3 are needed (for 719 * each 512 bytes). For the 4-bit HW ECC, that default is not 720 * usable: 10 bytes are needed, not 6. 721 */ 722 if (pdata->ecc_bits == 4) { 723 int chunks = info->mtd.writesize / 512; 724 725 if (!chunks || info->mtd.oobsize < 16) { 726 dev_dbg(&pdev->dev, "too small\n"); 727 ret = -EINVAL; 728 goto err_scan; 729 } 730 731 /* For small page chips, preserve the manufacturer's 732 * badblock marking data ... and make sure a flash BBT 733 * table marker fits in the free bytes. 734 */ 735 if (chunks == 1) { 736 info->ecclayout = hwecc4_small; 737 info->ecclayout.oobfree[1].length = 738 info->mtd.oobsize - 16; 739 goto syndrome_done; 740 } 741 if (chunks == 4) { 742 info->ecclayout = hwecc4_2048; 743 info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST; 744 goto syndrome_done; 745 } 746 747 /* 4KiB page chips are not yet supported. The eccpos from 748 * nand_ecclayout cannot hold 80 bytes and change to eccpos[] 749 * breaks userspace ioctl interface with mtd-utils. Once we 750 * resolve this issue, NAND_ECC_HW_OOB_FIRST mode can be used 751 * for the 4KiB page chips. 752 */ 753 dev_warn(&pdev->dev, "no 4-bit ECC support yet " 754 "for 4KiB-page NAND\n"); 755 ret = -EIO; 756 goto err_scan; 757 758syndrome_done: 759 info->chip.ecc.layout = &info->ecclayout; 760 } 761 762 ret = nand_scan_tail(&info->mtd); 763 if (ret < 0) 764 goto err_scan; 765 766 if (mtd_has_partitions()) { 767 struct mtd_partition *mtd_parts = NULL; 768 int mtd_parts_nb = 0; 769 770 if (mtd_has_cmdlinepart()) { 771 static const char *probes[] __initconst = 772 { "cmdlinepart", NULL }; 773 774 mtd_parts_nb = parse_mtd_partitions(&info->mtd, probes, 775 &mtd_parts, 0); 776 } 777 778 if (mtd_parts_nb <= 0) { 779 mtd_parts = pdata->parts; 780 mtd_parts_nb = pdata->nr_parts; 781 } 782 783 /* Register any partitions */ 784 if (mtd_parts_nb > 0) { 785 ret = add_mtd_partitions(&info->mtd, 786 mtd_parts, mtd_parts_nb); 787 if (ret == 0) 788 info->partitioned = true; 789 } 790 791 } else if (pdata->nr_parts) { 792 dev_warn(&pdev->dev, "ignoring %d default partitions on %s\n", 793 pdata->nr_parts, info->mtd.name); 794 } 795 796 /* If there's no partition info, just package the whole chip 797 * as a single MTD device. 798 */ 799 if (!info->partitioned) 800 ret = add_mtd_device(&info->mtd) ? -ENODEV : 0; 801 802 if (ret < 0) 803 goto err_scan; 804 805 val = davinci_nand_readl(info, NRCSR_OFFSET); 806 dev_info(&pdev->dev, "controller rev. %d.%d\n", 807 (val >> 8) & 0xff, val & 0xff); 808 809 return 0; 810 811err_scan: 812 clk_disable(info->clk); 813 814err_clk_enable: 815 clk_put(info->clk); 816 817 spin_lock_irq(&davinci_nand_lock); 818 if (ecc_mode == NAND_ECC_HW_SYNDROME) 819 ecc4_busy = false; 820 spin_unlock_irq(&davinci_nand_lock); 821 822err_ecc: 823err_clk: 824err_ioremap: 825 if (base) 826 iounmap(base); 827 if (vaddr) 828 iounmap(vaddr); 829 830err_nomem: 831 kfree(info); 832 return ret; 833} 834 835static int __exit nand_davinci_remove(struct platform_device *pdev) 836{ 837 struct davinci_nand_info *info = platform_get_drvdata(pdev); 838 int status; 839 840 if (mtd_has_partitions() && info->partitioned) 841 status = del_mtd_partitions(&info->mtd); 842 else 843 status = del_mtd_device(&info->mtd); 844 845 spin_lock_irq(&davinci_nand_lock); 846 if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME) 847 ecc4_busy = false; 848 spin_unlock_irq(&davinci_nand_lock); 849 850 iounmap(info->base); 851 iounmap(info->vaddr); 852 853 nand_release(&info->mtd); 854 855 clk_disable(info->clk); 856 clk_put(info->clk); 857 858 kfree(info); 859 860 return 0; 861} 862 863static struct platform_driver nand_davinci_driver = { 864 .remove = __exit_p(nand_davinci_remove), 865 .driver = { 866 .name = "davinci_nand", 867 }, 868}; 869MODULE_ALIAS("platform:davinci_nand"); 870 871static int __init nand_davinci_init(void) 872{ 873 return platform_driver_probe(&nand_davinci_driver, nand_davinci_probe); 874} 875module_init(nand_davinci_init); 876 877static void __exit nand_davinci_exit(void) 878{ 879 platform_driver_unregister(&nand_davinci_driver); 880} 881module_exit(nand_davinci_exit); 882 883MODULE_LICENSE("GPL"); 884MODULE_AUTHOR("Texas Instruments"); 885MODULE_DESCRIPTION("Davinci NAND flash driver"); 886