1/* 2 * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10#define MMCIPOWER 0x000 11#define MCI_PWR_OFF 0x00 12#define MCI_PWR_UP 0x02 13#define MCI_PWR_ON 0x03 14#define MCI_DATA2DIREN (1 << 2) 15#define MCI_CMDDIREN (1 << 3) 16#define MCI_DATA0DIREN (1 << 4) 17#define MCI_DATA31DIREN (1 << 5) 18#define MCI_OD (1 << 6) 19#define MCI_ROD (1 << 7) 20/* The ST Micro version does not have ROD */ 21#define MCI_FBCLKEN (1 << 7) 22#define MCI_DATA74DIREN (1 << 8) 23 24#define MMCICLOCK 0x004 25#define MCI_CLK_ENABLE (1 << 8) 26#define MCI_CLK_PWRSAVE (1 << 9) 27#define MCI_CLK_BYPASS (1 << 10) 28#define MCI_4BIT_BUS (1 << 11) 29/* 8bit wide buses supported in ST Micro versions */ 30#define MCI_ST_8BIT_BUS (1 << 12) 31 32#define MMCIARGUMENT 0x008 33#define MMCICOMMAND 0x00c 34#define MCI_CPSM_RESPONSE (1 << 6) 35#define MCI_CPSM_LONGRSP (1 << 7) 36#define MCI_CPSM_INTERRUPT (1 << 8) 37#define MCI_CPSM_PENDING (1 << 9) 38#define MCI_CPSM_ENABLE (1 << 10) 39#define MCI_SDIO_SUSP (1 << 11) 40#define MCI_ENCMD_COMPL (1 << 12) 41#define MCI_NIEN (1 << 13) 42#define MCI_CE_ATACMD (1 << 14) 43 44#define MMCIRESPCMD 0x010 45#define MMCIRESPONSE0 0x014 46#define MMCIRESPONSE1 0x018 47#define MMCIRESPONSE2 0x01c 48#define MMCIRESPONSE3 0x020 49#define MMCIDATATIMER 0x024 50#define MMCIDATALENGTH 0x028 51#define MMCIDATACTRL 0x02c 52#define MCI_DPSM_ENABLE (1 << 0) 53#define MCI_DPSM_DIRECTION (1 << 1) 54#define MCI_DPSM_MODE (1 << 2) 55#define MCI_DPSM_DMAENABLE (1 << 3) 56#define MCI_DPSM_BLOCKSIZE (1 << 4) 57#define MCI_DPSM_RWSTART (1 << 8) 58#define MCI_DPSM_RWSTOP (1 << 9) 59#define MCI_DPSM_RWMOD (1 << 10) 60#define MCI_DPSM_SDIOEN (1 << 11) 61 62#define MMCIDATACNT 0x030 63#define MMCISTATUS 0x034 64#define MCI_CMDCRCFAIL (1 << 0) 65#define MCI_DATACRCFAIL (1 << 1) 66#define MCI_CMDTIMEOUT (1 << 2) 67#define MCI_DATATIMEOUT (1 << 3) 68#define MCI_TXUNDERRUN (1 << 4) 69#define MCI_RXOVERRUN (1 << 5) 70#define MCI_CMDRESPEND (1 << 6) 71#define MCI_CMDSENT (1 << 7) 72#define MCI_DATAEND (1 << 8) 73#define MCI_DATABLOCKEND (1 << 10) 74#define MCI_CMDACTIVE (1 << 11) 75#define MCI_TXACTIVE (1 << 12) 76#define MCI_RXACTIVE (1 << 13) 77#define MCI_TXFIFOHALFEMPTY (1 << 14) 78#define MCI_RXFIFOHALFFULL (1 << 15) 79#define MCI_TXFIFOFULL (1 << 16) 80#define MCI_RXFIFOFULL (1 << 17) 81#define MCI_TXFIFOEMPTY (1 << 18) 82#define MCI_RXFIFOEMPTY (1 << 19) 83#define MCI_TXDATAAVLBL (1 << 20) 84#define MCI_RXDATAAVLBL (1 << 21) 85#define MCI_SDIOIT (1 << 22) 86#define MCI_CEATAEND (1 << 23) 87 88#define MMCICLEAR 0x038 89#define MCI_CMDCRCFAILCLR (1 << 0) 90#define MCI_DATACRCFAILCLR (1 << 1) 91#define MCI_CMDTIMEOUTCLR (1 << 2) 92#define MCI_DATATIMEOUTCLR (1 << 3) 93#define MCI_TXUNDERRUNCLR (1 << 4) 94#define MCI_RXOVERRUNCLR (1 << 5) 95#define MCI_CMDRESPENDCLR (1 << 6) 96#define MCI_CMDSENTCLR (1 << 7) 97#define MCI_DATAENDCLR (1 << 8) 98#define MCI_DATABLOCKENDCLR (1 << 10) 99#define MCI_SDIOITC (1 << 22) 100#define MCI_CEATAENDC (1 << 23) 101 102#define MMCIMASK0 0x03c 103#define MCI_CMDCRCFAILMASK (1 << 0) 104#define MCI_DATACRCFAILMASK (1 << 1) 105#define MCI_CMDTIMEOUTMASK (1 << 2) 106#define MCI_DATATIMEOUTMASK (1 << 3) 107#define MCI_TXUNDERRUNMASK (1 << 4) 108#define MCI_RXOVERRUNMASK (1 << 5) 109#define MCI_CMDRESPENDMASK (1 << 6) 110#define MCI_CMDSENTMASK (1 << 7) 111#define MCI_DATAENDMASK (1 << 8) 112#define MCI_DATABLOCKENDMASK (1 << 10) 113#define MCI_CMDACTIVEMASK (1 << 11) 114#define MCI_TXACTIVEMASK (1 << 12) 115#define MCI_RXACTIVEMASK (1 << 13) 116#define MCI_TXFIFOHALFEMPTYMASK (1 << 14) 117#define MCI_RXFIFOHALFFULLMASK (1 << 15) 118#define MCI_TXFIFOFULLMASK (1 << 16) 119#define MCI_RXFIFOFULLMASK (1 << 17) 120#define MCI_TXFIFOEMPTYMASK (1 << 18) 121#define MCI_RXFIFOEMPTYMASK (1 << 19) 122#define MCI_TXDATAAVLBLMASK (1 << 20) 123#define MCI_RXDATAAVLBLMASK (1 << 21) 124#define MCI_SDIOITMASK (1 << 22) 125#define MCI_CEATAENDMASK (1 << 23) 126 127#define MMCIMASK1 0x040 128#define MMCIFIFOCNT 0x048 129#define MMCIFIFO 0x080 /* to 0x0bc */ 130 131#define MCI_IRQENABLE \ 132 (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ 133 MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ 134 MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK) 135 136/* 137 * The size of the FIFO in bytes. 138 */ 139#define MCI_FIFOSIZE (16*4) 140 141#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2) 142 143#define NR_SG 16 144 145struct clk; 146struct variant_data; 147 148struct mmci_host { 149 void __iomem *base; 150 struct mmc_request *mrq; 151 struct mmc_command *cmd; 152 struct mmc_data *data; 153 struct mmc_host *mmc; 154 struct clk *clk; 155 int gpio_cd; 156 int gpio_wp; 157 158 unsigned int data_xfered; 159 160 spinlock_t lock; 161 162 unsigned int mclk; 163 unsigned int cclk; 164 u32 pwr; 165 struct mmci_platform_data *plat; 166 struct variant_data *variant; 167 168 u8 hw_designer; 169 u8 hw_revision:4; 170 171 struct timer_list timer; 172 unsigned int oldstat; 173 174 /* pio stuff */ 175 struct sg_mapping_iter sg_miter; 176 unsigned int size; 177 struct regulator *vcc; 178}; 179