1/* 2 * V4L2 Driver for i.MX27/i.MX25 camera host 3 * 4 * Copyright (C) 2008, Sascha Hauer, Pengutronix 5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/init.h> 14#include <linux/module.h> 15#include <linux/io.h> 16#include <linux/delay.h> 17#include <linux/slab.h> 18#include <linux/dma-mapping.h> 19#include <linux/errno.h> 20#include <linux/fs.h> 21#include <linux/interrupt.h> 22#include <linux/kernel.h> 23#include <linux/mm.h> 24#include <linux/moduleparam.h> 25#include <linux/time.h> 26#include <linux/version.h> 27#include <linux/device.h> 28#include <linux/platform_device.h> 29#include <linux/mutex.h> 30#include <linux/clk.h> 31 32#include <media/v4l2-common.h> 33#include <media/v4l2-dev.h> 34#include <media/videobuf-dma-contig.h> 35#include <media/soc_camera.h> 36#include <media/soc_mediabus.h> 37 38#include <linux/videodev2.h> 39 40#include <mach/mx2_cam.h> 41#ifdef CONFIG_MACH_MX27 42#include <mach/dma-mx1-mx2.h> 43#endif 44#include <mach/hardware.h> 45 46#include <asm/dma.h> 47 48#define MX2_CAM_DRV_NAME "mx2-camera" 49#define MX2_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) 50#define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera" 51 52/* reset values */ 53#define CSICR1_RESET_VAL 0x40000800 54#define CSICR2_RESET_VAL 0x0 55#define CSICR3_RESET_VAL 0x0 56 57/* csi control reg 1 */ 58#define CSICR1_SWAP16_EN (1 << 31) 59#define CSICR1_EXT_VSYNC (1 << 30) 60#define CSICR1_EOF_INTEN (1 << 29) 61#define CSICR1_PRP_IF_EN (1 << 28) 62#define CSICR1_CCIR_MODE (1 << 27) 63#define CSICR1_COF_INTEN (1 << 26) 64#define CSICR1_SF_OR_INTEN (1 << 25) 65#define CSICR1_RF_OR_INTEN (1 << 24) 66#define CSICR1_STATFF_LEVEL (3 << 22) 67#define CSICR1_STATFF_INTEN (1 << 21) 68#define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */ 69#define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */ 70#define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */ 71#define CSICR1_RXFF_INTEN (1 << 18) 72#define CSICR1_SOF_POL (1 << 17) 73#define CSICR1_SOF_INTEN (1 << 16) 74#define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12) 75#define CSICR1_HSYNC_POL (1 << 11) 76#define CSICR1_CCIR_EN (1 << 10) 77#define CSICR1_MCLKEN (1 << 9) 78#define CSICR1_FCC (1 << 8) 79#define CSICR1_PACK_DIR (1 << 7) 80#define CSICR1_CLR_STATFIFO (1 << 6) 81#define CSICR1_CLR_RXFIFO (1 << 5) 82#define CSICR1_GCLK_MODE (1 << 4) 83#define CSICR1_INV_DATA (1 << 3) 84#define CSICR1_INV_PCLK (1 << 2) 85#define CSICR1_REDGE (1 << 1) 86 87#define SHIFT_STATFF_LEVEL 22 88#define SHIFT_RXFF_LEVEL 19 89#define SHIFT_MCLKDIV 12 90 91/* control reg 3 */ 92#define CSICR3_FRMCNT (0xFFFF << 16) 93#define CSICR3_FRMCNT_RST (1 << 15) 94#define CSICR3_DMA_REFLASH_RFF (1 << 14) 95#define CSICR3_DMA_REFLASH_SFF (1 << 13) 96#define CSICR3_DMA_REQ_EN_RFF (1 << 12) 97#define CSICR3_DMA_REQ_EN_SFF (1 << 11) 98#define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */ 99#define CSICR3_CSI_SUP (1 << 3) 100#define CSICR3_ZERO_PACK_EN (1 << 2) 101#define CSICR3_ECC_INT_EN (1 << 1) 102#define CSICR3_ECC_AUTO_EN (1 << 0) 103 104#define SHIFT_FRMCNT 16 105 106/* csi status reg */ 107#define CSISR_SFF_OR_INT (1 << 25) 108#define CSISR_RFF_OR_INT (1 << 24) 109#define CSISR_STATFF_INT (1 << 21) 110#define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */ 111#define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */ 112#define CSISR_RXFF_INT (1 << 18) 113#define CSISR_EOF_INT (1 << 17) 114#define CSISR_SOF_INT (1 << 16) 115#define CSISR_F2_INT (1 << 15) 116#define CSISR_F1_INT (1 << 14) 117#define CSISR_COF_INT (1 << 13) 118#define CSISR_ECC_INT (1 << 1) 119#define CSISR_DRDY (1 << 0) 120 121#define CSICR1 0x00 122#define CSICR2 0x04 123#define CSISR (cpu_is_mx27() ? 0x08 : 0x18) 124#define CSISTATFIFO 0x0c 125#define CSIRFIFO 0x10 126#define CSIRXCNT 0x14 127#define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08) 128#define CSIDMASA_STATFIFO 0x20 129#define CSIDMATA_STATFIFO 0x24 130#define CSIDMASA_FB1 0x28 131#define CSIDMASA_FB2 0x2c 132#define CSIFBUF_PARA 0x30 133#define CSIIMAG_PARA 0x34 134 135/* EMMA PrP */ 136#define PRP_CNTL 0x00 137#define PRP_INTR_CNTL 0x04 138#define PRP_INTRSTATUS 0x08 139#define PRP_SOURCE_Y_PTR 0x0c 140#define PRP_SOURCE_CB_PTR 0x10 141#define PRP_SOURCE_CR_PTR 0x14 142#define PRP_DEST_RGB1_PTR 0x18 143#define PRP_DEST_RGB2_PTR 0x1c 144#define PRP_DEST_Y_PTR 0x20 145#define PRP_DEST_CB_PTR 0x24 146#define PRP_DEST_CR_PTR 0x28 147#define PRP_SRC_FRAME_SIZE 0x2c 148#define PRP_DEST_CH1_LINE_STRIDE 0x30 149#define PRP_SRC_PIXEL_FORMAT_CNTL 0x34 150#define PRP_CH1_PIXEL_FORMAT_CNTL 0x38 151#define PRP_CH1_OUT_IMAGE_SIZE 0x3c 152#define PRP_CH2_OUT_IMAGE_SIZE 0x40 153#define PRP_SRC_LINE_STRIDE 0x44 154#define PRP_CSC_COEF_012 0x48 155#define PRP_CSC_COEF_345 0x4c 156#define PRP_CSC_COEF_678 0x50 157#define PRP_CH1_RZ_HORI_COEF1 0x54 158#define PRP_CH1_RZ_HORI_COEF2 0x58 159#define PRP_CH1_RZ_HORI_VALID 0x5c 160#define PRP_CH1_RZ_VERT_COEF1 0x60 161#define PRP_CH1_RZ_VERT_COEF2 0x64 162#define PRP_CH1_RZ_VERT_VALID 0x68 163#define PRP_CH2_RZ_HORI_COEF1 0x6c 164#define PRP_CH2_RZ_HORI_COEF2 0x70 165#define PRP_CH2_RZ_HORI_VALID 0x74 166#define PRP_CH2_RZ_VERT_COEF1 0x78 167#define PRP_CH2_RZ_VERT_COEF2 0x7c 168#define PRP_CH2_RZ_VERT_VALID 0x80 169 170#define PRP_CNTL_CH1EN (1 << 0) 171#define PRP_CNTL_CH2EN (1 << 1) 172#define PRP_CNTL_CSIEN (1 << 2) 173#define PRP_CNTL_DATA_IN_YUV420 (0 << 3) 174#define PRP_CNTL_DATA_IN_YUV422 (1 << 3) 175#define PRP_CNTL_DATA_IN_RGB16 (2 << 3) 176#define PRP_CNTL_DATA_IN_RGB32 (3 << 3) 177#define PRP_CNTL_CH1_OUT_RGB8 (0 << 5) 178#define PRP_CNTL_CH1_OUT_RGB16 (1 << 5) 179#define PRP_CNTL_CH1_OUT_RGB32 (2 << 5) 180#define PRP_CNTL_CH1_OUT_YUV422 (3 << 5) 181#define PRP_CNTL_CH2_OUT_YUV420 (0 << 7) 182#define PRP_CNTL_CH2_OUT_YUV422 (1 << 7) 183#define PRP_CNTL_CH2_OUT_YUV444 (2 << 7) 184#define PRP_CNTL_CH1_LEN (1 << 9) 185#define PRP_CNTL_CH2_LEN (1 << 10) 186#define PRP_CNTL_SKIP_FRAME (1 << 11) 187#define PRP_CNTL_SWRST (1 << 12) 188#define PRP_CNTL_CLKEN (1 << 13) 189#define PRP_CNTL_WEN (1 << 14) 190#define PRP_CNTL_CH1BYP (1 << 15) 191#define PRP_CNTL_IN_TSKIP(x) ((x) << 16) 192#define PRP_CNTL_CH1_TSKIP(x) ((x) << 19) 193#define PRP_CNTL_CH2_TSKIP(x) ((x) << 22) 194#define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25) 195#define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27) 196#define PRP_CNTL_CH2B1EN (1 << 29) 197#define PRP_CNTL_CH2B2EN (1 << 30) 198#define PRP_CNTL_CH2FEN (1 << 31) 199 200/* IRQ Enable and status register */ 201#define PRP_INTR_RDERR (1 << 0) 202#define PRP_INTR_CH1WERR (1 << 1) 203#define PRP_INTR_CH2WERR (1 << 2) 204#define PRP_INTR_CH1FC (1 << 3) 205#define PRP_INTR_CH2FC (1 << 5) 206#define PRP_INTR_LBOVF (1 << 7) 207#define PRP_INTR_CH2OVF (1 << 8) 208 209#define mx27_camera_emma(pcdev) (cpu_is_mx27() && pcdev->use_emma) 210 211#define MAX_VIDEO_MEM 16 212 213struct mx2_camera_dev { 214 struct device *dev; 215 struct soc_camera_host soc_host; 216 struct soc_camera_device *icd; 217 struct clk *clk_csi, *clk_emma; 218 219 unsigned int irq_csi, irq_emma; 220 void __iomem *base_csi, *base_emma; 221 unsigned long base_dma; 222 223 struct mx2_camera_platform_data *pdata; 224 struct resource *res_csi, *res_emma; 225 unsigned long platform_flags; 226 227 struct list_head capture; 228 struct list_head active_bufs; 229 230 spinlock_t lock; 231 232 int dma; 233 struct mx2_buffer *active; 234 struct mx2_buffer *fb1_active; 235 struct mx2_buffer *fb2_active; 236 237 int use_emma; 238 239 u32 csicr1; 240 241 void *discard_buffer; 242 dma_addr_t discard_buffer_dma; 243 size_t discard_size; 244}; 245 246/* buffer for one video frame */ 247struct mx2_buffer { 248 /* common v4l buffer stuff -- must be first */ 249 struct videobuf_buffer vb; 250 251 enum v4l2_mbus_pixelcode code; 252 253 int bufnum; 254}; 255 256static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev) 257{ 258 unsigned long flags; 259 260 clk_disable(pcdev->clk_csi); 261 writel(0, pcdev->base_csi + CSICR1); 262 if (mx27_camera_emma(pcdev)) { 263 writel(0, pcdev->base_emma + PRP_CNTL); 264 } else if (cpu_is_mx25()) { 265 spin_lock_irqsave(&pcdev->lock, flags); 266 pcdev->fb1_active = NULL; 267 pcdev->fb2_active = NULL; 268 writel(0, pcdev->base_csi + CSIDMASA_FB1); 269 writel(0, pcdev->base_csi + CSIDMASA_FB2); 270 spin_unlock_irqrestore(&pcdev->lock, flags); 271 } 272} 273 274/* 275 * The following two functions absolutely depend on the fact, that 276 * there can be only one camera on mx2 camera sensor interface 277 */ 278static int mx2_camera_add_device(struct soc_camera_device *icd) 279{ 280 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 281 struct mx2_camera_dev *pcdev = ici->priv; 282 int ret; 283 u32 csicr1; 284 285 if (pcdev->icd) 286 return -EBUSY; 287 288 ret = clk_enable(pcdev->clk_csi); 289 if (ret < 0) 290 return ret; 291 292 csicr1 = CSICR1_MCLKEN; 293 294 if (mx27_camera_emma(pcdev)) { 295 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC | 296 CSICR1_RXFF_LEVEL(0); 297 } else if (cpu_is_mx27()) 298 csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2); 299 300 pcdev->csicr1 = csicr1; 301 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 302 303 pcdev->icd = icd; 304 305 dev_info(icd->dev.parent, "Camera driver attached to camera %d\n", 306 icd->devnum); 307 308 return 0; 309} 310 311static void mx2_camera_remove_device(struct soc_camera_device *icd) 312{ 313 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 314 struct mx2_camera_dev *pcdev = ici->priv; 315 316 BUG_ON(icd != pcdev->icd); 317 318 dev_info(icd->dev.parent, "Camera driver detached from camera %d\n", 319 icd->devnum); 320 321 mx2_camera_deactivate(pcdev); 322 323 if (pcdev->discard_buffer) { 324 dma_free_coherent(ici->v4l2_dev.dev, pcdev->discard_size, 325 pcdev->discard_buffer, 326 pcdev->discard_buffer_dma); 327 pcdev->discard_buffer = NULL; 328 } 329 330 pcdev->icd = NULL; 331} 332 333#ifdef CONFIG_MACH_MX27 334static void mx27_camera_dma_enable(struct mx2_camera_dev *pcdev) 335{ 336 u32 tmp; 337 338 imx_dma_enable(pcdev->dma); 339 340 tmp = readl(pcdev->base_csi + CSICR1); 341 tmp |= CSICR1_RF_OR_INTEN; 342 writel(tmp, pcdev->base_csi + CSICR1); 343} 344 345static irqreturn_t mx27_camera_irq(int irq_csi, void *data) 346{ 347 struct mx2_camera_dev *pcdev = data; 348 u32 status = readl(pcdev->base_csi + CSISR); 349 350 if (status & CSISR_SOF_INT && pcdev->active) { 351 u32 tmp; 352 353 tmp = readl(pcdev->base_csi + CSICR1); 354 writel(tmp | CSICR1_CLR_RXFIFO, pcdev->base_csi + CSICR1); 355 mx27_camera_dma_enable(pcdev); 356 } 357 358 writel(CSISR_SOF_INT | CSISR_RFF_OR_INT, pcdev->base_csi + CSISR); 359 360 return IRQ_HANDLED; 361} 362#else 363static irqreturn_t mx27_camera_irq(int irq_csi, void *data) 364{ 365 return IRQ_NONE; 366} 367#endif /* CONFIG_MACH_MX27 */ 368 369static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb, 370 int state) 371{ 372 struct videobuf_buffer *vb; 373 struct mx2_buffer *buf; 374 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active : 375 &pcdev->fb2_active; 376 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2; 377 unsigned long flags; 378 379 spin_lock_irqsave(&pcdev->lock, flags); 380 381 if (*fb_active == NULL) 382 goto out; 383 384 vb = &(*fb_active)->vb; 385 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 386 vb, vb->baddr, vb->bsize); 387 388 vb->state = state; 389 do_gettimeofday(&vb->ts); 390 vb->field_count++; 391 392 wake_up(&vb->done); 393 394 if (list_empty(&pcdev->capture)) { 395 buf = NULL; 396 writel(0, pcdev->base_csi + fb_reg); 397 } else { 398 buf = list_entry(pcdev->capture.next, struct mx2_buffer, 399 vb.queue); 400 vb = &buf->vb; 401 list_del(&vb->queue); 402 vb->state = VIDEOBUF_ACTIVE; 403 writel(videobuf_to_dma_contig(vb), pcdev->base_csi + fb_reg); 404 } 405 406 *fb_active = buf; 407 408out: 409 spin_unlock_irqrestore(&pcdev->lock, flags); 410} 411 412static irqreturn_t mx25_camera_irq(int irq_csi, void *data) 413{ 414 struct mx2_camera_dev *pcdev = data; 415 u32 status = readl(pcdev->base_csi + CSISR); 416 417 if (status & CSISR_DMA_TSF_FB1_INT) 418 mx25_camera_frame_done(pcdev, 1, VIDEOBUF_DONE); 419 else if (status & CSISR_DMA_TSF_FB2_INT) 420 mx25_camera_frame_done(pcdev, 2, VIDEOBUF_DONE); 421 422 423 writel(status, pcdev->base_csi + CSISR); 424 425 return IRQ_HANDLED; 426} 427 428/* 429 * Videobuf operations 430 */ 431static int mx2_videobuf_setup(struct videobuf_queue *vq, unsigned int *count, 432 unsigned int *size) 433{ 434 struct soc_camera_device *icd = vq->priv_data; 435 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, 436 icd->current_fmt->host_fmt); 437 438 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); 439 440 if (bytes_per_line < 0) 441 return bytes_per_line; 442 443 *size = bytes_per_line * icd->user_height; 444 445 if (0 == *count) 446 *count = 32; 447 if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024) 448 *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size; 449 450 return 0; 451} 452 453static void free_buffer(struct videobuf_queue *vq, struct mx2_buffer *buf) 454{ 455 struct soc_camera_device *icd = vq->priv_data; 456 struct videobuf_buffer *vb = &buf->vb; 457 458 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 459 vb, vb->baddr, vb->bsize); 460 461 /* 462 * This waits until this buffer is out of danger, i.e., until it is no 463 * longer in STATE_QUEUED or STATE_ACTIVE 464 */ 465 videobuf_waiton(vb, 0, 0); 466 467 videobuf_dma_contig_free(vq, vb); 468 dev_dbg(&icd->dev, "%s freed\n", __func__); 469 470 vb->state = VIDEOBUF_NEEDS_INIT; 471} 472 473static int mx2_videobuf_prepare(struct videobuf_queue *vq, 474 struct videobuf_buffer *vb, enum v4l2_field field) 475{ 476 struct soc_camera_device *icd = vq->priv_data; 477 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 478 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width, 479 icd->current_fmt->host_fmt); 480 int ret = 0; 481 482 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 483 vb, vb->baddr, vb->bsize); 484 485 if (bytes_per_line < 0) 486 return bytes_per_line; 487 488#ifdef DEBUG 489 /* 490 * This can be useful if you want to see if we actually fill 491 * the buffer with something 492 */ 493 memset((void *)vb->baddr, 0xaa, vb->bsize); 494#endif 495 496 if (buf->code != icd->current_fmt->code || 497 vb->width != icd->user_width || 498 vb->height != icd->user_height || 499 vb->field != field) { 500 buf->code = icd->current_fmt->code; 501 vb->width = icd->user_width; 502 vb->height = icd->user_height; 503 vb->field = field; 504 vb->state = VIDEOBUF_NEEDS_INIT; 505 } 506 507 vb->size = bytes_per_line * vb->height; 508 if (vb->baddr && vb->bsize < vb->size) { 509 ret = -EINVAL; 510 goto out; 511 } 512 513 if (vb->state == VIDEOBUF_NEEDS_INIT) { 514 ret = videobuf_iolock(vq, vb, NULL); 515 if (ret) 516 goto fail; 517 518 vb->state = VIDEOBUF_PREPARED; 519 } 520 521 return 0; 522 523fail: 524 free_buffer(vq, buf); 525out: 526 return ret; 527} 528 529static void mx2_videobuf_queue(struct videobuf_queue *vq, 530 struct videobuf_buffer *vb) 531{ 532 struct soc_camera_device *icd = vq->priv_data; 533 struct soc_camera_host *ici = 534 to_soc_camera_host(icd->dev.parent); 535 struct mx2_camera_dev *pcdev = ici->priv; 536 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 537 unsigned long flags; 538 539 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 540 vb, vb->baddr, vb->bsize); 541 542 spin_lock_irqsave(&pcdev->lock, flags); 543 544 vb->state = VIDEOBUF_QUEUED; 545 list_add_tail(&vb->queue, &pcdev->capture); 546 547 if (mx27_camera_emma(pcdev)) { 548 goto out; 549#ifdef CONFIG_MACH_MX27 550 } else if (cpu_is_mx27()) { 551 int ret; 552 553 if (pcdev->active == NULL) { 554 ret = imx_dma_setup_single(pcdev->dma, 555 videobuf_to_dma_contig(vb), vb->size, 556 (u32)pcdev->base_dma + 0x10, 557 DMA_MODE_READ); 558 if (ret) { 559 vb->state = VIDEOBUF_ERROR; 560 wake_up(&vb->done); 561 goto out; 562 } 563 564 vb->state = VIDEOBUF_ACTIVE; 565 pcdev->active = buf; 566 } 567#endif 568 } else { /* cpu_is_mx25() */ 569 u32 csicr3, dma_inten = 0; 570 571 if (pcdev->fb1_active == NULL) { 572 writel(videobuf_to_dma_contig(vb), 573 pcdev->base_csi + CSIDMASA_FB1); 574 pcdev->fb1_active = buf; 575 dma_inten = CSICR1_FB1_DMA_INTEN; 576 } else if (pcdev->fb2_active == NULL) { 577 writel(videobuf_to_dma_contig(vb), 578 pcdev->base_csi + CSIDMASA_FB2); 579 pcdev->fb2_active = buf; 580 dma_inten = CSICR1_FB2_DMA_INTEN; 581 } 582 583 if (dma_inten) { 584 list_del(&vb->queue); 585 vb->state = VIDEOBUF_ACTIVE; 586 587 csicr3 = readl(pcdev->base_csi + CSICR3); 588 589 /* Reflash DMA */ 590 writel(csicr3 | CSICR3_DMA_REFLASH_RFF, 591 pcdev->base_csi + CSICR3); 592 593 /* clear & enable interrupts */ 594 writel(dma_inten, pcdev->base_csi + CSISR); 595 pcdev->csicr1 |= dma_inten; 596 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 597 598 /* enable DMA */ 599 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1); 600 writel(csicr3, pcdev->base_csi + CSICR3); 601 } 602 } 603 604out: 605 spin_unlock_irqrestore(&pcdev->lock, flags); 606} 607 608static void mx2_videobuf_release(struct videobuf_queue *vq, 609 struct videobuf_buffer *vb) 610{ 611 struct soc_camera_device *icd = vq->priv_data; 612 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 613 struct mx2_camera_dev *pcdev = ici->priv; 614 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb); 615 unsigned long flags; 616 617#ifdef DEBUG 618 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 619 vb, vb->baddr, vb->bsize); 620 621 switch (vb->state) { 622 case VIDEOBUF_ACTIVE: 623 dev_info(&icd->dev, "%s (active)\n", __func__); 624 break; 625 case VIDEOBUF_QUEUED: 626 dev_info(&icd->dev, "%s (queued)\n", __func__); 627 break; 628 case VIDEOBUF_PREPARED: 629 dev_info(&icd->dev, "%s (prepared)\n", __func__); 630 break; 631 default: 632 dev_info(&icd->dev, "%s (unknown) %d\n", __func__, 633 vb->state); 634 break; 635 } 636#endif 637 638 spin_lock_irqsave(&pcdev->lock, flags); 639 if (vb->state == VIDEOBUF_QUEUED) { 640 list_del(&vb->queue); 641 vb->state = VIDEOBUF_ERROR; 642 } 643 spin_unlock_irqrestore(&pcdev->lock, flags); 644 645 free_buffer(vq, buf); 646} 647 648static struct videobuf_queue_ops mx2_videobuf_ops = { 649 .buf_setup = mx2_videobuf_setup, 650 .buf_prepare = mx2_videobuf_prepare, 651 .buf_queue = mx2_videobuf_queue, 652 .buf_release = mx2_videobuf_release, 653}; 654 655static void mx2_camera_init_videobuf(struct videobuf_queue *q, 656 struct soc_camera_device *icd) 657{ 658 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 659 struct mx2_camera_dev *pcdev = ici->priv; 660 661 videobuf_queue_dma_contig_init(q, &mx2_videobuf_ops, pcdev->dev, 662 &pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE, 663 V4L2_FIELD_NONE, sizeof(struct mx2_buffer), icd); 664} 665 666#define MX2_BUS_FLAGS (SOCAM_DATAWIDTH_8 | \ 667 SOCAM_MASTER | \ 668 SOCAM_VSYNC_ACTIVE_HIGH | \ 669 SOCAM_VSYNC_ACTIVE_LOW | \ 670 SOCAM_HSYNC_ACTIVE_HIGH | \ 671 SOCAM_HSYNC_ACTIVE_LOW | \ 672 SOCAM_PCLK_SAMPLE_RISING | \ 673 SOCAM_PCLK_SAMPLE_FALLING | \ 674 SOCAM_DATA_ACTIVE_HIGH | \ 675 SOCAM_DATA_ACTIVE_LOW) 676 677static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev) 678{ 679 u32 cntl; 680 int count = 0; 681 682 cntl = readl(pcdev->base_emma + PRP_CNTL); 683 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL); 684 while (count++ < 100) { 685 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST)) 686 return 0; 687 barrier(); 688 udelay(1); 689 } 690 691 return -ETIMEDOUT; 692} 693 694static void mx27_camera_emma_buf_init(struct soc_camera_device *icd, 695 int bytesperline) 696{ 697 struct soc_camera_host *ici = 698 to_soc_camera_host(icd->dev.parent); 699 struct mx2_camera_dev *pcdev = ici->priv; 700 701 writel(pcdev->discard_buffer_dma, 702 pcdev->base_emma + PRP_DEST_RGB1_PTR); 703 writel(pcdev->discard_buffer_dma, 704 pcdev->base_emma + PRP_DEST_RGB2_PTR); 705 706 /* 707 * We only use the EMMA engine to get rid of the broken 708 * DMA Engine. No color space consversion at the moment. 709 * We adjust incoming and outgoing pixelformat to rgb16 710 * and adjust the bytesperline accordingly. 711 */ 712 writel(PRP_CNTL_CH1EN | 713 PRP_CNTL_CSIEN | 714 PRP_CNTL_DATA_IN_RGB16 | 715 PRP_CNTL_CH1_OUT_RGB16 | 716 PRP_CNTL_CH1_LEN | 717 PRP_CNTL_CH1BYP | 718 PRP_CNTL_CH1_TSKIP(0) | 719 PRP_CNTL_IN_TSKIP(0), 720 pcdev->base_emma + PRP_CNTL); 721 722 writel(((bytesperline >> 1) << 16) | icd->user_height, 723 pcdev->base_emma + PRP_SRC_FRAME_SIZE); 724 writel(((bytesperline >> 1) << 16) | icd->user_height, 725 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE); 726 writel(bytesperline, 727 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE); 728 writel(0x2ca00565, /* RGB565 */ 729 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL); 730 writel(0x2ca00565, /* RGB565 */ 731 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL); 732 733 /* Enable interrupts */ 734 writel(PRP_INTR_RDERR | 735 PRP_INTR_CH1WERR | 736 PRP_INTR_CH2WERR | 737 PRP_INTR_CH1FC | 738 PRP_INTR_CH2FC | 739 PRP_INTR_LBOVF | 740 PRP_INTR_CH2OVF, 741 pcdev->base_emma + PRP_INTR_CNTL); 742} 743 744static int mx2_camera_set_bus_param(struct soc_camera_device *icd, 745 __u32 pixfmt) 746{ 747 struct soc_camera_host *ici = 748 to_soc_camera_host(icd->dev.parent); 749 struct mx2_camera_dev *pcdev = ici->priv; 750 unsigned long camera_flags, common_flags; 751 int ret = 0; 752 int bytesperline; 753 u32 csicr1 = pcdev->csicr1; 754 755 camera_flags = icd->ops->query_bus_param(icd); 756 757 common_flags = soc_camera_bus_param_compatible(camera_flags, 758 MX2_BUS_FLAGS); 759 if (!common_flags) 760 return -EINVAL; 761 762 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) && 763 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) { 764 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH) 765 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW; 766 else 767 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH; 768 } 769 770 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) && 771 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) { 772 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING) 773 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING; 774 else 775 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING; 776 } 777 778 ret = icd->ops->set_bus_param(icd, common_flags); 779 if (ret < 0) 780 return ret; 781 782 if (common_flags & SOCAM_PCLK_SAMPLE_RISING) 783 csicr1 |= CSICR1_REDGE; 784 if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH) 785 csicr1 |= CSICR1_SOF_POL; 786 if (common_flags & SOCAM_HSYNC_ACTIVE_HIGH) 787 csicr1 |= CSICR1_HSYNC_POL; 788 if (pcdev->platform_flags & MX2_CAMERA_SWAP16) 789 csicr1 |= CSICR1_SWAP16_EN; 790 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC) 791 csicr1 |= CSICR1_EXT_VSYNC; 792 if (pcdev->platform_flags & MX2_CAMERA_CCIR) 793 csicr1 |= CSICR1_CCIR_EN; 794 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE) 795 csicr1 |= CSICR1_CCIR_MODE; 796 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK) 797 csicr1 |= CSICR1_GCLK_MODE; 798 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA) 799 csicr1 |= CSICR1_INV_DATA; 800 if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB) 801 csicr1 |= CSICR1_PACK_DIR; 802 803 pcdev->csicr1 = csicr1; 804 805 bytesperline = soc_mbus_bytes_per_line(icd->user_width, 806 icd->current_fmt->host_fmt); 807 if (bytesperline < 0) 808 return bytesperline; 809 810 if (mx27_camera_emma(pcdev)) { 811 ret = mx27_camera_emma_prp_reset(pcdev); 812 if (ret) 813 return ret; 814 815 if (pcdev->discard_buffer) 816 dma_free_coherent(ici->v4l2_dev.dev, 817 pcdev->discard_size, pcdev->discard_buffer, 818 pcdev->discard_buffer_dma); 819 820 /* 821 * I didn't manage to properly enable/disable the prp 822 * on a per frame basis during running transfers, 823 * thus we allocate a buffer here and use it to 824 * discard frames when no buffer is available. 825 * Feel free to work on this ;) 826 */ 827 pcdev->discard_size = icd->user_height * bytesperline; 828 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev, 829 pcdev->discard_size, &pcdev->discard_buffer_dma, 830 GFP_KERNEL); 831 if (!pcdev->discard_buffer) 832 return -ENOMEM; 833 834 mx27_camera_emma_buf_init(icd, bytesperline); 835 } else if (cpu_is_mx25()) { 836 writel((bytesperline * icd->user_height) >> 2, 837 pcdev->base_csi + CSIRXCNT); 838 writel((bytesperline << 16) | icd->user_height, 839 pcdev->base_csi + CSIIMAG_PARA); 840 } 841 842 writel(pcdev->csicr1, pcdev->base_csi + CSICR1); 843 844 return 0; 845} 846 847static int mx2_camera_set_crop(struct soc_camera_device *icd, 848 struct v4l2_crop *a) 849{ 850 struct v4l2_rect *rect = &a->c; 851 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 852 struct v4l2_mbus_framefmt mf; 853 int ret; 854 855 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096); 856 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096); 857 858 ret = v4l2_subdev_call(sd, video, s_crop, a); 859 if (ret < 0) 860 return ret; 861 862 /* The capture device might have changed its output */ 863 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf); 864 if (ret < 0) 865 return ret; 866 867 dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n", 868 mf.width, mf.height); 869 870 icd->user_width = mf.width; 871 icd->user_height = mf.height; 872 873 return ret; 874} 875 876static int mx2_camera_set_fmt(struct soc_camera_device *icd, 877 struct v4l2_format *f) 878{ 879 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 880 struct mx2_camera_dev *pcdev = ici->priv; 881 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 882 const struct soc_camera_format_xlate *xlate; 883 struct v4l2_pix_format *pix = &f->fmt.pix; 884 struct v4l2_mbus_framefmt mf; 885 int ret; 886 887 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat); 888 if (!xlate) { 889 dev_warn(icd->dev.parent, "Format %x not found\n", 890 pix->pixelformat); 891 return -EINVAL; 892 } 893 894 /* eMMA can only do RGB565 */ 895 if (mx27_camera_emma(pcdev) && pix->pixelformat != V4L2_PIX_FMT_RGB565) 896 return -EINVAL; 897 898 mf.width = pix->width; 899 mf.height = pix->height; 900 mf.field = pix->field; 901 mf.colorspace = pix->colorspace; 902 mf.code = xlate->code; 903 904 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf); 905 if (ret < 0 && ret != -ENOIOCTLCMD) 906 return ret; 907 908 if (mf.code != xlate->code) 909 return -EINVAL; 910 911 pix->width = mf.width; 912 pix->height = mf.height; 913 pix->field = mf.field; 914 pix->colorspace = mf.colorspace; 915 icd->current_fmt = xlate; 916 917 return 0; 918} 919 920static int mx2_camera_try_fmt(struct soc_camera_device *icd, 921 struct v4l2_format *f) 922{ 923 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 924 struct mx2_camera_dev *pcdev = ici->priv; 925 struct v4l2_subdev *sd = soc_camera_to_subdev(icd); 926 const struct soc_camera_format_xlate *xlate; 927 struct v4l2_pix_format *pix = &f->fmt.pix; 928 struct v4l2_mbus_framefmt mf; 929 __u32 pixfmt = pix->pixelformat; 930 unsigned int width_limit; 931 int ret; 932 933 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt); 934 if (pixfmt && !xlate) { 935 dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt); 936 return -EINVAL; 937 } 938 939 940 /* eMMA can only do RGB565 */ 941 if (mx27_camera_emma(pcdev) && pixfmt != V4L2_PIX_FMT_RGB565) 942 return -EINVAL; 943 944 /* limit to MX25 hardware capabilities */ 945 if (cpu_is_mx25()) { 946 if (xlate->host_fmt->bits_per_sample <= 8) 947 width_limit = 0xffff * 4; 948 else 949 width_limit = 0xffff * 2; 950 /* CSIIMAG_PARA limit */ 951 if (pix->width > width_limit) 952 pix->width = width_limit; 953 if (pix->height > 0xffff) 954 pix->height = 0xffff; 955 956 pix->bytesperline = soc_mbus_bytes_per_line(pix->width, 957 xlate->host_fmt); 958 if (pix->bytesperline < 0) 959 return pix->bytesperline; 960 pix->sizeimage = pix->height * pix->bytesperline; 961 if (pix->sizeimage > (4 * 0x3ffff)) { /* CSIRXCNT limit */ 962 dev_warn(icd->dev.parent, 963 "Image size (%u) above limit\n", 964 pix->sizeimage); 965 return -EINVAL; 966 } 967 } 968 969 /* limit to sensor capabilities */ 970 mf.width = pix->width; 971 mf.height = pix->height; 972 mf.field = pix->field; 973 mf.colorspace = pix->colorspace; 974 mf.code = xlate->code; 975 976 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf); 977 if (ret < 0) 978 return ret; 979 980 if (mf.field == V4L2_FIELD_ANY) 981 mf.field = V4L2_FIELD_NONE; 982 if (mf.field != V4L2_FIELD_NONE) { 983 dev_err(icd->dev.parent, "Field type %d unsupported.\n", 984 mf.field); 985 return -EINVAL; 986 } 987 988 pix->width = mf.width; 989 pix->height = mf.height; 990 pix->field = mf.field; 991 pix->colorspace = mf.colorspace; 992 993 return 0; 994} 995 996static int mx2_camera_querycap(struct soc_camera_host *ici, 997 struct v4l2_capability *cap) 998{ 999 /* cap->name is set by the friendly caller:-> */ 1000 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card)); 1001 cap->version = MX2_CAM_VERSION_CODE; 1002 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; 1003 1004 return 0; 1005} 1006 1007static int mx2_camera_reqbufs(struct soc_camera_file *icf, 1008 struct v4l2_requestbuffers *p) 1009{ 1010 int i; 1011 1012 for (i = 0; i < p->count; i++) { 1013 struct mx2_buffer *buf = container_of(icf->vb_vidq.bufs[i], 1014 struct mx2_buffer, vb); 1015 INIT_LIST_HEAD(&buf->vb.queue); 1016 } 1017 1018 return 0; 1019} 1020 1021#ifdef CONFIG_MACH_MX27 1022static void mx27_camera_frame_done(struct mx2_camera_dev *pcdev, int state) 1023{ 1024 struct videobuf_buffer *vb; 1025 struct mx2_buffer *buf; 1026 unsigned long flags; 1027 int ret; 1028 1029 spin_lock_irqsave(&pcdev->lock, flags); 1030 1031 if (!pcdev->active) { 1032 dev_err(pcdev->dev, "%s called with no active buffer!\n", 1033 __func__); 1034 goto out; 1035 } 1036 1037 vb = &pcdev->active->vb; 1038 buf = container_of(vb, struct mx2_buffer, vb); 1039 WARN_ON(list_empty(&vb->queue)); 1040 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, 1041 vb, vb->baddr, vb->bsize); 1042 1043 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ 1044 list_del_init(&vb->queue); 1045 vb->state = state; 1046 do_gettimeofday(&vb->ts); 1047 vb->field_count++; 1048 1049 wake_up(&vb->done); 1050 1051 if (list_empty(&pcdev->capture)) { 1052 pcdev->active = NULL; 1053 goto out; 1054 } 1055 1056 pcdev->active = list_entry(pcdev->capture.next, 1057 struct mx2_buffer, vb.queue); 1058 1059 vb = &pcdev->active->vb; 1060 vb->state = VIDEOBUF_ACTIVE; 1061 1062 ret = imx_dma_setup_single(pcdev->dma, videobuf_to_dma_contig(vb), 1063 vb->size, (u32)pcdev->base_dma + 0x10, DMA_MODE_READ); 1064 1065 if (ret) { 1066 vb->state = VIDEOBUF_ERROR; 1067 pcdev->active = NULL; 1068 wake_up(&vb->done); 1069 } 1070 1071out: 1072 spin_unlock_irqrestore(&pcdev->lock, flags); 1073} 1074 1075static void mx27_camera_dma_err_callback(int channel, void *data, int err) 1076{ 1077 struct mx2_camera_dev *pcdev = data; 1078 1079 mx27_camera_frame_done(pcdev, VIDEOBUF_ERROR); 1080} 1081 1082static void mx27_camera_dma_callback(int channel, void *data) 1083{ 1084 struct mx2_camera_dev *pcdev = data; 1085 1086 mx27_camera_frame_done(pcdev, VIDEOBUF_DONE); 1087} 1088 1089#define DMA_REQ_CSI_RX 31 1090 1091static int __devinit mx27_camera_dma_init(struct platform_device *pdev, 1092 struct mx2_camera_dev *pcdev) 1093{ 1094 int err; 1095 1096 pcdev->dma = imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH); 1097 if (pcdev->dma < 0) { 1098 dev_err(&pdev->dev, "%s failed to request DMA channel\n", 1099 __func__); 1100 return pcdev->dma; 1101 } 1102 1103 err = imx_dma_setup_handlers(pcdev->dma, mx27_camera_dma_callback, 1104 mx27_camera_dma_err_callback, pcdev); 1105 if (err) { 1106 dev_err(&pdev->dev, "%s failed to set DMA callback\n", 1107 __func__); 1108 goto err_out; 1109 } 1110 1111 err = imx_dma_config_channel(pcdev->dma, 1112 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO, 1113 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR, 1114 DMA_REQ_CSI_RX, 1); 1115 if (err) { 1116 dev_err(&pdev->dev, "%s failed to config DMA channel\n", 1117 __func__); 1118 goto err_out; 1119 } 1120 1121 imx_dma_config_burstlen(pcdev->dma, 64); 1122 1123 return 0; 1124 1125err_out: 1126 imx_dma_free(pcdev->dma); 1127 1128 return err; 1129} 1130#endif /* CONFIG_MACH_MX27 */ 1131 1132static unsigned int mx2_camera_poll(struct file *file, poll_table *pt) 1133{ 1134 struct soc_camera_file *icf = file->private_data; 1135 1136 return videobuf_poll_stream(file, &icf->vb_vidq, pt); 1137} 1138 1139static struct soc_camera_host_ops mx2_soc_camera_host_ops = { 1140 .owner = THIS_MODULE, 1141 .add = mx2_camera_add_device, 1142 .remove = mx2_camera_remove_device, 1143 .set_fmt = mx2_camera_set_fmt, 1144 .set_crop = mx2_camera_set_crop, 1145 .try_fmt = mx2_camera_try_fmt, 1146 .init_videobuf = mx2_camera_init_videobuf, 1147 .reqbufs = mx2_camera_reqbufs, 1148 .poll = mx2_camera_poll, 1149 .querycap = mx2_camera_querycap, 1150 .set_bus_param = mx2_camera_set_bus_param, 1151}; 1152 1153static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev, 1154 int bufnum, int state) 1155{ 1156 struct mx2_buffer *buf; 1157 struct videobuf_buffer *vb; 1158 unsigned long phys; 1159 1160 if (!list_empty(&pcdev->active_bufs)) { 1161 buf = list_entry(pcdev->active_bufs.next, 1162 struct mx2_buffer, vb.queue); 1163 1164 BUG_ON(buf->bufnum != bufnum); 1165 1166 vb = &buf->vb; 1167#ifdef DEBUG 1168 phys = videobuf_to_dma_contig(vb); 1169 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum) 1170 != phys) { 1171 dev_err(pcdev->dev, "%p != %p\n", phys, 1172 readl(pcdev->base_emma + 1173 PRP_DEST_RGB1_PTR + 1174 4 * bufnum)); 1175 } 1176#endif 1177 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb, 1178 vb->baddr, vb->bsize); 1179 1180 list_del(&vb->queue); 1181 vb->state = state; 1182 do_gettimeofday(&vb->ts); 1183 vb->field_count++; 1184 1185 wake_up(&vb->done); 1186 } 1187 1188 if (list_empty(&pcdev->capture)) { 1189 writel(pcdev->discard_buffer_dma, pcdev->base_emma + 1190 PRP_DEST_RGB1_PTR + 4 * bufnum); 1191 return; 1192 } 1193 1194 buf = list_entry(pcdev->capture.next, 1195 struct mx2_buffer, vb.queue); 1196 1197 buf->bufnum = !bufnum; 1198 1199 list_move_tail(pcdev->capture.next, &pcdev->active_bufs); 1200 1201 vb = &buf->vb; 1202 vb->state = VIDEOBUF_ACTIVE; 1203 1204 phys = videobuf_to_dma_contig(vb); 1205 writel(phys, pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum); 1206} 1207 1208static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data) 1209{ 1210 struct mx2_camera_dev *pcdev = data; 1211 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS); 1212 struct mx2_buffer *buf; 1213 1214 if (status & (1 << 7)) { /* overflow */ 1215 u32 cntl; 1216 cntl = readl(pcdev->base_emma + PRP_CNTL); 1217 writel(cntl & ~PRP_CNTL_CH1EN, pcdev->base_emma + PRP_CNTL); 1218 writel(cntl, pcdev->base_emma + PRP_CNTL); 1219 } 1220 if ((status & (3 << 5)) == (3 << 5) 1221 && !list_empty(&pcdev->active_bufs)) { 1222 /* 1223 * Both buffers have triggered, process the one we're expecting 1224 * to first 1225 */ 1226 buf = list_entry(pcdev->active_bufs.next, 1227 struct mx2_buffer, vb.queue); 1228 mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE); 1229 status &= ~(1 << (6 - buf->bufnum)); /* mark processed */ 1230 } 1231 if (status & (1 << 6)) 1232 mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE); 1233 if (status & (1 << 5)) 1234 mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE); 1235 1236 writel(status, pcdev->base_emma + PRP_INTRSTATUS); 1237 1238 return IRQ_HANDLED; 1239} 1240 1241static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev) 1242{ 1243 struct resource *res_emma = pcdev->res_emma; 1244 int err = 0; 1245 1246 if (!request_mem_region(res_emma->start, resource_size(res_emma), 1247 MX2_CAM_DRV_NAME)) { 1248 err = -EBUSY; 1249 goto out; 1250 } 1251 1252 pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma)); 1253 if (!pcdev->base_emma) { 1254 err = -ENOMEM; 1255 goto exit_release; 1256 } 1257 1258 err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0, 1259 MX2_CAM_DRV_NAME, pcdev); 1260 if (err) { 1261 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n"); 1262 goto exit_iounmap; 1263 } 1264 1265 pcdev->clk_emma = clk_get(NULL, "emma"); 1266 if (IS_ERR(pcdev->clk_emma)) { 1267 err = PTR_ERR(pcdev->clk_emma); 1268 goto exit_free_irq; 1269 } 1270 1271 clk_enable(pcdev->clk_emma); 1272 1273 err = mx27_camera_emma_prp_reset(pcdev); 1274 if (err) 1275 goto exit_clk_emma_put; 1276 1277 return err; 1278 1279exit_clk_emma_put: 1280 clk_disable(pcdev->clk_emma); 1281 clk_put(pcdev->clk_emma); 1282exit_free_irq: 1283 free_irq(pcdev->irq_emma, pcdev); 1284exit_iounmap: 1285 iounmap(pcdev->base_emma); 1286exit_release: 1287 release_mem_region(res_emma->start, resource_size(res_emma)); 1288out: 1289 return err; 1290} 1291 1292static int __devinit mx2_camera_probe(struct platform_device *pdev) 1293{ 1294 struct mx2_camera_dev *pcdev; 1295 struct resource *res_csi, *res_emma; 1296 void __iomem *base_csi; 1297 int irq_csi, irq_emma; 1298 irq_handler_t mx2_cam_irq_handler = cpu_is_mx25() ? mx25_camera_irq 1299 : mx27_camera_irq; 1300 int err = 0; 1301 1302 dev_dbg(&pdev->dev, "initialising\n"); 1303 1304 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1305 irq_csi = platform_get_irq(pdev, 0); 1306 if (res_csi == NULL || irq_csi < 0) { 1307 dev_err(&pdev->dev, "Missing platform resources data\n"); 1308 err = -ENODEV; 1309 goto exit; 1310 } 1311 1312 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL); 1313 if (!pcdev) { 1314 dev_err(&pdev->dev, "Could not allocate pcdev\n"); 1315 err = -ENOMEM; 1316 goto exit; 1317 } 1318 1319 pcdev->clk_csi = clk_get(&pdev->dev, NULL); 1320 if (IS_ERR(pcdev->clk_csi)) { 1321 err = PTR_ERR(pcdev->clk_csi); 1322 goto exit_kfree; 1323 } 1324 1325 dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n", 1326 clk_get_rate(pcdev->clk_csi)); 1327 1328 /* Initialize DMA */ 1329#ifdef CONFIG_MACH_MX27 1330 if (cpu_is_mx27()) { 1331 err = mx27_camera_dma_init(pdev, pcdev); 1332 if (err) 1333 goto exit_clk_put; 1334 } 1335#endif /* CONFIG_MACH_MX27 */ 1336 1337 pcdev->res_csi = res_csi; 1338 pcdev->pdata = pdev->dev.platform_data; 1339 if (pcdev->pdata) { 1340 long rate; 1341 1342 pcdev->platform_flags = pcdev->pdata->flags; 1343 1344 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2); 1345 if (rate <= 0) { 1346 err = -ENODEV; 1347 goto exit_dma_free; 1348 } 1349 err = clk_set_rate(pcdev->clk_csi, rate); 1350 if (err < 0) 1351 goto exit_dma_free; 1352 } 1353 1354 INIT_LIST_HEAD(&pcdev->capture); 1355 INIT_LIST_HEAD(&pcdev->active_bufs); 1356 spin_lock_init(&pcdev->lock); 1357 1358 /* 1359 * Request the regions. 1360 */ 1361 if (!request_mem_region(res_csi->start, resource_size(res_csi), 1362 MX2_CAM_DRV_NAME)) { 1363 err = -EBUSY; 1364 goto exit_dma_free; 1365 } 1366 1367 base_csi = ioremap(res_csi->start, resource_size(res_csi)); 1368 if (!base_csi) { 1369 err = -ENOMEM; 1370 goto exit_release; 1371 } 1372 pcdev->irq_csi = irq_csi; 1373 pcdev->base_csi = base_csi; 1374 pcdev->base_dma = res_csi->start; 1375 pcdev->dev = &pdev->dev; 1376 1377 err = request_irq(pcdev->irq_csi, mx2_cam_irq_handler, 0, 1378 MX2_CAM_DRV_NAME, pcdev); 1379 if (err) { 1380 dev_err(pcdev->dev, "Camera interrupt register failed \n"); 1381 goto exit_iounmap; 1382 } 1383 1384 if (cpu_is_mx27()) { 1385 /* EMMA support */ 1386 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1387 irq_emma = platform_get_irq(pdev, 1); 1388 1389 if (res_emma && irq_emma >= 0) { 1390 dev_info(&pdev->dev, "Using EMMA\n"); 1391 pcdev->use_emma = 1; 1392 pcdev->res_emma = res_emma; 1393 pcdev->irq_emma = irq_emma; 1394 if (mx27_camera_emma_init(pcdev)) 1395 goto exit_free_irq; 1396 } 1397 } 1398 1399 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME, 1400 pcdev->soc_host.ops = &mx2_soc_camera_host_ops, 1401 pcdev->soc_host.priv = pcdev; 1402 pcdev->soc_host.v4l2_dev.dev = &pdev->dev; 1403 pcdev->soc_host.nr = pdev->id; 1404 err = soc_camera_host_register(&pcdev->soc_host); 1405 if (err) 1406 goto exit_free_emma; 1407 1408 return 0; 1409 1410exit_free_emma: 1411 if (mx27_camera_emma(pcdev)) { 1412 free_irq(pcdev->irq_emma, pcdev); 1413 clk_disable(pcdev->clk_emma); 1414 clk_put(pcdev->clk_emma); 1415 iounmap(pcdev->base_emma); 1416 release_mem_region(res_emma->start, resource_size(res_emma)); 1417 } 1418exit_free_irq: 1419 free_irq(pcdev->irq_csi, pcdev); 1420exit_iounmap: 1421 iounmap(base_csi); 1422exit_release: 1423 release_mem_region(res_csi->start, resource_size(res_csi)); 1424exit_dma_free: 1425#ifdef CONFIG_MACH_MX27 1426 if (cpu_is_mx27()) 1427 imx_dma_free(pcdev->dma); 1428exit_clk_put: 1429 clk_put(pcdev->clk_csi); 1430#endif /* CONFIG_MACH_MX27 */ 1431exit_kfree: 1432 kfree(pcdev); 1433exit: 1434 return err; 1435} 1436 1437static int __devexit mx2_camera_remove(struct platform_device *pdev) 1438{ 1439 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev); 1440 struct mx2_camera_dev *pcdev = container_of(soc_host, 1441 struct mx2_camera_dev, soc_host); 1442 struct resource *res; 1443 1444 clk_put(pcdev->clk_csi); 1445#ifdef CONFIG_MACH_MX27 1446 if (cpu_is_mx27()) 1447 imx_dma_free(pcdev->dma); 1448#endif /* CONFIG_MACH_MX27 */ 1449 free_irq(pcdev->irq_csi, pcdev); 1450 if (mx27_camera_emma(pcdev)) 1451 free_irq(pcdev->irq_emma, pcdev); 1452 1453 soc_camera_host_unregister(&pcdev->soc_host); 1454 1455 iounmap(pcdev->base_csi); 1456 1457 if (mx27_camera_emma(pcdev)) { 1458 clk_disable(pcdev->clk_emma); 1459 clk_put(pcdev->clk_emma); 1460 iounmap(pcdev->base_emma); 1461 res = pcdev->res_emma; 1462 release_mem_region(res->start, resource_size(res)); 1463 } 1464 1465 res = pcdev->res_csi; 1466 release_mem_region(res->start, resource_size(res)); 1467 1468 kfree(pcdev); 1469 1470 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n"); 1471 1472 return 0; 1473} 1474 1475static struct platform_driver mx2_camera_driver = { 1476 .driver = { 1477 .name = MX2_CAM_DRV_NAME, 1478 }, 1479 .remove = __devexit_p(mx2_camera_remove), 1480}; 1481 1482 1483static int __init mx2_camera_init(void) 1484{ 1485 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe); 1486} 1487 1488static void __exit mx2_camera_exit(void) 1489{ 1490 return platform_driver_unregister(&mx2_camera_driver); 1491} 1492 1493module_init(mx2_camera_init); 1494module_exit(mx2_camera_exit); 1495 1496MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver"); 1497MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>"); 1498MODULE_LICENSE("GPL"); 1499