1/* 2 * driver for ENE KB3926 B/C/D CIR (also known as ENE0XXX) 3 * 4 * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of the 9 * License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 19 * USA 20 */ 21#include <linux/spinlock.h> 22 23 24/* hardware address */ 25#define ENE_STATUS 0 /* hardware status - unused */ 26#define ENE_ADDR_HI 1 /* hi byte of register address */ 27#define ENE_ADDR_LO 2 /* low byte of register address */ 28#define ENE_IO 3 /* read/write window */ 29#define ENE_MAX_IO 4 30 31/* 8 bytes of samples, divided in 2 halfs*/ 32#define ENE_SAMPLE_BUFFER 0xF8F0 /* regular sample buffer */ 33#define ENE_SAMPLE_SPC_MASK 0x80 /* sample is space */ 34#define ENE_SAMPLE_VALUE_MASK 0x7F 35#define ENE_SAMPLE_OVERFLOW 0x7F 36#define ENE_SAMPLES_SIZE 4 37 38/* fan input sample buffer */ 39#define ENE_SAMPLE_BUFFER_FAN 0xF8FB /* this buffer holds high byte of */ 40 /* each sample of normal buffer */ 41#define ENE_FAN_SMPL_PULS_MSK 0x8000 /* this bit of combined sample */ 42 /* if set, says that sample is pulse */ 43#define ENE_FAN_VALUE_MASK 0x0FFF /* mask for valid bits of the value */ 44 45/* first firmware register */ 46#define ENE_FW1 0xF8F8 47#define ENE_FW1_ENABLE 0x01 /* enable fw processing */ 48#define ENE_FW1_TXIRQ 0x02 /* TX interrupt pending */ 49#define ENE_FW1_WAKE 0x40 /* enable wake from S3 */ 50#define ENE_FW1_IRQ 0x80 /* enable interrupt */ 51 52/* second firmware register */ 53#define ENE_FW2 0xF8F9 54#define ENE_FW2_BUF_HIGH 0x01 /* which half of the buffer to read */ 55#define ENE_FW2_IRQ_CLR 0x04 /* clear this on IRQ */ 56#define ENE_FW2_GP40_AS_LEARN 0x08 /* normal input is used as */ 57 /* learning input */ 58#define ENE_FW2_FAN_AS_NRML_IN 0x40 /* fan is used as normal input */ 59#define ENE_FW2_LEARNING 0x80 /* hardware supports learning and TX */ 60 61/* transmitter ports */ 62#define ENE_TX_PORT2 0xFC01 /* this enables one or both */ 63#define ENE_TX_PORT2_EN 0x20 /* TX ports */ 64#define ENE_TX_PORT1 0xFC08 65#define ENE_TX_PORT1_EN 0x02 66 67/* IRQ registers block (for revision B) */ 68#define ENEB_IRQ 0xFD09 /* IRQ number */ 69#define ENEB_IRQ_UNK1 0xFD17 /* unknown setting = 1 */ 70#define ENEB_IRQ_STATUS 0xFD80 /* irq status */ 71#define ENEB_IRQ_STATUS_IR 0x20 /* IR irq */ 72 73/* fan as input settings - only if learning capable */ 74#define ENE_FAN_AS_IN1 0xFE30 /* fan init reg 1 */ 75#define ENE_FAN_AS_IN1_EN 0xCD 76#define ENE_FAN_AS_IN2 0xFE31 /* fan init reg 2 */ 77#define ENE_FAN_AS_IN2_EN 0x03 78#define ENE_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */ 79 80/* IRQ registers block (for revision C,D) */ 81#define ENEC_IRQ 0xFE9B /* new irq settings register */ 82#define ENEC_IRQ_MASK 0x0F /* irq number mask */ 83#define ENEC_IRQ_UNK_EN 0x10 /* always enabled */ 84#define ENEC_IRQ_STATUS 0x20 /* irq status and ACK */ 85 86/* CIR block settings */ 87#define ENE_CIR_CONF1 0xFEC0 88#define ENE_CIR_CONF1_TX_CLEAR 0x01 /* clear that on revC */ 89 /* while transmitting */ 90#define ENE_CIR_CONF1_RX_ON 0x07 /* normal receiver enabled */ 91#define ENE_CIR_CONF1_LEARN1 0x08 /* enabled on learning mode */ 92#define ENE_CIR_CONF1_TX_ON 0x30 /* enabled on transmit */ 93#define ENE_CIR_CONF1_TX_CARR 0x80 /* send TX carrier or not */ 94 95#define ENE_CIR_CONF2 0xFEC1 /* unknown setting = 0 */ 96#define ENE_CIR_CONF2_LEARN2 0x10 /* set on enable learning */ 97#define ENE_CIR_CONF2_GPIO40DIS 0x20 /* disable input via gpio40 */ 98 99#define ENE_CIR_SAMPLE_PERIOD 0xFEC8 /* sample period in us */ 100#define ENE_CIR_SAMPLE_OVERFLOW 0x80 /* interrupt on overflows if set */ 101 102 103/* Two byte tx buffer */ 104#define ENE_TX_INPUT1 0xFEC9 105#define ENE_TX_INPUT2 0xFECA 106#define ENE_TX_PULSE_MASK 0x80 /* Transmitted sample is pulse */ 107#define ENE_TX_SMLP_MASK 0x7F 108#define ENE_TX_SMPL_PERIOD 50 /* transmit sample period - fixed */ 109 110 111/* Unknown TX setting - TX sample period ??? */ 112#define ENE_TX_UNK1 0xFECB /* set to 0x63 */ 113 114/* Current received carrier period */ 115#define ENE_RX_CARRIER 0xFECC /* RX period (500 ns) */ 116#define ENE_RX_CARRIER_VALID 0x80 /* Register content valid */ 117 118 119/* TX period (1/carrier) */ 120#define ENE_TX_PERIOD 0xFECE /* TX period (500 ns) */ 121#define ENE_TX_PERIOD_UNKBIT 0x80 /* This bit set on transmit*/ 122#define ENE_TX_PERIOD_PULSE 0xFECF /* TX pulse period (500 ns)*/ 123 124/* Hardware versions */ 125#define ENE_HW_VERSION 0xFF00 /* hardware revision */ 126#define ENE_PLLFRH 0xFF16 127#define ENE_PLLFRL 0xFF17 128 129#define ENE_HW_UNK 0xFF1D 130#define ENE_HW_UNK_CLR 0x04 131#define ENE_HW_VER_MAJOR 0xFF1E /* chip version */ 132#define ENE_HW_VER_MINOR 0xFF1F 133#define ENE_HW_VER_OLD 0xFD00 134 135/* Normal/Learning carrier ranges - only valid if we have learning input*/ 136/* TODO: test */ 137#define ENE_NORMAL_RX_LOW 34 138#define ENE_NORMAL_RX_HI 38 139 140/* Tx carrier range */ 141/* Hardware might be able to do more, but this range is enough for 142 all purposes */ 143#define ENE_TX_PERIOD_MAX 32 /* corresponds to 29.4 kHz */ 144#define ENE_TX_PERIOD_MIN 16 /* corrsponds to 62.5 kHz */ 145 146 147 148/* Minimal and maximal gaps */ 149 150/* Normal case: 151 Minimal gap is 0x7F * sample period 152 Maximum gap depends on hardware. 153 For KB3926B, it is unlimited, for newer models its around 154 250000, after which HW stops sending samples, and that is 155 not possible to change */ 156 157/* Fan case: 158 Both minimal and maximal gaps are same, and equal to 0xFFF * 0x61 159 And there is nothing to change this setting 160*/ 161 162#define ENE_MAXGAP 250000 163#define ENE_MINGAP (127 * sample_period) 164 165/******************************************************************************/ 166 167#define ENE_DRIVER_NAME "ene_ir" 168 169#define ENE_IRQ_RX 1 170#define ENE_IRQ_TX 2 171 172#define ENE_HW_B 1 /* 3926B */ 173#define ENE_HW_C 2 /* 3926C */ 174#define ENE_HW_D 3 /* 3926D */ 175 176#define ene_printk(level, text, ...) \ 177 printk(level ENE_DRIVER_NAME ": " text, ## __VA_ARGS__) 178 179#define ene_dbg(text, ...) \ 180 if (debug) \ 181 printk(KERN_DEBUG \ 182 ENE_DRIVER_NAME ": " text "\n" , ## __VA_ARGS__) 183 184#define ene_dbg_verbose(text, ...) \ 185 if (debug > 1) \ 186 printk(KERN_DEBUG \ 187 ENE_DRIVER_NAME ": " text "\n" , ## __VA_ARGS__) 188 189 190struct ene_device { 191 struct pnp_dev *pnp_dev; 192 struct input_dev *idev; 193 struct ir_dev_props *props; 194 int in_use; 195 196 /* hw IO settings */ 197 unsigned long hw_io; 198 int irq; 199 spinlock_t hw_lock; 200 201 /* HW features */ 202 int hw_revision; /* hardware revision */ 203 bool hw_learning_and_tx_capable; /* learning capable */ 204 bool hw_gpio40_learning; /* gpio40 is learning */ 205 bool hw_fan_as_normal_input; /* fan input is used as */ 206 /* regular input */ 207 /* HW state*/ 208 int rx_pointer; /* hw pointer to rx buffer */ 209 bool rx_fan_input_inuse; /* is fan input in use for rx*/ 210 int tx_reg; /* current reg used for TX */ 211 u8 saved_conf1; /* saved FEC0 reg */ 212 213 /* TX sample handling */ 214 unsigned int tx_sample; /* current sample for TX */ 215 bool tx_sample_pulse; /* current sample is pulse */ 216 217 /* TX buffer */ 218 int *tx_buffer; /* input samples buffer*/ 219 int tx_pos; /* position in that bufer */ 220 int tx_len; /* current len of tx buffer */ 221 int tx_done; /* done transmitting */ 222 /* one more sample pending*/ 223 struct completion tx_complete; /* TX completion */ 224 struct timer_list tx_sim_timer; 225 226 /* TX settings */ 227 int tx_period; 228 int tx_duty_cycle; 229 int transmitter_mask; 230 231 /* RX settings */ 232 bool learning_enabled; /* learning input enabled */ 233 bool carrier_detect_enabled; /* carrier detect enabled */ 234 int rx_period_adjust; 235}; 236