1/* 2 * TX4939 internal IDE driver 3 * Based on RBTX49xx patch from CELF patch archive. 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file "COPYING" in the main directory of this archive 7 * for more details. 8 * 9 * (C) Copyright TOSHIBA CORPORATION 2005-2007 10 */ 11 12#include <linux/module.h> 13#include <linux/types.h> 14#include <linux/ide.h> 15#include <linux/init.h> 16#include <linux/delay.h> 17#include <linux/platform_device.h> 18#include <linux/io.h> 19#include <linux/scatterlist.h> 20 21#include <asm/ide.h> 22 23#define MODNAME "tx4939ide" 24 25/* ATA Shadow Registers (8-bit except for Data which is 16-bit) */ 26#define TX4939IDE_Data 0x000 27#define TX4939IDE_Error_Feature 0x001 28#define TX4939IDE_Sec 0x002 29#define TX4939IDE_LBA0 0x003 30#define TX4939IDE_LBA1 0x004 31#define TX4939IDE_LBA2 0x005 32#define TX4939IDE_DevHead 0x006 33#define TX4939IDE_Stat_Cmd 0x007 34#define TX4939IDE_AltStat_DevCtl 0x402 35/* H/W DMA Registers */ 36#define TX4939IDE_DMA_Cmd 0x800 /* 8-bit */ 37#define TX4939IDE_DMA_Stat 0x802 /* 8-bit */ 38#define TX4939IDE_PRD_Ptr 0x804 /* 32-bit */ 39/* ATA100 CORE Registers (16-bit) */ 40#define TX4939IDE_Sys_Ctl 0xc00 41#define TX4939IDE_Xfer_Cnt_1 0xc08 42#define TX4939IDE_Xfer_Cnt_2 0xc0a 43#define TX4939IDE_Sec_Cnt 0xc10 44#define TX4939IDE_Start_Lo_Addr 0xc18 45#define TX4939IDE_Start_Up_Addr 0xc20 46#define TX4939IDE_Add_Ctl 0xc28 47#define TX4939IDE_Lo_Burst_Cnt 0xc30 48#define TX4939IDE_Up_Burst_Cnt 0xc38 49#define TX4939IDE_PIO_Addr 0xc88 50#define TX4939IDE_H_Rst_Tim 0xc90 51#define TX4939IDE_Int_Ctl 0xc98 52#define TX4939IDE_Pkt_Cmd 0xcb8 53#define TX4939IDE_Bxfer_Cnt_Hi 0xcc0 54#define TX4939IDE_Bxfer_Cnt_Lo 0xcc8 55#define TX4939IDE_Dev_TErr 0xcd0 56#define TX4939IDE_Pkt_Xfer_Ctl 0xcd8 57#define TX4939IDE_Start_TAddr 0xce0 58 59/* bits for Int_Ctl */ 60#define TX4939IDE_INT_ADDRERR 0x80 61#define TX4939IDE_INT_REACHMUL 0x40 62#define TX4939IDE_INT_DEVTIMING 0x20 63#define TX4939IDE_INT_UDMATERM 0x10 64#define TX4939IDE_INT_TIMER 0x08 65#define TX4939IDE_INT_BUSERR 0x04 66#define TX4939IDE_INT_XFEREND 0x02 67#define TX4939IDE_INT_HOST 0x01 68 69#define TX4939IDE_IGNORE_INTS \ 70 (TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL | \ 71 TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_UDMATERM | \ 72 TX4939IDE_INT_TIMER | TX4939IDE_INT_XFEREND) 73 74#ifdef __BIG_ENDIAN 75#define tx4939ide_swizzlel(a) ((a) ^ 4) 76#define tx4939ide_swizzlew(a) ((a) ^ 6) 77#define tx4939ide_swizzleb(a) ((a) ^ 7) 78#else 79#define tx4939ide_swizzlel(a) (a) 80#define tx4939ide_swizzlew(a) (a) 81#define tx4939ide_swizzleb(a) (a) 82#endif 83 84static u16 tx4939ide_readw(void __iomem *base, u32 reg) 85{ 86 return __raw_readw(base + tx4939ide_swizzlew(reg)); 87} 88static u8 tx4939ide_readb(void __iomem *base, u32 reg) 89{ 90 return __raw_readb(base + tx4939ide_swizzleb(reg)); 91} 92static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg) 93{ 94 __raw_writel(val, base + tx4939ide_swizzlel(reg)); 95} 96static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg) 97{ 98 __raw_writew(val, base + tx4939ide_swizzlew(reg)); 99} 100static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg) 101{ 102 __raw_writeb(val, base + tx4939ide_swizzleb(reg)); 103} 104 105#define TX4939IDE_BASE(hwif) ((void __iomem *)(hwif)->extra_base) 106 107static void tx4939ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 108{ 109 int is_slave = drive->dn; 110 u32 mask, val; 111 const u8 pio = drive->pio_mode - XFER_PIO_0; 112 u8 safe = pio; 113 ide_drive_t *pair; 114 115 pair = ide_get_pair_dev(drive); 116 if (pair) 117 safe = min_t(u8, safe, pair->pio_mode - XFER_PIO_0); 118 /* 119 * Update Command Transfer Mode for master/slave and Data 120 * Transfer Mode for this drive. 121 */ 122 mask = is_slave ? 0x07f00000 : 0x000007f0; 123 val = ((safe << 8) | (pio << 4)) << (is_slave ? 16 : 0); 124 hwif->select_data = (hwif->select_data & ~mask) | val; 125 /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */ 126} 127 128static void tx4939ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) 129{ 130 u32 mask, val; 131 const u8 mode = drive->dma_mode; 132 133 /* Update Data Transfer Mode for this drive. */ 134 if (mode >= XFER_UDMA_0) 135 val = mode - XFER_UDMA_0 + 8; 136 else 137 val = mode - XFER_MW_DMA_0 + 5; 138 if (drive->dn) { 139 mask = 0x00f00000; 140 val <<= 20; 141 } else { 142 mask = 0x000000f0; 143 val <<= 4; 144 } 145 hwif->select_data = (hwif->select_data & ~mask) | val; 146 /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */ 147} 148 149static u16 tx4939ide_check_error_ints(ide_hwif_t *hwif) 150{ 151 void __iomem *base = TX4939IDE_BASE(hwif); 152 u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl); 153 154 if (ctl & TX4939IDE_INT_BUSERR) { 155 /* reset FIFO */ 156 u16 sysctl = tx4939ide_readw(base, TX4939IDE_Sys_Ctl); 157 158 tx4939ide_writew(sysctl | 0x4000, base, TX4939IDE_Sys_Ctl); 159 mmiowb(); 160 /* wait 12GBUSCLK (typ. 60ns @ GBUS200MHz, max 270ns) */ 161 ndelay(270); 162 tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl); 163 } 164 if (ctl & (TX4939IDE_INT_ADDRERR | 165 TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_BUSERR)) 166 pr_err("%s: Error interrupt %#x (%s%s%s )\n", 167 hwif->name, ctl, 168 ctl & TX4939IDE_INT_ADDRERR ? " Address-Error" : "", 169 ctl & TX4939IDE_INT_DEVTIMING ? " DEV-Timing" : "", 170 ctl & TX4939IDE_INT_BUSERR ? " Bus-Error" : ""); 171 return ctl; 172} 173 174static void tx4939ide_clear_irq(ide_drive_t *drive) 175{ 176 ide_hwif_t *hwif; 177 void __iomem *base; 178 u16 ctl; 179 180 /* 181 * tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all job 182 * for DMA case. 183 */ 184 if (drive->waiting_for_dma) 185 return; 186 hwif = drive->hwif; 187 base = TX4939IDE_BASE(hwif); 188 ctl = tx4939ide_check_error_ints(hwif); 189 tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl); 190} 191 192static u8 tx4939ide_cable_detect(ide_hwif_t *hwif) 193{ 194 void __iomem *base = TX4939IDE_BASE(hwif); 195 196 return tx4939ide_readw(base, TX4939IDE_Sys_Ctl) & 0x2000 ? 197 ATA_CBL_PATA40 : ATA_CBL_PATA80; 198} 199 200#ifdef __BIG_ENDIAN 201static void tx4939ide_dma_host_set(ide_drive_t *drive, int on) 202{ 203 ide_hwif_t *hwif = drive->hwif; 204 u8 unit = drive->dn; 205 void __iomem *base = TX4939IDE_BASE(hwif); 206 u8 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat); 207 208 if (on) 209 dma_stat |= (1 << (5 + unit)); 210 else 211 dma_stat &= ~(1 << (5 + unit)); 212 213 tx4939ide_writeb(dma_stat, base, TX4939IDE_DMA_Stat); 214} 215#else 216#define tx4939ide_dma_host_set ide_dma_host_set 217#endif 218 219static u8 tx4939ide_clear_dma_status(void __iomem *base) 220{ 221 u8 dma_stat; 222 223 /* read DMA status for INTR & ERROR flags */ 224 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat); 225 /* clear INTR & ERROR flags */ 226 tx4939ide_writeb(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, base, 227 TX4939IDE_DMA_Stat); 228 /* recover intmask cleared by writing to bit2 of DMA_Stat */ 229 tx4939ide_writew(TX4939IDE_IGNORE_INTS << 8, base, TX4939IDE_Int_Ctl); 230 return dma_stat; 231} 232 233#ifdef __BIG_ENDIAN 234/* custom ide_build_dmatable to handle swapped layout */ 235static int tx4939ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd) 236{ 237 ide_hwif_t *hwif = drive->hwif; 238 u32 *table = (u32 *)hwif->dmatable_cpu; 239 unsigned int count = 0; 240 int i; 241 struct scatterlist *sg; 242 243 for_each_sg(hwif->sg_table, sg, cmd->sg_nents, i) { 244 u32 cur_addr, cur_len, bcount; 245 246 cur_addr = sg_dma_address(sg); 247 cur_len = sg_dma_len(sg); 248 249 /* 250 * Fill in the DMA table, without crossing any 64kB boundaries. 251 */ 252 253 while (cur_len) { 254 if (count++ >= PRD_ENTRIES) 255 goto use_pio_instead; 256 257 bcount = 0x10000 - (cur_addr & 0xffff); 258 if (bcount > cur_len) 259 bcount = cur_len; 260 if (bcount == 0x10000) 261 bcount = 0x8000; 262 *table++ = bcount & 0xffff; 263 *table++ = cur_addr; 264 cur_addr += bcount; 265 cur_len -= bcount; 266 } 267 } 268 269 if (count) { 270 *(table - 2) |= 0x80000000; 271 return count; 272 } 273 274use_pio_instead: 275 printk(KERN_ERR "%s: %s\n", drive->name, 276 count ? "DMA table too small" : "empty DMA table?"); 277 278 return 0; /* revert to PIO for this request */ 279} 280#else 281#define tx4939ide_build_dmatable ide_build_dmatable 282#endif 283 284static int tx4939ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd) 285{ 286 ide_hwif_t *hwif = drive->hwif; 287 void __iomem *base = TX4939IDE_BASE(hwif); 288 u8 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR; 289 290 /* fall back to PIO! */ 291 if (tx4939ide_build_dmatable(drive, cmd) == 0) 292 return 1; 293 294 /* PRD table */ 295 tx4939ide_writel(hwif->dmatable_dma, base, TX4939IDE_PRD_Ptr); 296 297 /* specify r/w */ 298 tx4939ide_writeb(rw, base, TX4939IDE_DMA_Cmd); 299 300 /* clear INTR & ERROR flags */ 301 tx4939ide_clear_dma_status(base); 302 303 tx4939ide_writew(SECTOR_SIZE / 2, base, drive->dn ? 304 TX4939IDE_Xfer_Cnt_2 : TX4939IDE_Xfer_Cnt_1); 305 306 tx4939ide_writew(blk_rq_sectors(cmd->rq), base, TX4939IDE_Sec_Cnt); 307 308 return 0; 309} 310 311static int tx4939ide_dma_end(ide_drive_t *drive) 312{ 313 ide_hwif_t *hwif = drive->hwif; 314 u8 dma_stat, dma_cmd; 315 void __iomem *base = TX4939IDE_BASE(hwif); 316 u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl); 317 318 /* get DMA command mode */ 319 dma_cmd = tx4939ide_readb(base, TX4939IDE_DMA_Cmd); 320 /* stop DMA */ 321 tx4939ide_writeb(dma_cmd & ~ATA_DMA_START, base, TX4939IDE_DMA_Cmd); 322 323 /* read and clear the INTR & ERROR bits */ 324 dma_stat = tx4939ide_clear_dma_status(base); 325 326#define CHECK_DMA_MASK (ATA_DMA_ACTIVE | ATA_DMA_ERR | ATA_DMA_INTR) 327 328 /* verify good DMA status */ 329 if ((dma_stat & CHECK_DMA_MASK) == 0 && 330 (ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) == 331 (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) 332 /* INT_IDE lost... bug? */ 333 return 0; 334 return ((dma_stat & CHECK_DMA_MASK) != 335 ATA_DMA_INTR) ? 0x10 | dma_stat : 0; 336} 337 338/* returns 1 if DMA IRQ issued, 0 otherwise */ 339static int tx4939ide_dma_test_irq(ide_drive_t *drive) 340{ 341 ide_hwif_t *hwif = drive->hwif; 342 void __iomem *base = TX4939IDE_BASE(hwif); 343 u16 ctl, ide_int; 344 u8 dma_stat, stat; 345 int found = 0; 346 347 ctl = tx4939ide_check_error_ints(hwif); 348 ide_int = ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST); 349 switch (ide_int) { 350 case TX4939IDE_INT_HOST: 351 /* On error, XFEREND might not be asserted. */ 352 stat = tx4939ide_readb(base, TX4939IDE_AltStat_DevCtl); 353 if ((stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) == ATA_ERR) 354 found = 1; 355 else 356 /* Wait for XFEREND (Mask HOST and unmask XFEREND) */ 357 ctl &= ~TX4939IDE_INT_XFEREND << 8; 358 ctl |= ide_int << 8; 359 break; 360 case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND: 361 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat); 362 if (!(dma_stat & ATA_DMA_INTR)) 363 pr_warning("%s: weird interrupt status. " 364 "DMA_Stat %#02x int_ctl %#04x\n", 365 hwif->name, dma_stat, ctl); 366 found = 1; 367 break; 368 } 369 /* 370 * Do not clear XFEREND, HOST now. They will be cleared by 371 * clearing bit2 of DMA_Stat. 372 */ 373 ctl &= ~ide_int; 374 tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl); 375 return found; 376} 377 378#ifdef __BIG_ENDIAN 379static u8 tx4939ide_dma_sff_read_status(ide_hwif_t *hwif) 380{ 381 void __iomem *base = TX4939IDE_BASE(hwif); 382 383 return tx4939ide_readb(base, TX4939IDE_DMA_Stat); 384} 385#else 386#define tx4939ide_dma_sff_read_status ide_dma_sff_read_status 387#endif 388 389static void tx4939ide_init_hwif(ide_hwif_t *hwif) 390{ 391 void __iomem *base = TX4939IDE_BASE(hwif); 392 393 /* Soft Reset */ 394 tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl); 395 mmiowb(); 396 /* at least 20 GBUSCLK (typ. 100ns @ GBUS200MHz, max 450ns) */ 397 ndelay(450); 398 tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl); 399 /* mask some interrupts and clear all interrupts */ 400 tx4939ide_writew((TX4939IDE_IGNORE_INTS << 8) | 0xff, base, 401 TX4939IDE_Int_Ctl); 402 403 tx4939ide_writew(0x0008, base, TX4939IDE_Lo_Burst_Cnt); 404 tx4939ide_writew(0, base, TX4939IDE_Up_Burst_Cnt); 405} 406 407static int tx4939ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d) 408{ 409 hwif->dma_base = 410 hwif->extra_base + tx4939ide_swizzleb(TX4939IDE_DMA_Cmd); 411 /* 412 * Note that we cannot use ATA_DMA_TABLE_OFS, ATA_DMA_STATUS 413 * for big endian. 414 */ 415 return ide_allocate_dma_engine(hwif); 416} 417 418static void tx4939ide_tf_load_fixup(ide_drive_t *drive) 419{ 420 ide_hwif_t *hwif = drive->hwif; 421 void __iomem *base = TX4939IDE_BASE(hwif); 422 u16 sysctl = hwif->select_data >> (drive->dn ? 16 : 0); 423 424 /* 425 * Fix ATA100 CORE System Control Register. (The write to the 426 * Device/Head register may write wrong data to the System 427 * Control Register) 428 * While Sys_Ctl is written here, dev_select() is not needed. 429 */ 430 tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl); 431} 432 433static void tx4939ide_tf_load(ide_drive_t *drive, struct ide_taskfile *tf, 434 u8 valid) 435{ 436 ide_tf_load(drive, tf, valid); 437 438 if (valid & IDE_VALID_DEVICE) 439 tx4939ide_tf_load_fixup(drive); 440} 441 442#ifdef __BIG_ENDIAN 443 444/* custom iops (independent from SWAP_IO_SPACE) */ 445static void tx4939ide_input_data_swap(ide_drive_t *drive, struct ide_cmd *cmd, 446 void *buf, unsigned int len) 447{ 448 unsigned long port = drive->hwif->io_ports.data_addr; 449 unsigned short *ptr = buf; 450 unsigned int count = (len + 1) / 2; 451 452 while (count--) 453 *ptr++ = cpu_to_le16(__raw_readw((void __iomem *)port)); 454 __ide_flush_dcache_range((unsigned long)buf, roundup(len, 2)); 455} 456 457static void tx4939ide_output_data_swap(ide_drive_t *drive, struct ide_cmd *cmd, 458 void *buf, unsigned int len) 459{ 460 unsigned long port = drive->hwif->io_ports.data_addr; 461 unsigned short *ptr = buf; 462 unsigned int count = (len + 1) / 2; 463 464 while (count--) { 465 __raw_writew(le16_to_cpu(*ptr), (void __iomem *)port); 466 ptr++; 467 } 468 __ide_flush_dcache_range((unsigned long)buf, roundup(len, 2)); 469} 470 471static const struct ide_tp_ops tx4939ide_tp_ops = { 472 .exec_command = ide_exec_command, 473 .read_status = ide_read_status, 474 .read_altstatus = ide_read_altstatus, 475 .write_devctl = ide_write_devctl, 476 477 .dev_select = ide_dev_select, 478 .tf_load = tx4939ide_tf_load, 479 .tf_read = ide_tf_read, 480 481 .input_data = tx4939ide_input_data_swap, 482 .output_data = tx4939ide_output_data_swap, 483}; 484 485#else /* __LITTLE_ENDIAN */ 486 487static const struct ide_tp_ops tx4939ide_tp_ops = { 488 .exec_command = ide_exec_command, 489 .read_status = ide_read_status, 490 .read_altstatus = ide_read_altstatus, 491 .write_devctl = ide_write_devctl, 492 493 .dev_select = ide_dev_select, 494 .tf_load = tx4939ide_tf_load, 495 .tf_read = ide_tf_read, 496 497 .input_data = ide_input_data, 498 .output_data = ide_output_data, 499}; 500 501#endif /* __LITTLE_ENDIAN */ 502 503static const struct ide_port_ops tx4939ide_port_ops = { 504 .set_pio_mode = tx4939ide_set_pio_mode, 505 .set_dma_mode = tx4939ide_set_dma_mode, 506 .clear_irq = tx4939ide_clear_irq, 507 .cable_detect = tx4939ide_cable_detect, 508}; 509 510static const struct ide_dma_ops tx4939ide_dma_ops = { 511 .dma_host_set = tx4939ide_dma_host_set, 512 .dma_setup = tx4939ide_dma_setup, 513 .dma_start = ide_dma_start, 514 .dma_end = tx4939ide_dma_end, 515 .dma_test_irq = tx4939ide_dma_test_irq, 516 .dma_lost_irq = ide_dma_lost_irq, 517 .dma_timer_expiry = ide_dma_sff_timer_expiry, 518 .dma_sff_read_status = tx4939ide_dma_sff_read_status, 519}; 520 521static const struct ide_port_info tx4939ide_port_info __initdata = { 522 .init_hwif = tx4939ide_init_hwif, 523 .init_dma = tx4939ide_init_dma, 524 .port_ops = &tx4939ide_port_ops, 525 .dma_ops = &tx4939ide_dma_ops, 526 .tp_ops = &tx4939ide_tp_ops, 527 .host_flags = IDE_HFLAG_MMIO, 528 .pio_mask = ATA_PIO4, 529 .mwdma_mask = ATA_MWDMA2, 530 .udma_mask = ATA_UDMA5, 531 .chipset = ide_generic, 532}; 533 534static int __init tx4939ide_probe(struct platform_device *pdev) 535{ 536 struct ide_hw hw, *hws[] = { &hw }; 537 struct ide_host *host; 538 struct resource *res; 539 int irq, ret; 540 unsigned long mapbase; 541 542 irq = platform_get_irq(pdev, 0); 543 if (irq < 0) 544 return -ENODEV; 545 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 546 if (!res) 547 return -ENODEV; 548 549 if (!devm_request_mem_region(&pdev->dev, res->start, 550 res->end - res->start + 1, "tx4938ide")) 551 return -EBUSY; 552 mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start, 553 res->end - res->start + 1); 554 if (!mapbase) 555 return -EBUSY; 556 memset(&hw, 0, sizeof(hw)); 557 hw.io_ports.data_addr = 558 mapbase + tx4939ide_swizzlew(TX4939IDE_Data); 559 hw.io_ports.error_addr = 560 mapbase + tx4939ide_swizzleb(TX4939IDE_Error_Feature); 561 hw.io_ports.nsect_addr = 562 mapbase + tx4939ide_swizzleb(TX4939IDE_Sec); 563 hw.io_ports.lbal_addr = 564 mapbase + tx4939ide_swizzleb(TX4939IDE_LBA0); 565 hw.io_ports.lbam_addr = 566 mapbase + tx4939ide_swizzleb(TX4939IDE_LBA1); 567 hw.io_ports.lbah_addr = 568 mapbase + tx4939ide_swizzleb(TX4939IDE_LBA2); 569 hw.io_ports.device_addr = 570 mapbase + tx4939ide_swizzleb(TX4939IDE_DevHead); 571 hw.io_ports.command_addr = 572 mapbase + tx4939ide_swizzleb(TX4939IDE_Stat_Cmd); 573 hw.io_ports.ctl_addr = 574 mapbase + tx4939ide_swizzleb(TX4939IDE_AltStat_DevCtl); 575 hw.irq = irq; 576 hw.dev = &pdev->dev; 577 578 pr_info("TX4939 IDE interface (base %#lx, irq %d)\n", mapbase, irq); 579 host = ide_host_alloc(&tx4939ide_port_info, hws, 1); 580 if (!host) 581 return -ENOMEM; 582 /* use extra_base for base address of the all registers */ 583 host->ports[0]->extra_base = mapbase; 584 ret = ide_host_register(host, &tx4939ide_port_info, hws); 585 if (ret) { 586 ide_host_free(host); 587 return ret; 588 } 589 platform_set_drvdata(pdev, host); 590 return 0; 591} 592 593static int __exit tx4939ide_remove(struct platform_device *pdev) 594{ 595 struct ide_host *host = platform_get_drvdata(pdev); 596 597 ide_host_remove(host); 598 return 0; 599} 600 601#ifdef CONFIG_PM 602static int tx4939ide_resume(struct platform_device *dev) 603{ 604 struct ide_host *host = platform_get_drvdata(dev); 605 ide_hwif_t *hwif = host->ports[0]; 606 607 tx4939ide_init_hwif(hwif); 608 return 0; 609} 610#else 611#define tx4939ide_resume NULL 612#endif 613 614static struct platform_driver tx4939ide_driver = { 615 .driver = { 616 .name = MODNAME, 617 .owner = THIS_MODULE, 618 }, 619 .remove = __exit_p(tx4939ide_remove), 620 .resume = tx4939ide_resume, 621}; 622 623static int __init tx4939ide_init(void) 624{ 625 return platform_driver_probe(&tx4939ide_driver, tx4939ide_probe); 626} 627 628static void __exit tx4939ide_exit(void) 629{ 630 platform_driver_unregister(&tx4939ide_driver); 631} 632 633module_init(tx4939ide_init); 634module_exit(tx4939ide_exit); 635 636MODULE_DESCRIPTION("TX4939 internal IDE driver"); 637MODULE_LICENSE("GPL"); 638MODULE_ALIAS("platform:tx4939ide"); 639