1/* 2 * Blackfin On-Chip Two Wire Interface Driver 3 * 4 * Copyright 2005-2007 Analog Devices Inc. 5 * 6 * Enter bugs at http://blackfin.uclinux.org/ 7 * 8 * Licensed under the GPL-2 or later. 9 */ 10 11#include <linux/module.h> 12#include <linux/kernel.h> 13#include <linux/init.h> 14#include <linux/i2c.h> 15#include <linux/slab.h> 16#include <linux/io.h> 17#include <linux/mm.h> 18#include <linux/timer.h> 19#include <linux/spinlock.h> 20#include <linux/completion.h> 21#include <linux/interrupt.h> 22#include <linux/platform_device.h> 23 24#include <asm/blackfin.h> 25#include <asm/portmux.h> 26#include <asm/irq.h> 27 28/* SMBus mode*/ 29#define TWI_I2C_MODE_STANDARD 1 30#define TWI_I2C_MODE_STANDARDSUB 2 31#define TWI_I2C_MODE_COMBINED 3 32#define TWI_I2C_MODE_REPEAT 4 33 34struct bfin_twi_iface { 35 int irq; 36 spinlock_t lock; 37 char read_write; 38 u8 command; 39 u8 *transPtr; 40 int readNum; 41 int writeNum; 42 int cur_mode; 43 int manual_stop; 44 int result; 45 struct i2c_adapter adap; 46 struct completion complete; 47 struct i2c_msg *pmsg; 48 int msg_num; 49 int cur_msg; 50 u16 saved_clkdiv; 51 u16 saved_control; 52 void __iomem *regs_base; 53}; 54 55 56#define DEFINE_TWI_REG(reg, off) \ 57static inline u16 read_##reg(struct bfin_twi_iface *iface) \ 58 { return bfin_read16(iface->regs_base + (off)); } \ 59static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \ 60 { bfin_write16(iface->regs_base + (off), v); } 61 62DEFINE_TWI_REG(CLKDIV, 0x00) 63DEFINE_TWI_REG(CONTROL, 0x04) 64DEFINE_TWI_REG(SLAVE_CTL, 0x08) 65DEFINE_TWI_REG(SLAVE_STAT, 0x0C) 66DEFINE_TWI_REG(SLAVE_ADDR, 0x10) 67DEFINE_TWI_REG(MASTER_CTL, 0x14) 68DEFINE_TWI_REG(MASTER_STAT, 0x18) 69DEFINE_TWI_REG(MASTER_ADDR, 0x1C) 70DEFINE_TWI_REG(INT_STAT, 0x20) 71DEFINE_TWI_REG(INT_MASK, 0x24) 72DEFINE_TWI_REG(FIFO_CTL, 0x28) 73DEFINE_TWI_REG(FIFO_STAT, 0x2C) 74DEFINE_TWI_REG(XMT_DATA8, 0x80) 75DEFINE_TWI_REG(XMT_DATA16, 0x84) 76DEFINE_TWI_REG(RCV_DATA8, 0x88) 77DEFINE_TWI_REG(RCV_DATA16, 0x8C) 78 79static const u16 pin_req[2][3] = { 80 {P_TWI0_SCL, P_TWI0_SDA, 0}, 81 {P_TWI1_SCL, P_TWI1_SDA, 0}, 82}; 83 84static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface, 85 unsigned short twi_int_status) 86{ 87 unsigned short mast_stat = read_MASTER_STAT(iface); 88 89 if (twi_int_status & XMTSERV) { 90 /* Transmit next data */ 91 if (iface->writeNum > 0) { 92 SSYNC(); 93 write_XMT_DATA8(iface, *(iface->transPtr++)); 94 iface->writeNum--; 95 } 96 /* start receive immediately after complete sending in 97 * combine mode. 98 */ 99 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) 100 write_MASTER_CTL(iface, 101 read_MASTER_CTL(iface) | MDIR | RSTART); 102 else if (iface->manual_stop) 103 write_MASTER_CTL(iface, 104 read_MASTER_CTL(iface) | STOP); 105 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && 106 iface->cur_msg + 1 < iface->msg_num) { 107 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD) 108 write_MASTER_CTL(iface, 109 read_MASTER_CTL(iface) | RSTART | MDIR); 110 else 111 write_MASTER_CTL(iface, 112 (read_MASTER_CTL(iface) | RSTART) & ~MDIR); 113 } 114 } 115 if (twi_int_status & RCVSERV) { 116 if (iface->readNum > 0) { 117 /* Receive next data */ 118 *(iface->transPtr) = read_RCV_DATA8(iface); 119 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { 120 /* Change combine mode into sub mode after 121 * read first data. 122 */ 123 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; 124 /* Get read number from first byte in block 125 * combine mode. 126 */ 127 if (iface->readNum == 1 && iface->manual_stop) 128 iface->readNum = *iface->transPtr + 1; 129 } 130 iface->transPtr++; 131 iface->readNum--; 132 } else if (iface->manual_stop) { 133 write_MASTER_CTL(iface, 134 read_MASTER_CTL(iface) | STOP); 135 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && 136 iface->cur_msg + 1 < iface->msg_num) { 137 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD) 138 write_MASTER_CTL(iface, 139 read_MASTER_CTL(iface) | RSTART | MDIR); 140 else 141 write_MASTER_CTL(iface, 142 (read_MASTER_CTL(iface) | RSTART) & ~MDIR); 143 } 144 } 145 if (twi_int_status & MERR) { 146 write_INT_MASK(iface, 0); 147 write_MASTER_STAT(iface, 0x3e); 148 write_MASTER_CTL(iface, 0); 149 iface->result = -EIO; 150 151 if (mast_stat & LOSTARB) 152 dev_dbg(&iface->adap.dev, "Lost Arbitration\n"); 153 if (mast_stat & ANAK) 154 dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n"); 155 if (mast_stat & DNAK) 156 dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n"); 157 if (mast_stat & BUFRDERR) 158 dev_dbg(&iface->adap.dev, "Buffer Read Error\n"); 159 if (mast_stat & BUFWRERR) 160 dev_dbg(&iface->adap.dev, "Buffer Write Error\n"); 161 162 /* If it is a quick transfer, only address without data, 163 * not an err, return 1. 164 */ 165 if (iface->cur_mode == TWI_I2C_MODE_STANDARD && 166 iface->transPtr == NULL && 167 (twi_int_status & MCOMP) && (mast_stat & DNAK)) 168 iface->result = 1; 169 170 complete(&iface->complete); 171 return; 172 } 173 if (twi_int_status & MCOMP) { 174 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { 175 if (iface->readNum == 0) { 176 /* set the read number to 1 and ask for manual 177 * stop in block combine mode 178 */ 179 iface->readNum = 1; 180 iface->manual_stop = 1; 181 write_MASTER_CTL(iface, 182 read_MASTER_CTL(iface) | (0xff << 6)); 183 } else { 184 /* set the readd number in other 185 * combine mode. 186 */ 187 write_MASTER_CTL(iface, 188 (read_MASTER_CTL(iface) & 189 (~(0xff << 6))) | 190 (iface->readNum << 6)); 191 } 192 /* remove restart bit and enable master receive */ 193 write_MASTER_CTL(iface, 194 read_MASTER_CTL(iface) & ~RSTART); 195 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && 196 iface->cur_msg+1 < iface->msg_num) { 197 iface->cur_msg++; 198 iface->transPtr = iface->pmsg[iface->cur_msg].buf; 199 iface->writeNum = iface->readNum = 200 iface->pmsg[iface->cur_msg].len; 201 /* Set Transmit device address */ 202 write_MASTER_ADDR(iface, 203 iface->pmsg[iface->cur_msg].addr); 204 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD) 205 iface->read_write = I2C_SMBUS_READ; 206 else { 207 iface->read_write = I2C_SMBUS_WRITE; 208 /* Transmit first data */ 209 if (iface->writeNum > 0) { 210 write_XMT_DATA8(iface, 211 *(iface->transPtr++)); 212 iface->writeNum--; 213 } 214 } 215 216 if (iface->pmsg[iface->cur_msg].len <= 255) 217 write_MASTER_CTL(iface, 218 (read_MASTER_CTL(iface) & 219 (~(0xff << 6))) | 220 (iface->pmsg[iface->cur_msg].len << 6)); 221 else { 222 write_MASTER_CTL(iface, 223 (read_MASTER_CTL(iface) | 224 (0xff << 6))); 225 iface->manual_stop = 1; 226 } 227 /* remove restart bit and enable master receive */ 228 write_MASTER_CTL(iface, 229 read_MASTER_CTL(iface) & ~RSTART); 230 } else { 231 iface->result = 1; 232 write_INT_MASK(iface, 0); 233 write_MASTER_CTL(iface, 0); 234 } 235 } 236 complete(&iface->complete); 237} 238 239/* Interrupt handler */ 240static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id) 241{ 242 struct bfin_twi_iface *iface = dev_id; 243 unsigned long flags; 244 unsigned short twi_int_status; 245 246 spin_lock_irqsave(&iface->lock, flags); 247 while (1) { 248 twi_int_status = read_INT_STAT(iface); 249 if (!twi_int_status) 250 break; 251 /* Clear interrupt status */ 252 write_INT_STAT(iface, twi_int_status); 253 bfin_twi_handle_interrupt(iface, twi_int_status); 254 SSYNC(); 255 } 256 spin_unlock_irqrestore(&iface->lock, flags); 257 return IRQ_HANDLED; 258} 259 260/* 261 * One i2c master transfer 262 */ 263static int bfin_twi_do_master_xfer(struct i2c_adapter *adap, 264 struct i2c_msg *msgs, int num) 265{ 266 struct bfin_twi_iface *iface = adap->algo_data; 267 struct i2c_msg *pmsg; 268 int rc = 0; 269 270 if (!(read_CONTROL(iface) & TWI_ENA)) 271 return -ENXIO; 272 273 while (read_MASTER_STAT(iface) & BUSBUSY) 274 yield(); 275 276 iface->pmsg = msgs; 277 iface->msg_num = num; 278 iface->cur_msg = 0; 279 280 pmsg = &msgs[0]; 281 if (pmsg->flags & I2C_M_TEN) { 282 dev_err(&adap->dev, "10 bits addr not supported!\n"); 283 return -EINVAL; 284 } 285 286 iface->cur_mode = TWI_I2C_MODE_REPEAT; 287 iface->manual_stop = 0; 288 iface->transPtr = pmsg->buf; 289 iface->writeNum = iface->readNum = pmsg->len; 290 iface->result = 0; 291 init_completion(&(iface->complete)); 292 /* Set Transmit device address */ 293 write_MASTER_ADDR(iface, pmsg->addr); 294 295 /* FIFO Initiation. Data in FIFO should be 296 * discarded before start a new operation. 297 */ 298 write_FIFO_CTL(iface, 0x3); 299 SSYNC(); 300 write_FIFO_CTL(iface, 0); 301 SSYNC(); 302 303 if (pmsg->flags & I2C_M_RD) 304 iface->read_write = I2C_SMBUS_READ; 305 else { 306 iface->read_write = I2C_SMBUS_WRITE; 307 /* Transmit first data */ 308 if (iface->writeNum > 0) { 309 write_XMT_DATA8(iface, *(iface->transPtr++)); 310 iface->writeNum--; 311 SSYNC(); 312 } 313 } 314 315 /* clear int stat */ 316 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV); 317 318 /* Interrupt mask . Enable XMT, RCV interrupt */ 319 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV); 320 SSYNC(); 321 322 if (pmsg->len <= 255) 323 write_MASTER_CTL(iface, pmsg->len << 6); 324 else { 325 write_MASTER_CTL(iface, 0xff << 6); 326 iface->manual_stop = 1; 327 } 328 329 /* Master enable */ 330 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | 331 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | 332 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); 333 SSYNC(); 334 335 while (!iface->result) { 336 if (!wait_for_completion_timeout(&iface->complete, 337 adap->timeout)) { 338 iface->result = -1; 339 dev_err(&adap->dev, "master transfer timeout\n"); 340 } 341 } 342 343 if (iface->result == 1) 344 rc = iface->cur_msg + 1; 345 else 346 rc = iface->result; 347 348 return rc; 349} 350 351/* 352 * Generic i2c master transfer entrypoint 353 */ 354static int bfin_twi_master_xfer(struct i2c_adapter *adap, 355 struct i2c_msg *msgs, int num) 356{ 357 return bfin_twi_do_master_xfer(adap, msgs, num); 358} 359 360/* 361 * One I2C SMBus transfer 362 */ 363int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr, 364 unsigned short flags, char read_write, 365 u8 command, int size, union i2c_smbus_data *data) 366{ 367 struct bfin_twi_iface *iface = adap->algo_data; 368 int rc = 0; 369 370 if (!(read_CONTROL(iface) & TWI_ENA)) 371 return -ENXIO; 372 373 while (read_MASTER_STAT(iface) & BUSBUSY) 374 yield(); 375 376 iface->writeNum = 0; 377 iface->readNum = 0; 378 379 /* Prepare datas & select mode */ 380 switch (size) { 381 case I2C_SMBUS_QUICK: 382 iface->transPtr = NULL; 383 iface->cur_mode = TWI_I2C_MODE_STANDARD; 384 break; 385 case I2C_SMBUS_BYTE: 386 if (data == NULL) 387 iface->transPtr = NULL; 388 else { 389 if (read_write == I2C_SMBUS_READ) 390 iface->readNum = 1; 391 else 392 iface->writeNum = 1; 393 iface->transPtr = &data->byte; 394 } 395 iface->cur_mode = TWI_I2C_MODE_STANDARD; 396 break; 397 case I2C_SMBUS_BYTE_DATA: 398 if (read_write == I2C_SMBUS_READ) { 399 iface->readNum = 1; 400 iface->cur_mode = TWI_I2C_MODE_COMBINED; 401 } else { 402 iface->writeNum = 1; 403 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; 404 } 405 iface->transPtr = &data->byte; 406 break; 407 case I2C_SMBUS_WORD_DATA: 408 if (read_write == I2C_SMBUS_READ) { 409 iface->readNum = 2; 410 iface->cur_mode = TWI_I2C_MODE_COMBINED; 411 } else { 412 iface->writeNum = 2; 413 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; 414 } 415 iface->transPtr = (u8 *)&data->word; 416 break; 417 case I2C_SMBUS_PROC_CALL: 418 iface->writeNum = 2; 419 iface->readNum = 2; 420 iface->cur_mode = TWI_I2C_MODE_COMBINED; 421 iface->transPtr = (u8 *)&data->word; 422 break; 423 case I2C_SMBUS_BLOCK_DATA: 424 if (read_write == I2C_SMBUS_READ) { 425 iface->readNum = 0; 426 iface->cur_mode = TWI_I2C_MODE_COMBINED; 427 } else { 428 iface->writeNum = data->block[0] + 1; 429 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; 430 } 431 iface->transPtr = data->block; 432 break; 433 case I2C_SMBUS_I2C_BLOCK_DATA: 434 if (read_write == I2C_SMBUS_READ) { 435 iface->readNum = data->block[0]; 436 iface->cur_mode = TWI_I2C_MODE_COMBINED; 437 } else { 438 iface->writeNum = data->block[0]; 439 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB; 440 } 441 iface->transPtr = (u8 *)&data->block[1]; 442 break; 443 default: 444 return -1; 445 } 446 447 iface->result = 0; 448 iface->manual_stop = 0; 449 iface->read_write = read_write; 450 iface->command = command; 451 init_completion(&(iface->complete)); 452 453 /* FIFO Initiation. Data in FIFO should be discarded before 454 * start a new operation. 455 */ 456 write_FIFO_CTL(iface, 0x3); 457 SSYNC(); 458 write_FIFO_CTL(iface, 0); 459 460 /* clear int stat */ 461 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV); 462 463 /* Set Transmit device address */ 464 write_MASTER_ADDR(iface, addr); 465 SSYNC(); 466 467 switch (iface->cur_mode) { 468 case TWI_I2C_MODE_STANDARDSUB: 469 write_XMT_DATA8(iface, iface->command); 470 write_INT_MASK(iface, MCOMP | MERR | 471 ((iface->read_write == I2C_SMBUS_READ) ? 472 RCVSERV : XMTSERV)); 473 SSYNC(); 474 475 if (iface->writeNum + 1 <= 255) 476 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6); 477 else { 478 write_MASTER_CTL(iface, 0xff << 6); 479 iface->manual_stop = 1; 480 } 481 /* Master enable */ 482 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | 483 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); 484 break; 485 case TWI_I2C_MODE_COMBINED: 486 write_XMT_DATA8(iface, iface->command); 487 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV); 488 SSYNC(); 489 490 if (iface->writeNum > 0) 491 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6); 492 else 493 write_MASTER_CTL(iface, 0x1 << 6); 494 /* Master enable */ 495 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | 496 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0)); 497 break; 498 default: 499 write_MASTER_CTL(iface, 0); 500 if (size != I2C_SMBUS_QUICK) { 501 /* Don't access xmit data register when this is a 502 * read operation. 503 */ 504 if (iface->read_write != I2C_SMBUS_READ) { 505 if (iface->writeNum > 0) { 506 write_XMT_DATA8(iface, 507 *(iface->transPtr++)); 508 if (iface->writeNum <= 255) 509 write_MASTER_CTL(iface, 510 iface->writeNum << 6); 511 else { 512 write_MASTER_CTL(iface, 513 0xff << 6); 514 iface->manual_stop = 1; 515 } 516 iface->writeNum--; 517 } else { 518 write_XMT_DATA8(iface, iface->command); 519 write_MASTER_CTL(iface, 1 << 6); 520 } 521 } else { 522 if (iface->readNum > 0 && iface->readNum <= 255) 523 write_MASTER_CTL(iface, 524 iface->readNum << 6); 525 else if (iface->readNum > 255) { 526 write_MASTER_CTL(iface, 0xff << 6); 527 iface->manual_stop = 1; 528 } else 529 break; 530 } 531 } 532 write_INT_MASK(iface, MCOMP | MERR | 533 ((iface->read_write == I2C_SMBUS_READ) ? 534 RCVSERV : XMTSERV)); 535 SSYNC(); 536 537 /* Master enable */ 538 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | 539 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | 540 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); 541 break; 542 } 543 SSYNC(); 544 545 while (!iface->result) { 546 if (!wait_for_completion_timeout(&iface->complete, 547 adap->timeout)) { 548 iface->result = -1; 549 dev_err(&adap->dev, "smbus transfer timeout\n"); 550 } 551 } 552 553 rc = (iface->result >= 0) ? 0 : -1; 554 555 return rc; 556} 557 558/* 559 * Generic I2C SMBus transfer entrypoint 560 */ 561int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr, 562 unsigned short flags, char read_write, 563 u8 command, int size, union i2c_smbus_data *data) 564{ 565 return bfin_twi_do_smbus_xfer(adap, addr, flags, 566 read_write, command, size, data); 567} 568 569/* 570 * Return what the adapter supports 571 */ 572static u32 bfin_twi_functionality(struct i2c_adapter *adap) 573{ 574 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 575 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 576 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL | 577 I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK; 578} 579 580static struct i2c_algorithm bfin_twi_algorithm = { 581 .master_xfer = bfin_twi_master_xfer, 582 .smbus_xfer = bfin_twi_smbus_xfer, 583 .functionality = bfin_twi_functionality, 584}; 585 586static int i2c_bfin_twi_suspend(struct platform_device *pdev, pm_message_t state) 587{ 588 struct bfin_twi_iface *iface = platform_get_drvdata(pdev); 589 590 iface->saved_clkdiv = read_CLKDIV(iface); 591 iface->saved_control = read_CONTROL(iface); 592 593 free_irq(iface->irq, iface); 594 595 /* Disable TWI */ 596 write_CONTROL(iface, iface->saved_control & ~TWI_ENA); 597 598 return 0; 599} 600 601static int i2c_bfin_twi_resume(struct platform_device *pdev) 602{ 603 struct bfin_twi_iface *iface = platform_get_drvdata(pdev); 604 605 int rc = request_irq(iface->irq, bfin_twi_interrupt_entry, 606 IRQF_DISABLED, pdev->name, iface); 607 if (rc) { 608 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq); 609 return -ENODEV; 610 } 611 612 /* Resume TWI interface clock as specified */ 613 write_CLKDIV(iface, iface->saved_clkdiv); 614 615 /* Resume TWI */ 616 write_CONTROL(iface, iface->saved_control); 617 618 return 0; 619} 620 621static int i2c_bfin_twi_probe(struct platform_device *pdev) 622{ 623 struct bfin_twi_iface *iface; 624 struct i2c_adapter *p_adap; 625 struct resource *res; 626 int rc; 627 unsigned int clkhilow; 628 629 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL); 630 if (!iface) { 631 dev_err(&pdev->dev, "Cannot allocate memory\n"); 632 rc = -ENOMEM; 633 goto out_error_nomem; 634 } 635 636 spin_lock_init(&(iface->lock)); 637 638 /* Find and map our resources */ 639 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 640 if (res == NULL) { 641 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); 642 rc = -ENOENT; 643 goto out_error_get_res; 644 } 645 646 iface->regs_base = ioremap(res->start, resource_size(res)); 647 if (iface->regs_base == NULL) { 648 dev_err(&pdev->dev, "Cannot map IO\n"); 649 rc = -ENXIO; 650 goto out_error_ioremap; 651 } 652 653 iface->irq = platform_get_irq(pdev, 0); 654 if (iface->irq < 0) { 655 dev_err(&pdev->dev, "No IRQ specified\n"); 656 rc = -ENOENT; 657 goto out_error_no_irq; 658 } 659 660 p_adap = &iface->adap; 661 p_adap->nr = pdev->id; 662 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name)); 663 p_adap->algo = &bfin_twi_algorithm; 664 p_adap->algo_data = iface; 665 p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 666 p_adap->dev.parent = &pdev->dev; 667 p_adap->timeout = 5 * HZ; 668 p_adap->retries = 3; 669 670 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi"); 671 if (rc) { 672 dev_err(&pdev->dev, "Can't setup pin mux!\n"); 673 goto out_error_pin_mux; 674 } 675 676 rc = request_irq(iface->irq, bfin_twi_interrupt_entry, 677 IRQF_DISABLED, pdev->name, iface); 678 if (rc) { 679 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq); 680 rc = -ENODEV; 681 goto out_error_req_irq; 682 } 683 684 /* Set TWI internal clock as 10MHz */ 685 write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F); 686 687 /* 688 * We will not end up with a CLKDIV=0 because no one will specify 689 * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250) 690 */ 691 clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2; 692 693 /* Set Twi interface clock as specified */ 694 write_CLKDIV(iface, (clkhilow << 8) | clkhilow); 695 696 /* Enable TWI */ 697 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA); 698 SSYNC(); 699 700 rc = i2c_add_numbered_adapter(p_adap); 701 if (rc < 0) { 702 dev_err(&pdev->dev, "Can't add i2c adapter!\n"); 703 goto out_error_add_adapter; 704 } 705 706 platform_set_drvdata(pdev, iface); 707 708 dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, " 709 "regs_base@%p\n", iface->regs_base); 710 711 return 0; 712 713out_error_add_adapter: 714 free_irq(iface->irq, iface); 715out_error_req_irq: 716out_error_no_irq: 717 peripheral_free_list(pin_req[pdev->id]); 718out_error_pin_mux: 719 iounmap(iface->regs_base); 720out_error_ioremap: 721out_error_get_res: 722 kfree(iface); 723out_error_nomem: 724 return rc; 725} 726 727static int i2c_bfin_twi_remove(struct platform_device *pdev) 728{ 729 struct bfin_twi_iface *iface = platform_get_drvdata(pdev); 730 731 platform_set_drvdata(pdev, NULL); 732 733 i2c_del_adapter(&(iface->adap)); 734 free_irq(iface->irq, iface); 735 peripheral_free_list(pin_req[pdev->id]); 736 iounmap(iface->regs_base); 737 kfree(iface); 738 739 return 0; 740} 741 742static struct platform_driver i2c_bfin_twi_driver = { 743 .probe = i2c_bfin_twi_probe, 744 .remove = i2c_bfin_twi_remove, 745 .suspend = i2c_bfin_twi_suspend, 746 .resume = i2c_bfin_twi_resume, 747 .driver = { 748 .name = "i2c-bfin-twi", 749 .owner = THIS_MODULE, 750 }, 751}; 752 753static int __init i2c_bfin_twi_init(void) 754{ 755 return platform_driver_register(&i2c_bfin_twi_driver); 756} 757 758static void __exit i2c_bfin_twi_exit(void) 759{ 760 platform_driver_unregister(&i2c_bfin_twi_driver); 761} 762 763module_init(i2c_bfin_twi_init); 764module_exit(i2c_bfin_twi_exit); 765 766MODULE_AUTHOR("Bryan Wu, Sonic Zhang"); 767MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver"); 768MODULE_LICENSE("GPL"); 769MODULE_ALIAS("platform:i2c-bfin-twi"); 770