1/* 2 * Copyright 2006-2007 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 24/****************************************************************************/ 25/*Portion I: Definitions shared between VBIOS and Driver */ 26/****************************************************************************/ 27 28 29#ifndef _ATOMBIOS_H 30#define _ATOMBIOS_H 31 32#define ATOM_VERSION_MAJOR 0x00020000 33#define ATOM_VERSION_MINOR 0x00000002 34 35#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) 36 37/* Endianness should be specified before inclusion, 38 * default to little endian 39 */ 40#ifndef ATOM_BIG_ENDIAN 41#error Endian not specified 42#endif 43 44#ifdef _H2INC 45 #ifndef ULONG 46 typedef unsigned long ULONG; 47 #endif 48 49 #ifndef UCHAR 50 typedef unsigned char UCHAR; 51 #endif 52 53 #ifndef USHORT 54 typedef unsigned short USHORT; 55 #endif 56#endif 57 58#define ATOM_DAC_A 0 59#define ATOM_DAC_B 1 60#define ATOM_EXT_DAC 2 61 62#define ATOM_CRTC1 0 63#define ATOM_CRTC2 1 64#define ATOM_CRTC3 2 65#define ATOM_CRTC4 3 66#define ATOM_CRTC5 4 67#define ATOM_CRTC6 5 68#define ATOM_CRTC_INVALID 0xFF 69 70#define ATOM_DIGA 0 71#define ATOM_DIGB 1 72 73#define ATOM_PPLL1 0 74#define ATOM_PPLL2 1 75#define ATOM_DCPLL 2 76#define ATOM_PPLL_INVALID 0xFF 77 78#define ATOM_SCALER1 0 79#define ATOM_SCALER2 1 80 81#define ATOM_SCALER_DISABLE 0 82#define ATOM_SCALER_CENTER 1 83#define ATOM_SCALER_EXPANSION 2 84#define ATOM_SCALER_MULTI_EX 3 85 86#define ATOM_DISABLE 0 87#define ATOM_ENABLE 1 88#define ATOM_LCD_BLOFF (ATOM_DISABLE+2) 89#define ATOM_LCD_BLON (ATOM_ENABLE+2) 90#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) 91#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) 92#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) 93#define ATOM_ENCODER_INIT (ATOM_DISABLE+7) 94#define ATOM_GET_STATUS (ATOM_DISABLE+8) 95 96#define ATOM_BLANKING 1 97#define ATOM_BLANKING_OFF 0 98 99#define ATOM_CURSOR1 0 100#define ATOM_CURSOR2 1 101 102#define ATOM_ICON1 0 103#define ATOM_ICON2 1 104 105#define ATOM_CRT1 0 106#define ATOM_CRT2 1 107 108#define ATOM_TV_NTSC 1 109#define ATOM_TV_NTSCJ 2 110#define ATOM_TV_PAL 3 111#define ATOM_TV_PALM 4 112#define ATOM_TV_PALCN 5 113#define ATOM_TV_PALN 6 114#define ATOM_TV_PAL60 7 115#define ATOM_TV_SECAM 8 116#define ATOM_TV_CV 16 117 118#define ATOM_DAC1_PS2 1 119#define ATOM_DAC1_CV 2 120#define ATOM_DAC1_NTSC 3 121#define ATOM_DAC1_PAL 4 122 123#define ATOM_DAC2_PS2 ATOM_DAC1_PS2 124#define ATOM_DAC2_CV ATOM_DAC1_CV 125#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC 126#define ATOM_DAC2_PAL ATOM_DAC1_PAL 127 128#define ATOM_PM_ON 0 129#define ATOM_PM_STANDBY 1 130#define ATOM_PM_SUSPEND 2 131#define ATOM_PM_OFF 3 132 133/* Bit0:{=0:single, =1:dual}, 134 Bit1 {=0:666RGB, =1:888RGB}, 135 Bit2:3:{Grey level} 136 Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ 137 138#define ATOM_PANEL_MISC_DUAL 0x00000001 139#define ATOM_PANEL_MISC_888RGB 0x00000002 140#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C 141#define ATOM_PANEL_MISC_FPDI 0x00000010 142#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 143#define ATOM_PANEL_MISC_SPATIAL 0x00000020 144#define ATOM_PANEL_MISC_TEMPORAL 0x00000040 145#define ATOM_PANEL_MISC_API_ENABLED 0x00000080 146 147 148#define MEMTYPE_DDR1 "DDR1" 149#define MEMTYPE_DDR2 "DDR2" 150#define MEMTYPE_DDR3 "DDR3" 151#define MEMTYPE_DDR4 "DDR4" 152 153#define ASIC_BUS_TYPE_PCI "PCI" 154#define ASIC_BUS_TYPE_AGP "AGP" 155#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" 156 157/* Maximum size of that FireGL flag string */ 158 159#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support 160#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) 161 162#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop 163#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 164 165#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support 166#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 167 168#define HW_ASSISTED_I2C_STATUS_FAILURE 2 169#define HW_ASSISTED_I2C_STATUS_SUCCESS 1 170 171#pragma pack(1) /* BIOS data must use byte aligment */ 172 173/* Define offset to location of ROM header. */ 174 175#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L 176#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L 177 178#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 179#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ 180#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f 181#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e 182 183/* Common header for all ROM Data tables. 184 Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. 185 And the pointer actually points to this header. */ 186 187typedef struct _ATOM_COMMON_TABLE_HEADER 188{ 189 USHORT usStructureSize; 190 UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ 191 UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ 192 /*Image can't be updated, while Driver needs to carry the new table! */ 193}ATOM_COMMON_TABLE_HEADER; 194 195typedef struct _ATOM_ROM_HEADER 196{ 197 ATOM_COMMON_TABLE_HEADER sHeader; 198 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, 199 atombios should init it as "ATOM", don't change the position */ 200 USHORT usBiosRuntimeSegmentAddress; 201 USHORT usProtectedModeInfoOffset; 202 USHORT usConfigFilenameOffset; 203 USHORT usCRC_BlockOffset; 204 USHORT usBIOS_BootupMessageOffset; 205 USHORT usInt10Offset; 206 USHORT usPciBusDevInitCode; 207 USHORT usIoBaseAddress; 208 USHORT usSubsystemVendorID; 209 USHORT usSubsystemID; 210 USHORT usPCI_InfoOffset; 211 USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ 212 USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ 213 UCHAR ucExtendedFunctionCode; 214 UCHAR ucReserved; 215}ATOM_ROM_HEADER; 216 217/*==============================Command Table Portion==================================== */ 218 219#ifdef UEFI_BUILD 220 #define UTEMP USHORT 221 #define USHORT void* 222#endif 223 224typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ 225 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 226 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON 227 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 228 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios 229 USHORT DIGxEncoderControl; //Only used by Bios 230 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 231 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 232 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed 233 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 234 USHORT GPIOPinControl; //Atomic Table, only used by Bios 235 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 236 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 237 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 238 USHORT DynamicClockGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 239 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 240 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 241 USHORT MemoryPLLInit; 242 USHORT AdjustDisplayPll; //only used by Bios 243 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 244 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios 245 USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios 246 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 247 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 248 USHORT LCD1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 249 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 250 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 251 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 252 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 253 USHORT GetConditionalGoldenSetting; //only used by Bios 254 USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 255 USHORT TMDSAEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 256 USHORT LVDSEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 257 USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 258 USHORT EnableScaler; //Atomic Table, used only by Bios 259 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 260 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 261 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 262 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 263 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios 264 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 265 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 266 USHORT SetCRTC_Replication; //Atomic Table, used only by Bios 267 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 268 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios 269 USHORT UpdateCRTC_DoubleBufferRegisters; 270 USHORT LUT_AutoFill; //Atomic Table, only used by Bios 271 USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios 272 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 273 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 274 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 275 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 276 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 277 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios 278 USHORT MemoryCleanUp; //Atomic Table, only used by Bios 279 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios 280 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components 281 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components 282 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init 283 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 284 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 285 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock 286 USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock 287 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios 288 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 289 USHORT MemoryTraining; //Atomic Table, used only by Bios 290 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 291 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 292 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 293 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 294 USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 295 USHORT SetupHWAssistedI2CStatus; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" 296 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 297 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 298 USHORT EnableYUV; //Atomic Table, indirectly used by various SW components,called from EnableVGARender 299 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 300 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 301 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 302 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 303 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios 304 USHORT DPEncoderService; //Function Table,only used by Bios 305}ATOM_MASTER_LIST_OF_COMMAND_TABLES; 306 307// For backward compatible 308#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction 309#define UNIPHYTransmitterControl DIG1TransmitterControl 310#define LVTMATransmitterControl DIG2TransmitterControl 311#define SetCRTC_DPM_State GetConditionalGoldenSetting 312#define SetUniphyInstance ASIC_StaticPwrMgtStatusChange 313#define HPDInterruptService ReadHWAssistedI2CStatus 314#define EnableVGA_Access GetSCLKOverMCLKRatio 315 316typedef struct _ATOM_MASTER_COMMAND_TABLE 317{ 318 ATOM_COMMON_TABLE_HEADER sHeader; 319 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; 320}ATOM_MASTER_COMMAND_TABLE; 321 322/****************************************************************************/ 323// Structures used in every command table 324/****************************************************************************/ 325typedef struct _ATOM_TABLE_ATTRIBUTE 326{ 327#if ATOM_BIG_ENDIAN 328 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 329 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 330 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 331#else 332 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 333 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 334 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 335#endif 336}ATOM_TABLE_ATTRIBUTE; 337 338typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS 339{ 340 ATOM_TABLE_ATTRIBUTE sbfAccess; 341 USHORT susAccess; 342}ATOM_TABLE_ATTRIBUTE_ACCESS; 343 344/****************************************************************************/ 345// Common header for all command tables. 346// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 347// And the pointer actually points to this header. 348/****************************************************************************/ 349typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER 350{ 351 ATOM_COMMON_TABLE_HEADER CommonHeader; 352 ATOM_TABLE_ATTRIBUTE TableAttribute; 353}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; 354 355/****************************************************************************/ 356// Structures used by ComputeMemoryEnginePLLTable 357/****************************************************************************/ 358#define COMPUTE_MEMORY_PLL_PARAM 1 359#define COMPUTE_ENGINE_PLL_PARAM 2 360 361typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 362{ 363 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div 364 UCHAR ucAction; //0:reserved //1:Memory //2:Engine 365 UCHAR ucReserved; //may expand to return larger Fbdiv later 366 UCHAR ucFbDiv; //return value 367 UCHAR ucPostDiv; //return value 368}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; 369 370typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 371{ 372 ULONG ulClock; //When return, [23:0] return real clock 373 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register 374 USHORT usFbDiv; //return Feedback value to be written to register 375 UCHAR ucPostDiv; //return post div to be written to register 376}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; 377#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 378 379 380#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value 381#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 382#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 383#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 384#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 385#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 386#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK 387 388#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 389#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 390#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 391#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 392#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 393 394typedef struct _ATOM_COMPUTE_CLOCK_FREQ 395{ 396#if ATOM_BIG_ENDIAN 397 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 398 ULONG ulClockFreq:24; // in unit of 10kHz 399#else 400 ULONG ulClockFreq:24; // in unit of 10kHz 401 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 402#endif 403}ATOM_COMPUTE_CLOCK_FREQ; 404 405typedef struct _ATOM_S_MPLL_FB_DIVIDER 406{ 407 USHORT usFbDivFrac; 408 USHORT usFbDiv; 409}ATOM_S_MPLL_FB_DIVIDER; 410 411typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 412{ 413 union 414 { 415 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 416 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 417 }; 418 UCHAR ucRefDiv; //Output Parameter 419 UCHAR ucPostDiv; //Output Parameter 420 UCHAR ucCntlFlag; //Output Parameter 421 UCHAR ucReserved; 422}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; 423 424// ucCntlFlag 425#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 426#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 427#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 428#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 429 430 431// V4 are only used for APU which PLL outside GPU 432typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 433{ 434#if ATOM_BIG_ENDIAN 435 ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly 436 ULONG ulClock:24; //Input= target clock, output = actual clock 437#else 438 ULONG ulClock:24; //Input= target clock, output = actual clock 439 ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly 440#endif 441}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; 442 443typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER 444{ 445 ATOM_COMPUTE_CLOCK_FREQ ulClock; 446 ULONG ulReserved[2]; 447}DYNAMICE_MEMORY_SETTINGS_PARAMETER; 448 449typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER 450{ 451 ATOM_COMPUTE_CLOCK_FREQ ulClock; 452 ULONG ulMemoryClock; 453 ULONG ulReserved; 454}DYNAMICE_ENGINE_SETTINGS_PARAMETER; 455 456/****************************************************************************/ 457// Structures used by SetEngineClockTable 458/****************************************************************************/ 459typedef struct _SET_ENGINE_CLOCK_PARAMETERS 460{ 461 ULONG ulTargetEngineClock; //In 10Khz unit 462}SET_ENGINE_CLOCK_PARAMETERS; 463 464typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION 465{ 466 ULONG ulTargetEngineClock; //In 10Khz unit 467 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 468}SET_ENGINE_CLOCK_PS_ALLOCATION; 469 470/****************************************************************************/ 471// Structures used by SetMemoryClockTable 472/****************************************************************************/ 473typedef struct _SET_MEMORY_CLOCK_PARAMETERS 474{ 475 ULONG ulTargetMemoryClock; //In 10Khz unit 476}SET_MEMORY_CLOCK_PARAMETERS; 477 478typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION 479{ 480 ULONG ulTargetMemoryClock; //In 10Khz unit 481 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 482}SET_MEMORY_CLOCK_PS_ALLOCATION; 483 484/****************************************************************************/ 485// Structures used by ASIC_Init.ctb 486/****************************************************************************/ 487typedef struct _ASIC_INIT_PARAMETERS 488{ 489 ULONG ulDefaultEngineClock; //In 10Khz unit 490 ULONG ulDefaultMemoryClock; //In 10Khz unit 491}ASIC_INIT_PARAMETERS; 492 493typedef struct _ASIC_INIT_PS_ALLOCATION 494{ 495 ASIC_INIT_PARAMETERS sASICInitClocks; 496 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure 497}ASIC_INIT_PS_ALLOCATION; 498 499/****************************************************************************/ 500// Structure used by DynamicClockGatingTable.ctb 501/****************************************************************************/ 502typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 503{ 504 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 505 UCHAR ucPadding[3]; 506}DYNAMIC_CLOCK_GATING_PARAMETERS; 507#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS 508 509/****************************************************************************/ 510// Structure used by EnableASIC_StaticPwrMgtTable.ctb 511/****************************************************************************/ 512typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 513{ 514 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 515 UCHAR ucPadding[3]; 516}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; 517#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 518 519/****************************************************************************/ 520// Structures used by DAC_LoadDetectionTable.ctb 521/****************************************************************************/ 522typedef struct _DAC_LOAD_DETECTION_PARAMETERS 523{ 524 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} 525 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} 526 UCHAR ucMisc; //Valid only when table revision =1.3 and above 527}DAC_LOAD_DETECTION_PARAMETERS; 528 529// DAC_LOAD_DETECTION_PARAMETERS.ucMisc 530#define DAC_LOAD_MISC_YPrPb 0x01 531 532typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION 533{ 534 DAC_LOAD_DETECTION_PARAMETERS sDacload; 535 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC 536}DAC_LOAD_DETECTION_PS_ALLOCATION; 537 538/****************************************************************************/ 539// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb 540/****************************************************************************/ 541typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 542{ 543 USHORT usPixelClock; // in 10KHz; for bios convenient 544 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) 545 UCHAR ucAction; // 0: turn off encoder 546 // 1: setup and turn on encoder 547 // 7: ATOM_ENCODER_INIT Initialize DAC 548}DAC_ENCODER_CONTROL_PARAMETERS; 549 550#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS 551 552/****************************************************************************/ 553// Structures used by DIG1EncoderControlTable 554// DIG2EncoderControlTable 555// ExternalEncoderControlTable 556/****************************************************************************/ 557typedef struct _DIG_ENCODER_CONTROL_PARAMETERS 558{ 559 USHORT usPixelClock; // in 10KHz; for bios convenient 560 UCHAR ucConfig; 561 // [2] Link Select: 562 // =0: PHY linkA if bfLane<3 563 // =1: PHY linkB if bfLanes<3 564 // =0: PHY linkA+B if bfLanes=3 565 // [3] Transmitter Sel 566 // =0: UNIPHY or PCIEPHY 567 // =1: LVTMA 568 UCHAR ucAction; // =0: turn off encoder 569 // =1: turn on encoder 570 UCHAR ucEncoderMode; 571 // =0: DP encoder 572 // =1: LVDS encoder 573 // =2: DVI encoder 574 // =3: HDMI encoder 575 // =4: SDVO encoder 576 UCHAR ucLaneNum; // how many lanes to enable 577 UCHAR ucReserved[2]; 578}DIG_ENCODER_CONTROL_PARAMETERS; 579#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS 580#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS 581 582//ucConfig 583#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 584#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 585#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 586#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 587#define ATOM_ENCODER_CONFIG_LINKA 0x00 588#define ATOM_ENCODER_CONFIG_LINKB 0x04 589#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA 590#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB 591#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 592#define ATOM_ENCODER_CONFIG_UNIPHY 0x00 593#define ATOM_ENCODER_CONFIG_LVTMA 0x08 594#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 595#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 596#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 597// ucAction 598// ATOM_ENABLE: Enable Encoder 599// ATOM_DISABLE: Disable Encoder 600 601//ucEncoderMode 602#define ATOM_ENCODER_MODE_DP 0 603#define ATOM_ENCODER_MODE_LVDS 1 604#define ATOM_ENCODER_MODE_DVI 2 605#define ATOM_ENCODER_MODE_HDMI 3 606#define ATOM_ENCODER_MODE_SDVO 4 607#define ATOM_ENCODER_MODE_DP_AUDIO 5 608#define ATOM_ENCODER_MODE_TV 13 609#define ATOM_ENCODER_MODE_CV 14 610#define ATOM_ENCODER_MODE_CRT 15 611 612typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 613{ 614#if ATOM_BIG_ENDIAN 615 UCHAR ucReserved1:2; 616 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 617 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 618 UCHAR ucReserved:1; 619 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 620#else 621 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 622 UCHAR ucReserved:1; 623 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 624 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 625 UCHAR ucReserved1:2; 626#endif 627}ATOM_DIG_ENCODER_CONFIG_V2; 628 629 630typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 631{ 632 USHORT usPixelClock; // in 10KHz; for bios convenient 633 ATOM_DIG_ENCODER_CONFIG_V2 acConfig; 634 UCHAR ucAction; 635 UCHAR ucEncoderMode; 636 // =0: DP encoder 637 // =1: LVDS encoder 638 // =2: DVI encoder 639 // =3: HDMI encoder 640 // =4: SDVO encoder 641 UCHAR ucLaneNum; // how many lanes to enable 642 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 643 UCHAR ucReserved; 644}DIG_ENCODER_CONTROL_PARAMETERS_V2; 645 646//ucConfig 647#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 648#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 649#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 650#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 651#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 652#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 653#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 654#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 655#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 656#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 657 658// ucAction: 659// ATOM_DISABLE 660// ATOM_ENABLE 661#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 662#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 663#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a 664#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b 665#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c 666#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 667#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e 668#define ATOM_ENCODER_CMD_SETUP 0x0f 669 670// ucStatus 671#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 672#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 673 674// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 675typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 676{ 677#if ATOM_BIG_ENDIAN 678 UCHAR ucReserved1:1; 679 UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F 680 UCHAR ucReserved:3; 681 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 682#else 683 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 684 UCHAR ucReserved:3; 685 UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F 686 UCHAR ucReserved1:1; 687#endif 688}ATOM_DIG_ENCODER_CONFIG_V3; 689 690#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 691 692 693typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 694{ 695 USHORT usPixelClock; // in 10KHz; for bios convenient 696 ATOM_DIG_ENCODER_CONFIG_V3 acConfig; 697 UCHAR ucAction; 698 UCHAR ucEncoderMode; 699 // =0: DP encoder 700 // =1: LVDS encoder 701 // =2: DVI encoder 702 // =3: HDMI encoder 703 // =4: SDVO encoder 704 // =5: DP audio 705 UCHAR ucLaneNum; // how many lanes to enable 706 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 707 UCHAR ucReserved; 708}DIG_ENCODER_CONTROL_PARAMETERS_V3; 709 710 711// define ucBitPerColor: 712#define PANEL_BPC_UNDEFINE 0x00 713#define PANEL_6BIT_PER_COLOR 0x01 714#define PANEL_8BIT_PER_COLOR 0x02 715#define PANEL_10BIT_PER_COLOR 0x03 716#define PANEL_12BIT_PER_COLOR 0x04 717#define PANEL_16BIT_PER_COLOR 0x05 718 719/****************************************************************************/ 720// Structures used by UNIPHYTransmitterControlTable 721// LVTMATransmitterControlTable 722// DVOOutputControlTable 723/****************************************************************************/ 724typedef struct _ATOM_DP_VS_MODE 725{ 726 UCHAR ucLaneSel; 727 UCHAR ucLaneSet; 728}ATOM_DP_VS_MODE; 729 730typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS 731{ 732 union 733 { 734 USHORT usPixelClock; // in 10KHz; for bios convenient 735 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 736 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 737 }; 738 UCHAR ucConfig; 739 // [0]=0: 4 lane Link, 740 // =1: 8 lane Link ( Dual Links TMDS ) 741 // [1]=0: InCoherent mode 742 // =1: Coherent Mode 743 // [2] Link Select: 744 // =0: PHY linkA if bfLane<3 745 // =1: PHY linkB if bfLanes<3 746 // =0: PHY linkA+B if bfLanes=3 747 // [5:4]PCIE lane Sel 748 // =0: lane 0~3 or 0~7 749 // =1: lane 4~7 750 // =2: lane 8~11 or 8~15 751 // =3: lane 12~15 752 UCHAR ucAction; // =0: turn off encoder 753 // =1: turn on encoder 754 UCHAR ucReserved[4]; 755}DIG_TRANSMITTER_CONTROL_PARAMETERS; 756 757#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS 758 759//ucInitInfo 760#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff 761 762//ucConfig 763#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 764#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 765#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 766#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 767#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 768#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 769#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 770 771#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 772#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 773#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 774 775#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 776#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 777#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 778#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 779#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 780#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 781#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 782#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 783#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 784#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 785#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 786 787//ucAction 788#define ATOM_TRANSMITTER_ACTION_DISABLE 0 789#define ATOM_TRANSMITTER_ACTION_ENABLE 1 790#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 791#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 792#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 793#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 794#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 795#define ATOM_TRANSMITTER_ACTION_INIT 7 796#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 797#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 798#define ATOM_TRANSMITTER_ACTION_SETUP 10 799#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 800#define ATOM_TRANSMITTER_ACTION_POWER_ON 12 801#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 802 803// Following are used for DigTransmitterControlTable ver1.2 804typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 805{ 806#if ATOM_BIG_ENDIAN 807 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 808 // =1 Dig Transmitter 2 ( Uniphy CD ) 809 // =2 Dig Transmitter 3 ( Uniphy EF ) 810 UCHAR ucReserved:1; 811 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 812 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 813 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 814 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 815 816 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 817 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 818#else 819 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 820 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 821 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 822 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 823 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 824 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 825 UCHAR ucReserved:1; 826 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 827 // =1 Dig Transmitter 2 ( Uniphy CD ) 828 // =2 Dig Transmitter 3 ( Uniphy EF ) 829#endif 830}ATOM_DIG_TRANSMITTER_CONFIG_V2; 831 832//ucConfig 833//Bit0 834#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 835 836//Bit1 837#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 838 839//Bit2 840#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 841#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 842#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 843 844// Bit3 845#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 846#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 847#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 848 849// Bit4 850#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 851 852// Bit7:6 853#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 854#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB 855#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD 856#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF 857 858typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 859{ 860 union 861 { 862 USHORT usPixelClock; // in 10KHz; for bios convenient 863 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 864 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 865 }; 866 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; 867 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 868 UCHAR ucReserved[4]; 869}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; 870 871typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 872{ 873#if ATOM_BIG_ENDIAN 874 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 875 // =1 Dig Transmitter 2 ( Uniphy CD ) 876 // =2 Dig Transmitter 3 ( Uniphy EF ) 877 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 878 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 879 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 880 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 881 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 882 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 883#else 884 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 885 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 886 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 887 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 888 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 889 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 890 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 891 // =1 Dig Transmitter 2 ( Uniphy CD ) 892 // =2 Dig Transmitter 3 ( Uniphy EF ) 893#endif 894}ATOM_DIG_TRANSMITTER_CONFIG_V3; 895 896typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 897{ 898 union 899 { 900 USHORT usPixelClock; // in 10KHz; for bios convenient 901 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 902 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 903 }; 904 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; 905 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 906 UCHAR ucLaneNum; 907 UCHAR ucReserved[3]; 908}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; 909 910//ucConfig 911//Bit0 912#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 913 914//Bit1 915#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 916 917//Bit2 918#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 919#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 920#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 921 922// Bit3 923#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 924#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 925#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 926 927// Bit5:4 928#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 929#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 930#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 931#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 932 933// Bit7:6 934#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 935#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB 936#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD 937#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF 938 939/****************************************************************************/ 940// Structures used by DAC1OuputControlTable 941// DAC2OuputControlTable 942// LVTMAOutputControlTable (Before DEC30) 943// TMDSAOutputControlTable (Before DEC30) 944/****************************************************************************/ 945typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 946{ 947 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE 948 // When the display is LCD, in addition to above: 949 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| 950 // ATOM_LCD_SELFTEST_STOP 951 952 UCHAR aucPadding[3]; // padding to DWORD aligned 953}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; 954 955#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 956 957 958#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 959#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 960 961#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 962#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 963 964#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 965#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 966 967#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 968#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 969 970#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 971#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 972 973#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 974#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 975 976#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 977#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 978 979#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 980#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION 981#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS 982 983/****************************************************************************/ 984// Structures used by BlankCRTCTable 985/****************************************************************************/ 986typedef struct _BLANK_CRTC_PARAMETERS 987{ 988 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 989 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF 990 USHORT usBlackColorRCr; 991 USHORT usBlackColorGY; 992 USHORT usBlackColorBCb; 993}BLANK_CRTC_PARAMETERS; 994#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS 995 996/****************************************************************************/ 997// Structures used by EnableCRTCTable 998// EnableCRTCMemReqTable 999// UpdateCRTC_DoubleBufferRegistersTable 1000/****************************************************************************/ 1001typedef struct _ENABLE_CRTC_PARAMETERS 1002{ 1003 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1004 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1005 UCHAR ucPadding[2]; 1006}ENABLE_CRTC_PARAMETERS; 1007#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS 1008 1009/****************************************************************************/ 1010// Structures used by SetCRTC_OverScanTable 1011/****************************************************************************/ 1012typedef struct _SET_CRTC_OVERSCAN_PARAMETERS 1013{ 1014 USHORT usOverscanRight; // right 1015 USHORT usOverscanLeft; // left 1016 USHORT usOverscanBottom; // bottom 1017 USHORT usOverscanTop; // top 1018 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1019 UCHAR ucPadding[3]; 1020}SET_CRTC_OVERSCAN_PARAMETERS; 1021#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS 1022 1023/****************************************************************************/ 1024// Structures used by SetCRTC_ReplicationTable 1025/****************************************************************************/ 1026typedef struct _SET_CRTC_REPLICATION_PARAMETERS 1027{ 1028 UCHAR ucH_Replication; // horizontal replication 1029 UCHAR ucV_Replication; // vertical replication 1030 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1031 UCHAR ucPadding; 1032}SET_CRTC_REPLICATION_PARAMETERS; 1033#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS 1034 1035/****************************************************************************/ 1036// Structures used by SelectCRTC_SourceTable 1037/****************************************************************************/ 1038typedef struct _SELECT_CRTC_SOURCE_PARAMETERS 1039{ 1040 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1041 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... 1042 UCHAR ucPadding[2]; 1043}SELECT_CRTC_SOURCE_PARAMETERS; 1044#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS 1045 1046typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 1047{ 1048 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1049 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1050 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1051 UCHAR ucPadding; 1052}SELECT_CRTC_SOURCE_PARAMETERS_V2; 1053 1054//ucEncoderID 1055//#define ASIC_INT_DAC1_ENCODER_ID 0x00 1056//#define ASIC_INT_TV_ENCODER_ID 0x02 1057//#define ASIC_INT_DIG1_ENCODER_ID 0x03 1058//#define ASIC_INT_DAC2_ENCODER_ID 0x04 1059//#define ASIC_EXT_TV_ENCODER_ID 0x06 1060//#define ASIC_INT_DVO_ENCODER_ID 0x07 1061//#define ASIC_INT_DIG2_ENCODER_ID 0x09 1062//#define ASIC_EXT_DIG_ENCODER_ID 0x05 1063 1064//ucEncodeMode 1065//#define ATOM_ENCODER_MODE_DP 0 1066//#define ATOM_ENCODER_MODE_LVDS 1 1067//#define ATOM_ENCODER_MODE_DVI 2 1068//#define ATOM_ENCODER_MODE_HDMI 3 1069//#define ATOM_ENCODER_MODE_SDVO 4 1070//#define ATOM_ENCODER_MODE_TV 13 1071//#define ATOM_ENCODER_MODE_CV 14 1072//#define ATOM_ENCODER_MODE_CRT 15 1073 1074/****************************************************************************/ 1075// Structures used by SetPixelClockTable 1076// GetPixelClockTable 1077/****************************************************************************/ 1078//Major revision=1., Minor revision=1 1079typedef struct _PIXEL_CLOCK_PARAMETERS 1080{ 1081 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1082 // 0 means disable PPLL 1083 USHORT usRefDiv; // Reference divider 1084 USHORT usFbDiv; // feedback divider 1085 UCHAR ucPostDiv; // post divider 1086 UCHAR ucFracFbDiv; // fractional feedback divider 1087 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1088 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1089 UCHAR ucCRTC; // Which CRTC uses this Ppll 1090 UCHAR ucPadding; 1091}PIXEL_CLOCK_PARAMETERS; 1092 1093//Major revision=1., Minor revision=2, add ucMiscIfno 1094//ucMiscInfo: 1095#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 1096#define MISC_DEVICE_INDEX_MASK 0xF0 1097#define MISC_DEVICE_INDEX_SHIFT 4 1098 1099typedef struct _PIXEL_CLOCK_PARAMETERS_V2 1100{ 1101 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1102 // 0 means disable PPLL 1103 USHORT usRefDiv; // Reference divider 1104 USHORT usFbDiv; // feedback divider 1105 UCHAR ucPostDiv; // post divider 1106 UCHAR ucFracFbDiv; // fractional feedback divider 1107 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1108 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1109 UCHAR ucCRTC; // Which CRTC uses this Ppll 1110 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog 1111}PIXEL_CLOCK_PARAMETERS_V2; 1112 1113//Major revision=1., Minor revision=3, structure/definition change 1114//ucEncoderMode: 1115//ATOM_ENCODER_MODE_DP 1116//ATOM_ENOCDER_MODE_LVDS 1117//ATOM_ENOCDER_MODE_DVI 1118//ATOM_ENOCDER_MODE_HDMI 1119//ATOM_ENOCDER_MODE_SDVO 1120//ATOM_ENCODER_MODE_TV 13 1121//ATOM_ENCODER_MODE_CV 14 1122//ATOM_ENCODER_MODE_CRT 15 1123 1124//ucDVOConfig 1125//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1126//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1127//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1128//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1129//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1130//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1131//#define DVO_ENCODER_CONFIG_24BIT 0x08 1132 1133//ucMiscInfo: also changed, see below 1134#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 1135#define PIXEL_CLOCK_MISC_VGA_MODE 0x02 1136#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 1137#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 1138#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 1139#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 1140#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 1141// V1.4 for RoadRunner 1142#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 1143#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 1144 1145typedef struct _PIXEL_CLOCK_PARAMETERS_V3 1146{ 1147 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1148 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. 1149 USHORT usRefDiv; // Reference divider 1150 USHORT usFbDiv; // feedback divider 1151 UCHAR ucPostDiv; // post divider 1152 UCHAR ucFracFbDiv; // fractional feedback divider 1153 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1154 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h 1155 union 1156 { 1157 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ 1158 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit 1159 }; 1160 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel 1161 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source 1162 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider 1163}PIXEL_CLOCK_PARAMETERS_V3; 1164 1165#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 1166#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST 1167 1168typedef struct _PIXEL_CLOCK_PARAMETERS_V5 1169{ 1170 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 1171 // drive the pixel clock. not used for DCPLL case. 1172 union{ 1173 UCHAR ucReserved; 1174 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. 1175 }; 1176 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing 1177 // 0 means disable PPLL/DCPLL. 1178 USHORT usFbDiv; // feedback divider integer part. 1179 UCHAR ucPostDiv; // post divider. 1180 UCHAR ucRefDiv; // Reference divider 1181 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1182 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1183 // indicate which graphic encoder will be used. 1184 UCHAR ucEncoderMode; // Encoder mode: 1185 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1186 // bit[1]= when VGA timing is used. 1187 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1188 // bit[4]= RefClock source for PPLL. 1189 // =0: XTLAIN( default mode ) 1190 // =1: other external clock source, which is pre-defined 1191 // by VBIOS depend on the feature required. 1192 // bit[7:5]: reserved. 1193 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1194 1195}PIXEL_CLOCK_PARAMETERS_V5; 1196 1197#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 1198#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 1199#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c 1200#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 1201#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 1202#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 1203#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 1204 1205typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 1206{ 1207 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; 1208}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; 1209 1210typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 1211{ 1212 UCHAR ucStatus; 1213 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock 1214 UCHAR ucReserved[2]; 1215}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; 1216 1217typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 1218{ 1219 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; 1220}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; 1221 1222/****************************************************************************/ 1223// Structures used by AdjustDisplayPllTable 1224/****************************************************************************/ 1225typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS 1226{ 1227 USHORT usPixelClock; 1228 UCHAR ucTransmitterID; 1229 UCHAR ucEncodeMode; 1230 union 1231 { 1232 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit 1233 UCHAR ucConfig; //if none DVO, not defined yet 1234 }; 1235 UCHAR ucReserved[3]; 1236}ADJUST_DISPLAY_PLL_PARAMETERS; 1237 1238#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 1239#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS 1240 1241typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 1242{ 1243 USHORT usPixelClock; // target pixel clock 1244 UCHAR ucTransmitterID; // transmitter id defined in objectid.h 1245 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI 1246 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX 1247 UCHAR ucReserved[3]; 1248}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; 1249 1250// usDispPllConfig v1.2 for RoadRunner 1251#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO 1252#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO 1253#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO 1254#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO 1255#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO 1256#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO 1257#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO 1258#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS 1259#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI 1260#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS 1261 1262 1263typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 1264{ 1265 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc 1266 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) 1267 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider 1268 UCHAR ucReserved[2]; 1269}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; 1270 1271typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 1272{ 1273 union 1274 { 1275 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; 1276 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; 1277 }; 1278} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; 1279 1280/****************************************************************************/ 1281// Structures used by EnableYUVTable 1282/****************************************************************************/ 1283typedef struct _ENABLE_YUV_PARAMETERS 1284{ 1285 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) 1286 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format 1287 UCHAR ucPadding[2]; 1288}ENABLE_YUV_PARAMETERS; 1289#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS 1290 1291/****************************************************************************/ 1292// Structures used by GetMemoryClockTable 1293/****************************************************************************/ 1294typedef struct _GET_MEMORY_CLOCK_PARAMETERS 1295{ 1296 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit 1297} GET_MEMORY_CLOCK_PARAMETERS; 1298#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS 1299 1300/****************************************************************************/ 1301// Structures used by GetEngineClockTable 1302/****************************************************************************/ 1303typedef struct _GET_ENGINE_CLOCK_PARAMETERS 1304{ 1305 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit 1306} GET_ENGINE_CLOCK_PARAMETERS; 1307#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS 1308 1309/****************************************************************************/ 1310// Following Structures and constant may be obsolete 1311/****************************************************************************/ 1312//Maxium 8 bytes,the data read in will be placed in the parameter space. 1313//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed 1314typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1315{ 1316 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1317 USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID 1318 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status 1319 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte 1320 UCHAR ucSlaveAddr; //Read from which slave 1321 UCHAR ucLineNumber; //Read from which HW assisted line 1322}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; 1323#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1324 1325 1326#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 1327#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 1328#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 1329#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 1330#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 1331 1332typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1333{ 1334 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1335 USHORT usByteOffset; //Write to which byte 1336 //Upper portion of usByteOffset is Format of data 1337 //1bytePS+offsetPS 1338 //2bytesPS+offsetPS 1339 //blockID+offsetPS 1340 //blockID+offsetID 1341 //blockID+counterID+offsetID 1342 UCHAR ucData; //PS data1 1343 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 1344 UCHAR ucSlaveAddr; //Write to which slave 1345 UCHAR ucLineNumber; //Write from which HW assisted line 1346}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; 1347 1348#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1349 1350typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS 1351{ 1352 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1353 UCHAR ucSlaveAddr; //Write to which slave 1354 UCHAR ucLineNumber; //Write from which HW assisted line 1355}SET_UP_HW_I2C_DATA_PARAMETERS; 1356 1357 1358/**************************************************************************/ 1359#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1360 1361/****************************************************************************/ 1362// Structures used by PowerConnectorDetectionTable 1363/****************************************************************************/ 1364typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS 1365{ 1366 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1367 UCHAR ucPwrBehaviorId; 1368 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1369}POWER_CONNECTOR_DETECTION_PARAMETERS; 1370 1371typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION 1372{ 1373 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1374 UCHAR ucReserved; 1375 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1376 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 1377}POWER_CONNECTOR_DETECTION_PS_ALLOCATION; 1378 1379/****************************LVDS SS Command Table Definitions**********************/ 1380 1381/****************************************************************************/ 1382// Structures used by EnableSpreadSpectrumOnPPLLTable 1383/****************************************************************************/ 1384typedef struct _ENABLE_LVDS_SS_PARAMETERS 1385{ 1386 USHORT usSpreadSpectrumPercentage; 1387 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1388 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY 1389 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1390 UCHAR ucPadding[3]; 1391}ENABLE_LVDS_SS_PARAMETERS; 1392 1393//ucTableFormatRevision=1,ucTableContentRevision=2 1394typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 1395{ 1396 USHORT usSpreadSpectrumPercentage; 1397 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1398 UCHAR ucSpreadSpectrumStep; // 1399 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1400 UCHAR ucSpreadSpectrumDelay; 1401 UCHAR ucSpreadSpectrumRange; 1402 UCHAR ucPadding; 1403}ENABLE_LVDS_SS_PARAMETERS_V2; 1404 1405//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. 1406typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL 1407{ 1408 USHORT usSpreadSpectrumPercentage; 1409 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1410 UCHAR ucSpreadSpectrumStep; // 1411 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1412 UCHAR ucSpreadSpectrumDelay; 1413 UCHAR ucSpreadSpectrumRange; 1414 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 1415}ENABLE_SPREAD_SPECTRUM_ON_PPLL; 1416 1417typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 1418{ 1419 USHORT usSpreadSpectrumPercentage; 1420 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1421 // Bit[1]: 1-Ext. 0-Int. 1422 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1423 // Bits[7:4] reserved 1424 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1425 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1426 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1427}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; 1428 1429#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 1430#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 1431#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 1432#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c 1433#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 1434#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 1435#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 1436#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF 1437#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 1438#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 1439#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 1440 1441#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL 1442 1443/**************************************************************************/ 1444 1445typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION 1446{ 1447 PIXEL_CLOCK_PARAMETERS sPCLKInput; 1448 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 1449}SET_PIXEL_CLOCK_PS_ALLOCATION; 1450 1451#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION 1452 1453/****************************************************************************/ 1454// Structures used by ### 1455/****************************************************************************/ 1456typedef struct _MEMORY_TRAINING_PARAMETERS 1457{ 1458 ULONG ulTargetMemoryClock; //In 10Khz unit 1459}MEMORY_TRAINING_PARAMETERS; 1460#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS 1461 1462 1463/****************************LVDS and other encoder command table definitions **********************/ 1464 1465 1466/****************************************************************************/ 1467// Structures used by LVDSEncoderControlTable (Before DCE30) 1468// LVTMAEncoderControlTable (Before DCE30) 1469// TMDSAEncoderControlTable (Before DCE30) 1470/****************************************************************************/ 1471typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS 1472{ 1473 USHORT usPixelClock; // in 10KHz; for bios convenient 1474 UCHAR ucMisc; // bit0=0: Enable single link 1475 // =1: Enable dual link 1476 // Bit1=0: 666RGB 1477 // =1: 888RGB 1478 UCHAR ucAction; // 0: turn off encoder 1479 // 1: setup and turn on encoder 1480}LVDS_ENCODER_CONTROL_PARAMETERS; 1481 1482#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS 1483 1484#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS 1485#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS 1486 1487#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS 1488#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS 1489 1490 1491//ucTableFormatRevision=1,ucTableContentRevision=2 1492typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 1493{ 1494 USHORT usPixelClock; // in 10KHz; for bios convenient 1495 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below 1496 UCHAR ucAction; // 0: turn off encoder 1497 // 1: setup and turn on encoder 1498 UCHAR ucTruncate; // bit0=0: Disable truncate 1499 // =1: Enable truncate 1500 // bit4=0: 666RGB 1501 // =1: 888RGB 1502 UCHAR ucSpatial; // bit0=0: Disable spatial dithering 1503 // =1: Enable spatial dithering 1504 // bit4=0: 666RGB 1505 // =1: 888RGB 1506 UCHAR ucTemporal; // bit0=0: Disable temporal dithering 1507 // =1: Enable temporal dithering 1508 // bit4=0: 666RGB 1509 // =1: 888RGB 1510 // bit5=0: Gray level 2 1511 // =1: Gray level 4 1512 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E 1513 // =1: 25FRC_SEL pattern F 1514 // bit6:5=0: 50FRC_SEL pattern A 1515 // =1: 50FRC_SEL pattern B 1516 // =2: 50FRC_SEL pattern C 1517 // =3: 50FRC_SEL pattern D 1518 // bit7=0: 75FRC_SEL pattern E 1519 // =1: 75FRC_SEL pattern F 1520}LVDS_ENCODER_CONTROL_PARAMETERS_V2; 1521 1522#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 1523 1524#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 1525#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 1526 1527#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 1528#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 1529 1530#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 1531#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 1532 1533#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 1534#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 1535 1536#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 1537#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 1538 1539/****************************************************************************/ 1540// Structures used by ### 1541/****************************************************************************/ 1542typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS 1543{ 1544 UCHAR ucEnable; // Enable or Disable External TMDS encoder 1545 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} 1546 UCHAR ucPadding[2]; 1547}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; 1548 1549typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION 1550{ 1551 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; 1552 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 1553}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; 1554 1555#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 1556 1557typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 1558{ 1559 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; 1560 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 1561}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; 1562 1563typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION 1564{ 1565 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; 1566 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 1567}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; 1568 1569/****************************************************************************/ 1570// Structures used by DVOEncoderControlTable 1571/****************************************************************************/ 1572//ucTableFormatRevision=1,ucTableContentRevision=3 1573 1574//ucDVOConfig: 1575#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1576#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1577#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1578#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1579#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1580#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1581#define DVO_ENCODER_CONFIG_24BIT 0x08 1582 1583typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 1584{ 1585 USHORT usPixelClock; 1586 UCHAR ucDVOConfig; 1587 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 1588 UCHAR ucReseved[4]; 1589}DVO_ENCODER_CONTROL_PARAMETERS_V3; 1590#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 1591 1592//ucTableFormatRevision=1 1593//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 1594// bit1=0: non-coherent mode 1595// =1: coherent mode 1596 1597//========================================================================================== 1598//Only change is here next time when changing encoder parameter definitions again! 1599#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 1600#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST 1601 1602#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 1603#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST 1604 1605#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 1606#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST 1607 1608#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS 1609#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION 1610 1611//========================================================================================== 1612#define PANEL_ENCODER_MISC_DUAL 0x01 1613#define PANEL_ENCODER_MISC_COHERENT 0x02 1614#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 1615#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 1616 1617#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE 1618#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE 1619#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) 1620 1621#define PANEL_ENCODER_TRUNCATE_EN 0x01 1622#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 1623#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 1624#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 1625#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 1626#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 1627#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 1628#define PANEL_ENCODER_25FRC_MASK 0x10 1629#define PANEL_ENCODER_25FRC_E 0x00 1630#define PANEL_ENCODER_25FRC_F 0x10 1631#define PANEL_ENCODER_50FRC_MASK 0x60 1632#define PANEL_ENCODER_50FRC_A 0x00 1633#define PANEL_ENCODER_50FRC_B 0x20 1634#define PANEL_ENCODER_50FRC_C 0x40 1635#define PANEL_ENCODER_50FRC_D 0x60 1636#define PANEL_ENCODER_75FRC_MASK 0x80 1637#define PANEL_ENCODER_75FRC_E 0x00 1638#define PANEL_ENCODER_75FRC_F 0x80 1639 1640/****************************************************************************/ 1641// Structures used by SetVoltageTable 1642/****************************************************************************/ 1643#define SET_VOLTAGE_TYPE_ASIC_VDDC 1 1644#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 1645#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 1646#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 1647#define SET_VOLTAGE_INIT_MODE 5 1648#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic 1649 1650#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 1651#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 1652#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 1653 1654#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 1655#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 1656#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 1657 1658typedef struct _SET_VOLTAGE_PARAMETERS 1659{ 1660 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 1661 UCHAR ucVoltageMode; // To set all, to set source A or source B or ... 1662 UCHAR ucVoltageIndex; // An index to tell which voltage level 1663 UCHAR ucReserved; 1664}SET_VOLTAGE_PARAMETERS; 1665 1666typedef struct _SET_VOLTAGE_PARAMETERS_V2 1667{ 1668 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 1669 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode 1670 USHORT usVoltageLevel; // real voltage level 1671}SET_VOLTAGE_PARAMETERS_V2; 1672 1673typedef struct _SET_VOLTAGE_PS_ALLOCATION 1674{ 1675 SET_VOLTAGE_PARAMETERS sASICSetVoltage; 1676 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 1677}SET_VOLTAGE_PS_ALLOCATION; 1678 1679/****************************************************************************/ 1680// Structures used by TVEncoderControlTable 1681/****************************************************************************/ 1682typedef struct _TV_ENCODER_CONTROL_PARAMETERS 1683{ 1684 USHORT usPixelClock; // in 10KHz; for bios convenient 1685 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." 1686 UCHAR ucAction; // 0: turn off encoder 1687 // 1: setup and turn on encoder 1688}TV_ENCODER_CONTROL_PARAMETERS; 1689 1690typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION 1691{ 1692 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; 1693 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one 1694}TV_ENCODER_CONTROL_PS_ALLOCATION; 1695 1696//==============================Data Table Portion==================================== 1697 1698/****************************************************************************/ 1699// Structure used in Data.mtb 1700/****************************************************************************/ 1701typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES 1702{ 1703 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! 1704 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 1705 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios 1706 USHORT StandardVESA_Timing; // Only used by Bios 1707 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 1708 USHORT DAC_Info; // Will be obsolete from R600 1709 USHORT LVDS_Info; // Shared by various SW components,latest version 1.1 1710 USHORT TMDS_Info; // Will be obsolete from R600 1711 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 1712 USHORT SupportedDevicesInfo; // Will be obsolete from R600 1713 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 1714 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 1715 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 1716 USHORT VESA_ToInternalModeLUT; // Only used by Bios 1717 USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 1718 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 1719 USHORT CompassionateData; // Will be obsolete from R600 1720 USHORT SaveRestoreInfo; // Only used by Bios 1721 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info 1722 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon 1723 USHORT XTMDS_Info; // Will be obsolete from R600 1724 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used 1725 USHORT Object_Header; // Shared by various SW components,latest version 1.1 1726 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! 1727 USHORT MC_InitParameter; // Only used by command table 1728 USHORT ASIC_VDDC_Info; // Will be obsolete from R600 1729 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" 1730 USHORT TV_VideoMode; // Only used by command table 1731 USHORT VRAM_Info; // Only used by command table, latest version 1.3 1732 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 1733 USHORT IntegratedSystemInfo; // Shared by various SW components 1734 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 1735 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 1736 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 1737}ATOM_MASTER_LIST_OF_DATA_TABLES; 1738 1739typedef struct _ATOM_MASTER_DATA_TABLE 1740{ 1741 ATOM_COMMON_TABLE_HEADER sHeader; 1742 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; 1743}ATOM_MASTER_DATA_TABLE; 1744 1745/****************************************************************************/ 1746// Structure used in MultimediaCapabilityInfoTable 1747/****************************************************************************/ 1748typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO 1749{ 1750 ATOM_COMMON_TABLE_HEADER sHeader; 1751 ULONG ulSignature; // HW info table signature string "$ATI" 1752 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) 1753 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) 1754 UCHAR ucVideoPortInfo; // Provides the video port capabilities 1755 UCHAR ucHostPortInfo; // Provides host port configuration information 1756}ATOM_MULTIMEDIA_CAPABILITY_INFO; 1757 1758/****************************************************************************/ 1759// Structure used in MultimediaConfigInfoTable 1760/****************************************************************************/ 1761typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO 1762{ 1763 ATOM_COMMON_TABLE_HEADER sHeader; 1764 ULONG ulSignature; // MM info table signature sting "$MMT" 1765 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) 1766 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) 1767 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting 1768 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) 1769 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) 1770 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) 1771 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) 1772 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 1773 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 1774 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 1775 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 1776 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 1777}ATOM_MULTIMEDIA_CONFIG_INFO; 1778 1779/****************************************************************************/ 1780// Structures used in FirmwareInfoTable 1781/****************************************************************************/ 1782 1783// usBIOSCapability Defintion: 1784// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 1785// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 1786// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 1787// Others: Reserved 1788#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 1789#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 1790#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 1791#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 1792#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 1793#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 1794#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 1795#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 1796#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 1797#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 1798#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 1799#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 1800#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip 1801#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip 1802 1803#ifndef _H2INC 1804 1805//Please don't add or expand this bitfield structure below, this one will retire soon.! 1806typedef struct _ATOM_FIRMWARE_CAPABILITY 1807{ 1808#if ATOM_BIG_ENDIAN 1809 USHORT Reserved:3; 1810 USHORT HyperMemory_Size:4; 1811 USHORT HyperMemory_Support:1; 1812 USHORT PPMode_Assigned:1; 1813 USHORT WMI_SUPPORT:1; 1814 USHORT GPUControlsBL:1; 1815 USHORT EngineClockSS_Support:1; 1816 USHORT MemoryClockSS_Support:1; 1817 USHORT ExtendedDesktopSupport:1; 1818 USHORT DualCRTC_Support:1; 1819 USHORT FirmwarePosted:1; 1820#else 1821 USHORT FirmwarePosted:1; 1822 USHORT DualCRTC_Support:1; 1823 USHORT ExtendedDesktopSupport:1; 1824 USHORT MemoryClockSS_Support:1; 1825 USHORT EngineClockSS_Support:1; 1826 USHORT GPUControlsBL:1; 1827 USHORT WMI_SUPPORT:1; 1828 USHORT PPMode_Assigned:1; 1829 USHORT HyperMemory_Support:1; 1830 USHORT HyperMemory_Size:4; 1831 USHORT Reserved:3; 1832#endif 1833}ATOM_FIRMWARE_CAPABILITY; 1834 1835typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 1836{ 1837 ATOM_FIRMWARE_CAPABILITY sbfAccess; 1838 USHORT susAccess; 1839}ATOM_FIRMWARE_CAPABILITY_ACCESS; 1840 1841#else 1842 1843typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 1844{ 1845 USHORT susAccess; 1846}ATOM_FIRMWARE_CAPABILITY_ACCESS; 1847 1848#endif 1849 1850typedef struct _ATOM_FIRMWARE_INFO 1851{ 1852 ATOM_COMMON_TABLE_HEADER sHeader; 1853 ULONG ulFirmwareRevision; 1854 ULONG ulDefaultEngineClock; //In 10Khz unit 1855 ULONG ulDefaultMemoryClock; //In 10Khz unit 1856 ULONG ulDriverTargetEngineClock; //In 10Khz unit 1857 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 1858 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 1859 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 1860 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 1861 ULONG ulASICMaxEngineClock; //In 10Khz unit 1862 ULONG ulASICMaxMemoryClock; //In 10Khz unit 1863 UCHAR ucASICMaxTemperature; 1864 UCHAR ucPadding[3]; //Don't use them 1865 ULONG aulReservedForBIOS[3]; //Don't use them 1866 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 1867 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 1868 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 1869 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 1870 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 1871 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 1872 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 1873 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 1874 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 1875 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! 1876 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 1877 USHORT usReferenceClock; //In 10Khz unit 1878 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 1879 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 1880 UCHAR ucDesign_ID; //Indicate what is the board design 1881 UCHAR ucMemoryModule_ID; //Indicate what is the board design 1882}ATOM_FIRMWARE_INFO; 1883 1884typedef struct _ATOM_FIRMWARE_INFO_V1_2 1885{ 1886 ATOM_COMMON_TABLE_HEADER sHeader; 1887 ULONG ulFirmwareRevision; 1888 ULONG ulDefaultEngineClock; //In 10Khz unit 1889 ULONG ulDefaultMemoryClock; //In 10Khz unit 1890 ULONG ulDriverTargetEngineClock; //In 10Khz unit 1891 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 1892 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 1893 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 1894 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 1895 ULONG ulASICMaxEngineClock; //In 10Khz unit 1896 ULONG ulASICMaxMemoryClock; //In 10Khz unit 1897 UCHAR ucASICMaxTemperature; 1898 UCHAR ucMinAllowedBL_Level; 1899 UCHAR ucPadding[2]; //Don't use them 1900 ULONG aulReservedForBIOS[2]; //Don't use them 1901 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 1902 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 1903 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 1904 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 1905 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 1906 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 1907 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 1908 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 1909 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 1910 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 1911 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 1912 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 1913 USHORT usReferenceClock; //In 10Khz unit 1914 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 1915 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 1916 UCHAR ucDesign_ID; //Indicate what is the board design 1917 UCHAR ucMemoryModule_ID; //Indicate what is the board design 1918}ATOM_FIRMWARE_INFO_V1_2; 1919 1920typedef struct _ATOM_FIRMWARE_INFO_V1_3 1921{ 1922 ATOM_COMMON_TABLE_HEADER sHeader; 1923 ULONG ulFirmwareRevision; 1924 ULONG ulDefaultEngineClock; //In 10Khz unit 1925 ULONG ulDefaultMemoryClock; //In 10Khz unit 1926 ULONG ulDriverTargetEngineClock; //In 10Khz unit 1927 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 1928 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 1929 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 1930 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 1931 ULONG ulASICMaxEngineClock; //In 10Khz unit 1932 ULONG ulASICMaxMemoryClock; //In 10Khz unit 1933 UCHAR ucASICMaxTemperature; 1934 UCHAR ucMinAllowedBL_Level; 1935 UCHAR ucPadding[2]; //Don't use them 1936 ULONG aulReservedForBIOS; //Don't use them 1937 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 1938 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 1939 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 1940 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 1941 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 1942 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 1943 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 1944 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 1945 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 1946 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 1947 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 1948 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 1949 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 1950 USHORT usReferenceClock; //In 10Khz unit 1951 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 1952 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 1953 UCHAR ucDesign_ID; //Indicate what is the board design 1954 UCHAR ucMemoryModule_ID; //Indicate what is the board design 1955}ATOM_FIRMWARE_INFO_V1_3; 1956 1957typedef struct _ATOM_FIRMWARE_INFO_V1_4 1958{ 1959 ATOM_COMMON_TABLE_HEADER sHeader; 1960 ULONG ulFirmwareRevision; 1961 ULONG ulDefaultEngineClock; //In 10Khz unit 1962 ULONG ulDefaultMemoryClock; //In 10Khz unit 1963 ULONG ulDriverTargetEngineClock; //In 10Khz unit 1964 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 1965 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 1966 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 1967 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 1968 ULONG ulASICMaxEngineClock; //In 10Khz unit 1969 ULONG ulASICMaxMemoryClock; //In 10Khz unit 1970 UCHAR ucASICMaxTemperature; 1971 UCHAR ucMinAllowedBL_Level; 1972 USHORT usBootUpVDDCVoltage; //In MV unit 1973 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 1974 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 1975 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 1976 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 1977 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 1978 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 1979 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 1980 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 1981 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 1982 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 1983 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 1984 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 1985 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 1986 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 1987 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 1988 USHORT usReferenceClock; //In 10Khz unit 1989 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 1990 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 1991 UCHAR ucDesign_ID; //Indicate what is the board design 1992 UCHAR ucMemoryModule_ID; //Indicate what is the board design 1993}ATOM_FIRMWARE_INFO_V1_4; 1994 1995//the structure below to be used from Cypress 1996typedef struct _ATOM_FIRMWARE_INFO_V2_1 1997{ 1998 ATOM_COMMON_TABLE_HEADER sHeader; 1999 ULONG ulFirmwareRevision; 2000 ULONG ulDefaultEngineClock; //In 10Khz unit 2001 ULONG ulDefaultMemoryClock; //In 10Khz unit 2002 ULONG ulReserved1; 2003 ULONG ulReserved2; 2004 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2005 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2006 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2007 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock 2008 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit 2009 UCHAR ucReserved1; //Was ucASICMaxTemperature; 2010 UCHAR ucMinAllowedBL_Level; 2011 USHORT usBootUpVDDCVoltage; //In MV unit 2012 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2013 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2014 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2015 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2016 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2017 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2018 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2019 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2020 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2021 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2022 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2023 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2024 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2025 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2026 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2027 USHORT usCoreReferenceClock; //In 10Khz unit 2028 USHORT usMemoryReferenceClock; //In 10Khz unit 2029 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2030 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2031 UCHAR ucReserved4[3]; 2032}ATOM_FIRMWARE_INFO_V2_1; 2033 2034 2035#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_1 2036 2037/****************************************************************************/ 2038// Structures used in IntegratedSystemInfoTable 2039/****************************************************************************/ 2040#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 2041#define IGP_CAP_FLAG_AC_CARD 0x4 2042#define IGP_CAP_FLAG_SDVO_CARD 0x8 2043#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 2044 2045typedef struct _ATOM_INTEGRATED_SYSTEM_INFO 2046{ 2047 ATOM_COMMON_TABLE_HEADER sHeader; 2048 ULONG ulBootUpEngineClock; //in 10kHz unit 2049 ULONG ulBootUpMemoryClock; //in 10kHz unit 2050 ULONG ulMaxSystemMemoryClock; //in 10kHz unit 2051 ULONG ulMinSystemMemoryClock; //in 10kHz unit 2052 UCHAR ucNumberOfCyclesInPeriodHi; 2053 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. 2054 USHORT usReserved1; 2055 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage 2056 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage 2057 ULONG ulReserved[2]; 2058 2059 USHORT usFSBClock; //In MHz unit 2060 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable 2061 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card 2062 //Bit[4]==1: P/2 mode, ==0: P/1 mode 2063 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal 2064 USHORT usK8MemoryClock; //in MHz unit 2065 USHORT usK8SyncStartDelay; //in 0.01 us unit 2066 USHORT usK8DataReturnTime; //in 0.01 us unit 2067 UCHAR ucMaxNBVoltage; 2068 UCHAR ucMinNBVoltage; 2069 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved 2070 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 2071 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime 2072 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit 2073 UCHAR ucMaxNBVoltageHigh; 2074 UCHAR ucMinNBVoltageHigh; 2075}ATOM_INTEGRATED_SYSTEM_INFO; 2076 2077/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO 2078ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock 2079 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock 2080ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2081 For AMD IGP,for now this can be 0 2082ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2083 For AMD IGP,for now this can be 0 2084 2085usFSBClock: For Intel IGP,it's FSB Freq 2086 For AMD IGP,it's HT Link Speed 2087 2088usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 2089usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2090usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2091 2092VC:Voltage Control 2093ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2094ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2095 2096ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 2097ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 2098 2099ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2100ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2101 2102 2103usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. 2104usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. 2105*/ 2106 2107 2108/* 2109The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; 2110Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 2111The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. 2112 2113SW components can access the IGP system infor structure in the same way as before 2114*/ 2115 2116 2117typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 2118{ 2119 ATOM_COMMON_TABLE_HEADER sHeader; 2120 ULONG ulBootUpEngineClock; //in 10kHz unit 2121 ULONG ulReserved1[2]; //must be 0x0 for the reserved 2122 ULONG ulBootUpUMAClock; //in 10kHz unit 2123 ULONG ulBootUpSidePortClock; //in 10kHz unit 2124 ULONG ulMinSidePortClock; //in 10kHz unit 2125 ULONG ulReserved2[6]; //must be 0x0 for the reserved 2126 ULONG ulSystemConfig; //see explanation below 2127 ULONG ulBootUpReqDisplayVector; 2128 ULONG ulOtherDisplayMisc; 2129 ULONG ulDDISlot1Config; 2130 ULONG ulDDISlot2Config; 2131 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2132 UCHAR ucUMAChannelNumber; 2133 UCHAR ucDockingPinBit; 2134 UCHAR ucDockingPinPolarity; 2135 ULONG ulDockingPinCFGInfo; 2136 ULONG ulCPUCapInfo; 2137 USHORT usNumberOfCyclesInPeriod; 2138 USHORT usMaxNBVoltage; 2139 USHORT usMinNBVoltage; 2140 USHORT usBootUpNBVoltage; 2141 ULONG ulHTLinkFreq; //in 10Khz 2142 USHORT usMinHTLinkWidth; 2143 USHORT usMaxHTLinkWidth; 2144 USHORT usUMASyncStartDelay; 2145 USHORT usUMADataReturnTime; 2146 USHORT usLinkStatusZeroTime; 2147 USHORT usDACEfuse; //for storing badgap value (for RS880 only) 2148 ULONG ulHighVoltageHTLinkFreq; // in 10Khz 2149 ULONG ulLowVoltageHTLinkFreq; // in 10Khz 2150 USHORT usMaxUpStreamHTLinkWidth; 2151 USHORT usMaxDownStreamHTLinkWidth; 2152 USHORT usMinUpStreamHTLinkWidth; 2153 USHORT usMinDownStreamHTLinkWidth; 2154 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. 2155 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. 2156 ULONG ulReserved3[96]; //must be 0x0 2157}ATOM_INTEGRATED_SYSTEM_INFO_V2; 2158 2159 2160 2161#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 2162#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 2163#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 2164#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 2165#define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 2166#define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 2167#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 2168#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 2169#define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 2170#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 2171 2172#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF 2173 2174#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F 2175#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 2176#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 2177#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 2178#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 2179#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 2180 2181#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 2182#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 2183#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 2184 2185#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 2186 2187// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR 2188typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 2189{ 2190 ATOM_COMMON_TABLE_HEADER sHeader; 2191 ULONG ulBootUpEngineClock; //in 10kHz unit 2192 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 2193 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge 2194 ULONG ulBootUpUMAClock; //in 10kHz unit 2195 ULONG ulReserved1[8]; //must be 0x0 for the reserved 2196 ULONG ulBootUpReqDisplayVector; 2197 ULONG ulOtherDisplayMisc; 2198 ULONG ulReserved2[4]; //must be 0x0 for the reserved 2199 ULONG ulSystemConfig; //TBD 2200 ULONG ulCPUCapInfo; //TBD 2201 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 2202 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 2203 USHORT usBootUpNBVoltage; //boot up NB voltage 2204 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD 2205 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD 2206 ULONG ulReserved3[4]; //must be 0x0 for the reserved 2207 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition 2208 ULONG ulDDISlot2Config; 2209 ULONG ulDDISlot3Config; 2210 ULONG ulDDISlot4Config; 2211 ULONG ulReserved4[4]; //must be 0x0 for the reserved 2212 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2213 UCHAR ucUMAChannelNumber; 2214 USHORT usReserved; 2215 ULONG ulReserved5[4]; //must be 0x0 for the reserved 2216 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default 2217 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback 2218 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications 2219 ULONG ulReserved6[61]; //must be 0x0 2220}ATOM_INTEGRATED_SYSTEM_INFO_V5; 2221 2222#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 2223#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 2224#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 2225#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 2226#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 2227#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 2228#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 2229#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 2230#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 2231#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 2232#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A 2233#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B 2234#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C 2235#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D 2236 2237// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable 2238#define ASIC_INT_DAC1_ENCODER_ID 0x00 2239#define ASIC_INT_TV_ENCODER_ID 0x02 2240#define ASIC_INT_DIG1_ENCODER_ID 0x03 2241#define ASIC_INT_DAC2_ENCODER_ID 0x04 2242#define ASIC_EXT_TV_ENCODER_ID 0x06 2243#define ASIC_INT_DVO_ENCODER_ID 0x07 2244#define ASIC_INT_DIG2_ENCODER_ID 0x09 2245#define ASIC_EXT_DIG_ENCODER_ID 0x05 2246#define ASIC_EXT_DIG2_ENCODER_ID 0x08 2247#define ASIC_INT_DIG3_ENCODER_ID 0x0a 2248#define ASIC_INT_DIG4_ENCODER_ID 0x0b 2249#define ASIC_INT_DIG5_ENCODER_ID 0x0c 2250#define ASIC_INT_DIG6_ENCODER_ID 0x0d 2251 2252//define Encoder attribute 2253#define ATOM_ANALOG_ENCODER 0 2254#define ATOM_DIGITAL_ENCODER 1 2255#define ATOM_DP_ENCODER 2 2256 2257#define ATOM_ENCODER_ENUM_MASK 0x70 2258#define ATOM_ENCODER_ENUM_ID1 0x00 2259#define ATOM_ENCODER_ENUM_ID2 0x10 2260#define ATOM_ENCODER_ENUM_ID3 0x20 2261#define ATOM_ENCODER_ENUM_ID4 0x30 2262#define ATOM_ENCODER_ENUM_ID5 0x40 2263#define ATOM_ENCODER_ENUM_ID6 0x50 2264 2265#define ATOM_DEVICE_CRT1_INDEX 0x00000000 2266#define ATOM_DEVICE_LCD1_INDEX 0x00000001 2267#define ATOM_DEVICE_TV1_INDEX 0x00000002 2268#define ATOM_DEVICE_DFP1_INDEX 0x00000003 2269#define ATOM_DEVICE_CRT2_INDEX 0x00000004 2270#define ATOM_DEVICE_LCD2_INDEX 0x00000005 2271#define ATOM_DEVICE_DFP6_INDEX 0x00000006 2272#define ATOM_DEVICE_DFP2_INDEX 0x00000007 2273#define ATOM_DEVICE_CV_INDEX 0x00000008 2274#define ATOM_DEVICE_DFP3_INDEX 0x00000009 2275#define ATOM_DEVICE_DFP4_INDEX 0x0000000A 2276#define ATOM_DEVICE_DFP5_INDEX 0x0000000B 2277 2278#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C 2279#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D 2280#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E 2281#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F 2282#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) 2283#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO 2284#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) 2285 2286#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) 2287 2288#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) 2289#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) 2290#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) 2291#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) 2292#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) 2293#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) 2294#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) 2295#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) 2296#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) 2297#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) 2298#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) 2299#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) 2300 2301#define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) 2302#define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) 2303#define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT) 2304#define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) 2305 2306#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 2307#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 2308#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 2309#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 2310#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 2311#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 2312#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 2313#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 2314#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 2315#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 2316#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 2317#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A 2318#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B 2319#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E 2320#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F 2321 2322 2323#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F 2324#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 2325#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 2326#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 2327#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 2328#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 2329 2330#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 2331 2332#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F 2333#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 2334 2335#define ATOM_DEVICE_I2C_ID_MASK 0x00000070 2336#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 2337#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 2338#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 2339#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 2340#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 2341 2342#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 2343#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 2344#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 2345#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 2346 2347// usDeviceSupport: 2348// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported 2349// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported 2350// Bit 2 = 0 - no TV1 support= 1- TV1 is supported 2351// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported 2352// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported 2353// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported 2354// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported 2355// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported 2356// Bit 8 = 0 - no CV support= 1- CV is supported 2357// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported 2358// Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported 2359// Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported 2360// 2361// 2362 2363/****************************************************************************/ 2364/* Structure used in MclkSS_InfoTable */ 2365/****************************************************************************/ 2366// ucI2C_ConfigID 2367// [7:0] - I2C LINE Associate ID 2368// = 0 - no I2C 2369// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) 2370// = 0, [6:0]=SW assisted I2C ID 2371// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use 2372// = 2, HW engine for Multimedia use 2373// = 3-7 Reserved for future I2C engines 2374// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C 2375 2376typedef struct _ATOM_I2C_ID_CONFIG 2377{ 2378#if ATOM_BIG_ENDIAN 2379 UCHAR bfHW_Capable:1; 2380 UCHAR bfHW_EngineID:3; 2381 UCHAR bfI2C_LineMux:4; 2382#else 2383 UCHAR bfI2C_LineMux:4; 2384 UCHAR bfHW_EngineID:3; 2385 UCHAR bfHW_Capable:1; 2386#endif 2387}ATOM_I2C_ID_CONFIG; 2388 2389typedef union _ATOM_I2C_ID_CONFIG_ACCESS 2390{ 2391 ATOM_I2C_ID_CONFIG sbfAccess; 2392 UCHAR ucAccess; 2393}ATOM_I2C_ID_CONFIG_ACCESS; 2394 2395 2396/****************************************************************************/ 2397// Structure used in GPIO_I2C_InfoTable 2398/****************************************************************************/ 2399typedef struct _ATOM_GPIO_I2C_ASSIGMENT 2400{ 2401 USHORT usClkMaskRegisterIndex; 2402 USHORT usClkEnRegisterIndex; 2403 USHORT usClkY_RegisterIndex; 2404 USHORT usClkA_RegisterIndex; 2405 USHORT usDataMaskRegisterIndex; 2406 USHORT usDataEnRegisterIndex; 2407 USHORT usDataY_RegisterIndex; 2408 USHORT usDataA_RegisterIndex; 2409 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 2410 UCHAR ucClkMaskShift; 2411 UCHAR ucClkEnShift; 2412 UCHAR ucClkY_Shift; 2413 UCHAR ucClkA_Shift; 2414 UCHAR ucDataMaskShift; 2415 UCHAR ucDataEnShift; 2416 UCHAR ucDataY_Shift; 2417 UCHAR ucDataA_Shift; 2418 UCHAR ucReserved1; 2419 UCHAR ucReserved2; 2420}ATOM_GPIO_I2C_ASSIGMENT; 2421 2422typedef struct _ATOM_GPIO_I2C_INFO 2423{ 2424 ATOM_COMMON_TABLE_HEADER sHeader; 2425 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; 2426}ATOM_GPIO_I2C_INFO; 2427 2428/****************************************************************************/ 2429// Common Structure used in other structures 2430/****************************************************************************/ 2431 2432#ifndef _H2INC 2433 2434//Please don't add or expand this bitfield structure below, this one will retire soon.! 2435typedef struct _ATOM_MODE_MISC_INFO 2436{ 2437#if ATOM_BIG_ENDIAN 2438 USHORT Reserved:6; 2439 USHORT RGB888:1; 2440 USHORT DoubleClock:1; 2441 USHORT Interlace:1; 2442 USHORT CompositeSync:1; 2443 USHORT V_ReplicationBy2:1; 2444 USHORT H_ReplicationBy2:1; 2445 USHORT VerticalCutOff:1; 2446 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 2447 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 2448 USHORT HorizontalCutOff:1; 2449#else 2450 USHORT HorizontalCutOff:1; 2451 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 2452 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 2453 USHORT VerticalCutOff:1; 2454 USHORT H_ReplicationBy2:1; 2455 USHORT V_ReplicationBy2:1; 2456 USHORT CompositeSync:1; 2457 USHORT Interlace:1; 2458 USHORT DoubleClock:1; 2459 USHORT RGB888:1; 2460 USHORT Reserved:6; 2461#endif 2462}ATOM_MODE_MISC_INFO; 2463 2464typedef union _ATOM_MODE_MISC_INFO_ACCESS 2465{ 2466 ATOM_MODE_MISC_INFO sbfAccess; 2467 USHORT usAccess; 2468}ATOM_MODE_MISC_INFO_ACCESS; 2469 2470#else 2471 2472typedef union _ATOM_MODE_MISC_INFO_ACCESS 2473{ 2474 USHORT usAccess; 2475}ATOM_MODE_MISC_INFO_ACCESS; 2476 2477#endif 2478 2479// usModeMiscInfo- 2480#define ATOM_H_CUTOFF 0x01 2481#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low 2482#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low 2483#define ATOM_V_CUTOFF 0x08 2484#define ATOM_H_REPLICATIONBY2 0x10 2485#define ATOM_V_REPLICATIONBY2 0x20 2486#define ATOM_COMPOSITESYNC 0x40 2487#define ATOM_INTERLACE 0x80 2488#define ATOM_DOUBLE_CLOCK_MODE 0x100 2489#define ATOM_RGB888_MODE 0x200 2490 2491//usRefreshRate- 2492#define ATOM_REFRESH_43 43 2493#define ATOM_REFRESH_47 47 2494#define ATOM_REFRESH_56 56 2495#define ATOM_REFRESH_60 60 2496#define ATOM_REFRESH_65 65 2497#define ATOM_REFRESH_70 70 2498#define ATOM_REFRESH_72 72 2499#define ATOM_REFRESH_75 75 2500#define ATOM_REFRESH_85 85 2501 2502// ATOM_MODE_TIMING data are exactly the same as VESA timing data. 2503// Translation from EDID to ATOM_MODE_TIMING, use the following formula. 2504// 2505// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK 2506// = EDID_HA + EDID_HBL 2507// VESA_HDISP = VESA_ACTIVE = EDID_HA 2508// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH 2509// = EDID_HA + EDID_HSO 2510// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW 2511// VESA_BORDER = EDID_BORDER 2512 2513/****************************************************************************/ 2514// Structure used in SetCRTC_UsingDTDTimingTable 2515/****************************************************************************/ 2516typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS 2517{ 2518 USHORT usH_Size; 2519 USHORT usH_Blanking_Time; 2520 USHORT usV_Size; 2521 USHORT usV_Blanking_Time; 2522 USHORT usH_SyncOffset; 2523 USHORT usH_SyncWidth; 2524 USHORT usV_SyncOffset; 2525 USHORT usV_SyncWidth; 2526 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 2527 UCHAR ucH_Border; // From DFP EDID 2528 UCHAR ucV_Border; 2529 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 2530 UCHAR ucPadding[3]; 2531}SET_CRTC_USING_DTD_TIMING_PARAMETERS; 2532 2533/****************************************************************************/ 2534// Structure used in SetCRTC_TimingTable 2535/****************************************************************************/ 2536typedef struct _SET_CRTC_TIMING_PARAMETERS 2537{ 2538 USHORT usH_Total; // horizontal total 2539 USHORT usH_Disp; // horizontal display 2540 USHORT usH_SyncStart; // horozontal Sync start 2541 USHORT usH_SyncWidth; // horizontal Sync width 2542 USHORT usV_Total; // vertical total 2543 USHORT usV_Disp; // vertical display 2544 USHORT usV_SyncStart; // vertical Sync start 2545 USHORT usV_SyncWidth; // vertical Sync width 2546 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 2547 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 2548 UCHAR ucOverscanRight; // right 2549 UCHAR ucOverscanLeft; // left 2550 UCHAR ucOverscanBottom; // bottom 2551 UCHAR ucOverscanTop; // top 2552 UCHAR ucReserved; 2553}SET_CRTC_TIMING_PARAMETERS; 2554#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS 2555 2556/****************************************************************************/ 2557// Structure used in StandardVESA_TimingTable 2558// AnalogTV_InfoTable 2559// ComponentVideoInfoTable 2560/****************************************************************************/ 2561typedef struct _ATOM_MODE_TIMING 2562{ 2563 USHORT usCRTC_H_Total; 2564 USHORT usCRTC_H_Disp; 2565 USHORT usCRTC_H_SyncStart; 2566 USHORT usCRTC_H_SyncWidth; 2567 USHORT usCRTC_V_Total; 2568 USHORT usCRTC_V_Disp; 2569 USHORT usCRTC_V_SyncStart; 2570 USHORT usCRTC_V_SyncWidth; 2571 USHORT usPixelClock; //in 10Khz unit 2572 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 2573 USHORT usCRTC_OverscanRight; 2574 USHORT usCRTC_OverscanLeft; 2575 USHORT usCRTC_OverscanBottom; 2576 USHORT usCRTC_OverscanTop; 2577 USHORT usReserve; 2578 UCHAR ucInternalModeNumber; 2579 UCHAR ucRefreshRate; 2580}ATOM_MODE_TIMING; 2581 2582typedef struct _ATOM_DTD_FORMAT 2583{ 2584 USHORT usPixClk; 2585 USHORT usHActive; 2586 USHORT usHBlanking_Time; 2587 USHORT usVActive; 2588 USHORT usVBlanking_Time; 2589 USHORT usHSyncOffset; 2590 USHORT usHSyncWidth; 2591 USHORT usVSyncOffset; 2592 USHORT usVSyncWidth; 2593 USHORT usImageHSize; 2594 USHORT usImageVSize; 2595 UCHAR ucHBorder; 2596 UCHAR ucVBorder; 2597 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 2598 UCHAR ucInternalModeNumber; 2599 UCHAR ucRefreshRate; 2600}ATOM_DTD_FORMAT; 2601 2602/****************************************************************************/ 2603// Structure used in LVDS_InfoTable 2604// * Need a document to describe this table 2605/****************************************************************************/ 2606#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 2607#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 2608#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 2609#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 2610 2611//ucTableFormatRevision=1 2612//ucTableContentRevision=1 2613typedef struct _ATOM_LVDS_INFO 2614{ 2615 ATOM_COMMON_TABLE_HEADER sHeader; 2616 ATOM_DTD_FORMAT sLCDTiming; 2617 USHORT usModePatchTableOffset; 2618 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 2619 USHORT usOffDelayInMs; 2620 UCHAR ucPowerSequenceDigOntoDEin10Ms; 2621 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 2622 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 2623 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 2624 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 2625 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 2626 UCHAR ucPanelDefaultRefreshRate; 2627 UCHAR ucPanelIdentification; 2628 UCHAR ucSS_Id; 2629}ATOM_LVDS_INFO; 2630 2631//ucTableFormatRevision=1 2632//ucTableContentRevision=2 2633typedef struct _ATOM_LVDS_INFO_V12 2634{ 2635 ATOM_COMMON_TABLE_HEADER sHeader; 2636 ATOM_DTD_FORMAT sLCDTiming; 2637 USHORT usExtInfoTableOffset; 2638 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 2639 USHORT usOffDelayInMs; 2640 UCHAR ucPowerSequenceDigOntoDEin10Ms; 2641 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 2642 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 2643 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 2644 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 2645 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 2646 UCHAR ucPanelDefaultRefreshRate; 2647 UCHAR ucPanelIdentification; 2648 UCHAR ucSS_Id; 2649 USHORT usLCDVenderID; 2650 USHORT usLCDProductID; 2651 UCHAR ucLCDPanel_SpecialHandlingCap; 2652 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 2653 UCHAR ucReserved[2]; 2654}ATOM_LVDS_INFO_V12; 2655 2656//Definitions for ucLCDPanel_SpecialHandlingCap: 2657 2658//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 2659//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 2660#define LCDPANEL_CAP_READ_EDID 0x1 2661 2662//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 2663//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 2664//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 2665#define LCDPANEL_CAP_DRR_SUPPORTED 0x2 2666 2667//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 2668#define LCDPANEL_CAP_eDP 0x4 2669 2670 2671//Color Bit Depth definition in EDID V1.4 @BYTE 14h 2672//Bit 6 5 4 2673 // 0 0 0 - Color bit depth is undefined 2674 // 0 0 1 - 6 Bits per Primary Color 2675 // 0 1 0 - 8 Bits per Primary Color 2676 // 0 1 1 - 10 Bits per Primary Color 2677 // 1 0 0 - 12 Bits per Primary Color 2678 // 1 0 1 - 14 Bits per Primary Color 2679 // 1 1 0 - 16 Bits per Primary Color 2680 // 1 1 1 - Reserved 2681 2682#define PANEL_COLOR_BIT_DEPTH_MASK 0x70 2683 2684// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} 2685#define PANEL_RANDOM_DITHER 0x80 2686#define PANEL_RANDOM_DITHER_MASK 0x80 2687 2688 2689#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 2690 2691typedef struct _ATOM_PATCH_RECORD_MODE 2692{ 2693 UCHAR ucRecordType; 2694 USHORT usHDisp; 2695 USHORT usVDisp; 2696}ATOM_PATCH_RECORD_MODE; 2697 2698typedef struct _ATOM_LCD_RTS_RECORD 2699{ 2700 UCHAR ucRecordType; 2701 UCHAR ucRTSValue; 2702}ATOM_LCD_RTS_RECORD; 2703 2704//!! If the record below exits, it shoud always be the first record for easy use in command table!!! 2705// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. 2706typedef struct _ATOM_LCD_MODE_CONTROL_CAP 2707{ 2708 UCHAR ucRecordType; 2709 USHORT usLCDCap; 2710}ATOM_LCD_MODE_CONTROL_CAP; 2711 2712#define LCD_MODE_CAP_BL_OFF 1 2713#define LCD_MODE_CAP_CRTC_OFF 2 2714#define LCD_MODE_CAP_PANEL_OFF 4 2715 2716typedef struct _ATOM_FAKE_EDID_PATCH_RECORD 2717{ 2718 UCHAR ucRecordType; 2719 UCHAR ucFakeEDIDLength; 2720 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. 2721} ATOM_FAKE_EDID_PATCH_RECORD; 2722 2723typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD 2724{ 2725 UCHAR ucRecordType; 2726 USHORT usHSize; 2727 USHORT usVSize; 2728}ATOM_PANEL_RESOLUTION_PATCH_RECORD; 2729 2730#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 2731#define LCD_RTS_RECORD_TYPE 2 2732#define LCD_CAP_RECORD_TYPE 3 2733#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 2734#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 2735#define ATOM_RECORD_END_TYPE 0xFF 2736 2737/****************************Spread Spectrum Info Table Definitions **********************/ 2738 2739//ucTableFormatRevision=1 2740//ucTableContentRevision=2 2741typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT 2742{ 2743 USHORT usSpreadSpectrumPercentage; 2744 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD 2745 UCHAR ucSS_Step; 2746 UCHAR ucSS_Delay; 2747 UCHAR ucSS_Id; 2748 UCHAR ucRecommendedRef_Div; 2749 UCHAR ucSS_Range; //it was reserved for V11 2750}ATOM_SPREAD_SPECTRUM_ASSIGNMENT; 2751 2752#define ATOM_MAX_SS_ENTRY 16 2753#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. 2754#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. 2755#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz 2756#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz 2757 2758 2759#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 2760#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 2761#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 2762#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 2763#define ATOM_INTERNAL_SS_MASK 0x00000000 2764#define ATOM_EXTERNAL_SS_MASK 0x00000002 2765#define EXEC_SS_STEP_SIZE_SHIFT 2 2766#define EXEC_SS_DELAY_SHIFT 4 2767#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 2768 2769typedef struct _ATOM_SPREAD_SPECTRUM_INFO 2770{ 2771 ATOM_COMMON_TABLE_HEADER sHeader; 2772 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; 2773}ATOM_SPREAD_SPECTRUM_INFO; 2774 2775/****************************************************************************/ 2776// Structure used in AnalogTV_InfoTable (Top level) 2777/****************************************************************************/ 2778//ucTVBootUpDefaultStd definiton: 2779 2780//ATOM_TV_NTSC 1 2781//ATOM_TV_NTSCJ 2 2782//ATOM_TV_PAL 3 2783//ATOM_TV_PALM 4 2784//ATOM_TV_PALCN 5 2785//ATOM_TV_PALN 6 2786//ATOM_TV_PAL60 7 2787//ATOM_TV_SECAM 8 2788 2789//ucTVSupportedStd definition: 2790#define NTSC_SUPPORT 0x1 2791#define NTSCJ_SUPPORT 0x2 2792 2793#define PAL_SUPPORT 0x4 2794#define PALM_SUPPORT 0x8 2795#define PALCN_SUPPORT 0x10 2796#define PALN_SUPPORT 0x20 2797#define PAL60_SUPPORT 0x40 2798#define SECAM_SUPPORT 0x80 2799 2800#define MAX_SUPPORTED_TV_TIMING 2 2801 2802typedef struct _ATOM_ANALOG_TV_INFO 2803{ 2804 ATOM_COMMON_TABLE_HEADER sHeader; 2805 UCHAR ucTV_SupportedStandard; 2806 UCHAR ucTV_BootUpDefaultStandard; 2807 UCHAR ucExt_TV_ASIC_ID; 2808 UCHAR ucExt_TV_ASIC_SlaveAddr; 2809 /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ 2810 ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; 2811}ATOM_ANALOG_TV_INFO; 2812 2813#define MAX_SUPPORTED_TV_TIMING_V1_2 3 2814 2815typedef struct _ATOM_ANALOG_TV_INFO_V1_2 2816{ 2817 ATOM_COMMON_TABLE_HEADER sHeader; 2818 UCHAR ucTV_SupportedStandard; 2819 UCHAR ucTV_BootUpDefaultStandard; 2820 UCHAR ucExt_TV_ASIC_ID; 2821 UCHAR ucExt_TV_ASIC_SlaveAddr; 2822 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2]; 2823}ATOM_ANALOG_TV_INFO_V1_2; 2824 2825typedef struct _ATOM_DPCD_INFO 2826{ 2827 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 2828 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane 2829 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP 2830 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) 2831}ATOM_DPCD_INFO; 2832 2833#define ATOM_DPCD_MAX_LANE_MASK 0x1F 2834 2835/**************************************************************************/ 2836// VRAM usage and their defintions 2837 2838// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. 2839// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. 2840// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! 2841// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR 2842// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX 2843 2844#ifndef VESA_MEMORY_IN_64K_BLOCK 2845#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) 2846#endif 2847 2848#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes 2849#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes 2850#define ATOM_HWICON_INFOTABLE_SIZE 32 2851#define MAX_DTD_MODE_IN_VRAM 6 2852#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) 2853#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) 2854#define DFP_ENCODER_TYPE_OFFSET 0x80 2855#define DP_ENCODER_LANE_NUM_OFFSET 0x84 2856#define DP_ENCODER_LINK_RATE_OFFSET 0x88 2857 2858#define ATOM_HWICON1_SURFACE_ADDR 0 2859#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 2860#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 2861#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) 2862#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 2863#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 2864 2865#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 2866#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 2867#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 2868 2869#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 2870 2871#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 2872#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 2873#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 2874 2875#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 2876#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 2877#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 2878 2879#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 2880#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 2881#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 2882 2883#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 2884#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 2885#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 2886 2887#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 2888#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 2889#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 2890 2891#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 2892#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 2893#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 2894 2895#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 2896#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 2897#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 2898 2899#define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 2900#define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 2901#define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 2902 2903#define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 2904#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 2905#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 2906 2907#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE) 2908 2909#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR+256) 2910#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START+512 2911 2912//The size below is in Kb! 2913#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) 2914 2915#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L 2916#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 2917#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 2918#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 2919 2920/***********************************************************************************/ 2921// Structure used in VRAM_UsageByFirmwareTable 2922// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm 2923// at running time. 2924// note2: From RV770, the memory is more than 32bit addressable, so we will change 2925// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains 2926// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware 2927// (in offset to start of memory address) is KB aligned instead of byte aligend. 2928/***********************************************************************************/ 2929// Note3: 2930/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, 2931for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: 2932 2933If (ulStartAddrUsedByFirmware!=0) 2934FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; 2935Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose 2936else //Non VGA case 2937 if (FB_Size<=2Gb) 2938 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; 2939 else 2940 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB 2941 2942CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ 2943 2944#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 2945 2946typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO 2947{ 2948 ULONG ulStartAddrUsedByFirmware; 2949 USHORT usFirmwareUseInKb; 2950 USHORT usReserved; 2951}ATOM_FIRMWARE_VRAM_RESERVE_INFO; 2952 2953typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE 2954{ 2955 ATOM_COMMON_TABLE_HEADER sHeader; 2956 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 2957}ATOM_VRAM_USAGE_BY_FIRMWARE; 2958 2959// change verion to 1.5, when allow driver to allocate the vram area for command table access. 2960typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 2961{ 2962 ULONG ulStartAddrUsedByFirmware; 2963 USHORT usFirmwareUseInKb; 2964 USHORT usFBUsedByDrvInKb; 2965}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; 2966 2967typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 2968{ 2969 ATOM_COMMON_TABLE_HEADER sHeader; 2970 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 2971}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; 2972 2973/****************************************************************************/ 2974// Structure used in GPIO_Pin_LUTTable 2975/****************************************************************************/ 2976typedef struct _ATOM_GPIO_PIN_ASSIGNMENT 2977{ 2978 USHORT usGpioPin_AIndex; 2979 UCHAR ucGpioPinBitShift; 2980 UCHAR ucGPIO_ID; 2981}ATOM_GPIO_PIN_ASSIGNMENT; 2982 2983typedef struct _ATOM_GPIO_PIN_LUT 2984{ 2985 ATOM_COMMON_TABLE_HEADER sHeader; 2986 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; 2987}ATOM_GPIO_PIN_LUT; 2988 2989/****************************************************************************/ 2990// Structure used in ComponentVideoInfoTable 2991/****************************************************************************/ 2992#define GPIO_PIN_ACTIVE_HIGH 0x1 2993 2994#define MAX_SUPPORTED_CV_STANDARDS 5 2995 2996// definitions for ATOM_D_INFO.ucSettings 2997#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] 2998#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out 2999#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] 3000 3001typedef struct _ATOM_GPIO_INFO 3002{ 3003 USHORT usAOffset; 3004 UCHAR ucSettings; 3005 UCHAR ucReserved; 3006}ATOM_GPIO_INFO; 3007 3008// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) 3009#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 3010 3011// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i 3012#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; 3013#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] 3014 3015// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode 3016//Line 3 out put 5V. 3017#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 3018#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 3019#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 3020 3021//Line 3 out put 2.2V 3022#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box 3023#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box 3024#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 3025 3026//Line 3 out put 0V 3027#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 3028#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 3029#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 3030 3031#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] 3032 3033#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 3034 3035//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. 3036#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3037#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3038 3039 3040typedef struct _ATOM_COMPONENT_VIDEO_INFO 3041{ 3042 ATOM_COMMON_TABLE_HEADER sHeader; 3043 USHORT usMask_PinRegisterIndex; 3044 USHORT usEN_PinRegisterIndex; 3045 USHORT usY_PinRegisterIndex; 3046 USHORT usA_PinRegisterIndex; 3047 UCHAR ucBitShift; 3048 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low 3049 ATOM_DTD_FORMAT sReserved; // must be zeroed out 3050 UCHAR ucMiscInfo; 3051 UCHAR uc480i; 3052 UCHAR uc480p; 3053 UCHAR uc720p; 3054 UCHAR uc1080i; 3055 UCHAR ucLetterBoxMode; 3056 UCHAR ucReserved[3]; 3057 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3058 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3059 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3060}ATOM_COMPONENT_VIDEO_INFO; 3061 3062//ucTableFormatRevision=2 3063//ucTableContentRevision=1 3064typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 3065{ 3066 ATOM_COMMON_TABLE_HEADER sHeader; 3067 UCHAR ucMiscInfo; 3068 UCHAR uc480i; 3069 UCHAR uc480p; 3070 UCHAR uc720p; 3071 UCHAR uc1080i; 3072 UCHAR ucReserved; 3073 UCHAR ucLetterBoxMode; 3074 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3075 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3076 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3077}ATOM_COMPONENT_VIDEO_INFO_V21; 3078 3079#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 3080 3081/****************************************************************************/ 3082// Structure used in object_InfoTable 3083/****************************************************************************/ 3084typedef struct _ATOM_OBJECT_HEADER 3085{ 3086 ATOM_COMMON_TABLE_HEADER sHeader; 3087 USHORT usDeviceSupport; 3088 USHORT usConnectorObjectTableOffset; 3089 USHORT usRouterObjectTableOffset; 3090 USHORT usEncoderObjectTableOffset; 3091 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 3092 USHORT usDisplayPathTableOffset; 3093}ATOM_OBJECT_HEADER; 3094 3095typedef struct _ATOM_OBJECT_HEADER_V3 3096{ 3097 ATOM_COMMON_TABLE_HEADER sHeader; 3098 USHORT usDeviceSupport; 3099 USHORT usConnectorObjectTableOffset; 3100 USHORT usRouterObjectTableOffset; 3101 USHORT usEncoderObjectTableOffset; 3102 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 3103 USHORT usDisplayPathTableOffset; 3104 USHORT usMiscObjectTableOffset; 3105}ATOM_OBJECT_HEADER_V3; 3106 3107typedef struct _ATOM_DISPLAY_OBJECT_PATH 3108{ 3109 USHORT usDeviceTag; //supported device 3110 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 3111 USHORT usConnObjectId; //Connector Object ID 3112 USHORT usGPUObjectId; //GPU ID 3113 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. 3114}ATOM_DISPLAY_OBJECT_PATH; 3115 3116typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE 3117{ 3118 UCHAR ucNumOfDispPath; 3119 UCHAR ucVersion; 3120 UCHAR ucPadding[2]; 3121 ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; 3122}ATOM_DISPLAY_OBJECT_PATH_TABLE; 3123 3124 3125typedef struct _ATOM_OBJECT //each object has this structure 3126{ 3127 USHORT usObjectID; 3128 USHORT usSrcDstTableOffset; 3129 USHORT usRecordOffset; //this pointing to a bunch of records defined below 3130 USHORT usReserved; 3131}ATOM_OBJECT; 3132 3133typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure 3134{ 3135 UCHAR ucNumberOfObjects; 3136 UCHAR ucPadding[3]; 3137 ATOM_OBJECT asObjects[1]; 3138}ATOM_OBJECT_TABLE; 3139 3140typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure 3141{ 3142 UCHAR ucNumberOfSrc; 3143 USHORT usSrcObjectID[1]; 3144 UCHAR ucNumberOfDst; 3145 USHORT usDstObjectID[1]; 3146}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; 3147 3148 3149//Two definitions below are for OPM on MXM module designs 3150 3151#define EXT_HPDPIN_LUTINDEX_0 0 3152#define EXT_HPDPIN_LUTINDEX_1 1 3153#define EXT_HPDPIN_LUTINDEX_2 2 3154#define EXT_HPDPIN_LUTINDEX_3 3 3155#define EXT_HPDPIN_LUTINDEX_4 4 3156#define EXT_HPDPIN_LUTINDEX_5 5 3157#define EXT_HPDPIN_LUTINDEX_6 6 3158#define EXT_HPDPIN_LUTINDEX_7 7 3159#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) 3160 3161#define EXT_AUXDDC_LUTINDEX_0 0 3162#define EXT_AUXDDC_LUTINDEX_1 1 3163#define EXT_AUXDDC_LUTINDEX_2 2 3164#define EXT_AUXDDC_LUTINDEX_3 3 3165#define EXT_AUXDDC_LUTINDEX_4 4 3166#define EXT_AUXDDC_LUTINDEX_5 5 3167#define EXT_AUXDDC_LUTINDEX_6 6 3168#define EXT_AUXDDC_LUTINDEX_7 7 3169#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) 3170 3171typedef struct _EXT_DISPLAY_PATH 3172{ 3173 USHORT usDeviceTag; //A bit vector to show what devices are supported 3174 USHORT usDeviceACPIEnum; //16bit device ACPI id. 3175 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions 3176 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT 3177 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT 3178 USHORT usExtEncoderObjId; //external encoder object id 3179 USHORT usReserved[3]; 3180}EXT_DISPLAY_PATH; 3181 3182#define NUMBER_OF_UCHAR_FOR_GUID 16 3183#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 3184 3185typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO 3186{ 3187 ATOM_COMMON_TABLE_HEADER sHeader; 3188 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string 3189 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. 3190 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. 3191 UCHAR Reserved [7]; // for potential expansion 3192}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 3193 3194//Related definitions, all records are differnt but they have a commond header 3195typedef struct _ATOM_COMMON_RECORD_HEADER 3196{ 3197 UCHAR ucRecordType; //An emun to indicate the record type 3198 UCHAR ucRecordSize; //The size of the whole record in byte 3199}ATOM_COMMON_RECORD_HEADER; 3200 3201 3202#define ATOM_I2C_RECORD_TYPE 1 3203#define ATOM_HPD_INT_RECORD_TYPE 2 3204#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 3205#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 3206#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 3207#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 3208#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 3209#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 3210#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 3211#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 3212#define ATOM_CONNECTOR_CF_RECORD_TYPE 11 3213#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 3214#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 3215#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 3216#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 3217#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table 3218#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table 3219#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 3220#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 3221 3222 3223//Must be updated when new record type is added,equal to that record definition! 3224#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 3225 3226typedef struct _ATOM_I2C_RECORD 3227{ 3228 ATOM_COMMON_RECORD_HEADER sheader; 3229 ATOM_I2C_ID_CONFIG sucI2cId; 3230 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC 3231}ATOM_I2C_RECORD; 3232 3233typedef struct _ATOM_HPD_INT_RECORD 3234{ 3235 ATOM_COMMON_RECORD_HEADER sheader; 3236 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 3237 UCHAR ucPlugged_PinState; 3238}ATOM_HPD_INT_RECORD; 3239 3240 3241typedef struct _ATOM_OUTPUT_PROTECTION_RECORD 3242{ 3243 ATOM_COMMON_RECORD_HEADER sheader; 3244 UCHAR ucProtectionFlag; 3245 UCHAR ucReserved; 3246}ATOM_OUTPUT_PROTECTION_RECORD; 3247 3248typedef struct _ATOM_CONNECTOR_DEVICE_TAG 3249{ 3250 ULONG ulACPIDeviceEnum; //Reserved for now 3251 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" 3252 USHORT usPadding; 3253}ATOM_CONNECTOR_DEVICE_TAG; 3254 3255typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD 3256{ 3257 ATOM_COMMON_RECORD_HEADER sheader; 3258 UCHAR ucNumberOfDevice; 3259 UCHAR ucReserved; 3260 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation 3261}ATOM_CONNECTOR_DEVICE_TAG_RECORD; 3262 3263 3264typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD 3265{ 3266 ATOM_COMMON_RECORD_HEADER sheader; 3267 UCHAR ucConfigGPIOID; 3268 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in 3269 UCHAR ucFlowinGPIPID; 3270 UCHAR ucExtInGPIPID; 3271}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; 3272 3273typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD 3274{ 3275 ATOM_COMMON_RECORD_HEADER sheader; 3276 UCHAR ucCTL1GPIO_ID; 3277 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high 3278 UCHAR ucCTL2GPIO_ID; 3279 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high 3280 UCHAR ucCTL3GPIO_ID; 3281 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high 3282 UCHAR ucCTLFPGA_IN_ID; 3283 UCHAR ucPadding[3]; 3284}ATOM_ENCODER_FPGA_CONTROL_RECORD; 3285 3286typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD 3287{ 3288 ATOM_COMMON_RECORD_HEADER sheader; 3289 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 3290 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected 3291}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; 3292 3293typedef struct _ATOM_JTAG_RECORD 3294{ 3295 ATOM_COMMON_RECORD_HEADER sheader; 3296 UCHAR ucTMSGPIO_ID; 3297 UCHAR ucTMSGPIOState; //Set to 1 when it's active high 3298 UCHAR ucTCKGPIO_ID; 3299 UCHAR ucTCKGPIOState; //Set to 1 when it's active high 3300 UCHAR ucTDOGPIO_ID; 3301 UCHAR ucTDOGPIOState; //Set to 1 when it's active high 3302 UCHAR ucTDIGPIO_ID; 3303 UCHAR ucTDIGPIOState; //Set to 1 when it's active high 3304 UCHAR ucPadding[2]; 3305}ATOM_JTAG_RECORD; 3306 3307 3308//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 3309typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR 3310{ 3311 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table 3312 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin 3313}ATOM_GPIO_PIN_CONTROL_PAIR; 3314 3315typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD 3316{ 3317 ATOM_COMMON_RECORD_HEADER sheader; 3318 UCHAR ucFlags; // Future expnadibility 3319 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object 3320 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 3321}ATOM_OBJECT_GPIO_CNTL_RECORD; 3322 3323//Definitions for GPIO pin state 3324#define GPIO_PIN_TYPE_INPUT 0x00 3325#define GPIO_PIN_TYPE_OUTPUT 0x10 3326#define GPIO_PIN_TYPE_HW_CONTROL 0x20 3327 3328//For GPIO_PIN_TYPE_OUTPUT the following is defined 3329#define GPIO_PIN_OUTPUT_STATE_MASK 0x01 3330#define GPIO_PIN_OUTPUT_STATE_SHIFT 0 3331#define GPIO_PIN_STATE_ACTIVE_LOW 0x0 3332#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 3333 3334// Indexes to GPIO array in GLSync record 3335#define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 3336#define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 3337#define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 3338#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 3339#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 3340#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 3341#define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 3342#define ATOM_GPIO_INDEX_GLSYNC_MAX 7 3343 3344typedef struct _ATOM_ENCODER_DVO_CF_RECORD 3345{ 3346 ATOM_COMMON_RECORD_HEADER sheader; 3347 ULONG ulStrengthControl; // DVOA strength control for CF 3348 UCHAR ucPadding[2]; 3349}ATOM_ENCODER_DVO_CF_RECORD; 3350 3351// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle 3352#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 3353#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 3354 3355typedef struct _ATOM_CONNECTOR_CF_RECORD 3356{ 3357 ATOM_COMMON_RECORD_HEADER sheader; 3358 USHORT usMaxPixClk; 3359 UCHAR ucFlowCntlGpioId; 3360 UCHAR ucSwapCntlGpioId; 3361 UCHAR ucConnectedDvoBundle; 3362 UCHAR ucPadding; 3363}ATOM_CONNECTOR_CF_RECORD; 3364 3365typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD 3366{ 3367 ATOM_COMMON_RECORD_HEADER sheader; 3368 ATOM_DTD_FORMAT asTiming; 3369}ATOM_CONNECTOR_HARDCODE_DTD_RECORD; 3370 3371typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD 3372{ 3373 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 3374 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A 3375 UCHAR ucReserved; 3376}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; 3377 3378 3379typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD 3380{ 3381 ATOM_COMMON_RECORD_HEADER sheader; 3382 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state 3383 UCHAR ucMuxControlPin; 3384 UCHAR ucMuxState[2]; //for alligment purpose 3385}ATOM_ROUTER_DDC_PATH_SELECT_RECORD; 3386 3387typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD 3388{ 3389 ATOM_COMMON_RECORD_HEADER sheader; 3390 UCHAR ucMuxType; 3391 UCHAR ucMuxControlPin; 3392 UCHAR ucMuxState[2]; //for alligment purpose 3393}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; 3394 3395// define ucMuxType 3396#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f 3397#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 3398 3399typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 3400{ 3401 ATOM_COMMON_RECORD_HEADER sheader; 3402 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table 3403}ATOM_CONNECTOR_HPDPIN_LUT_RECORD; 3404 3405typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 3406{ 3407 ATOM_COMMON_RECORD_HEADER sheader; 3408 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID 3409}ATOM_CONNECTOR_AUXDDC_LUT_RECORD; 3410 3411typedef struct _ATOM_OBJECT_LINK_RECORD 3412{ 3413 ATOM_COMMON_RECORD_HEADER sheader; 3414 USHORT usObjectID; //could be connector, encorder or other object in object.h 3415}ATOM_OBJECT_LINK_RECORD; 3416 3417typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD 3418{ 3419 ATOM_COMMON_RECORD_HEADER sheader; 3420 USHORT usReserved; 3421}ATOM_CONNECTOR_REMOTE_CAP_RECORD; 3422 3423/****************************************************************************/ 3424// ASIC voltage data table 3425/****************************************************************************/ 3426typedef struct _ATOM_VOLTAGE_INFO_HEADER 3427{ 3428 USHORT usVDDCBaseLevel; //In number of 50mv unit 3429 USHORT usReserved; //For possible extension table offset 3430 UCHAR ucNumOfVoltageEntries; 3431 UCHAR ucBytesPerVoltageEntry; 3432 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit 3433 UCHAR ucDefaultVoltageEntry; 3434 UCHAR ucVoltageControlI2cLine; 3435 UCHAR ucVoltageControlAddress; 3436 UCHAR ucVoltageControlOffset; 3437}ATOM_VOLTAGE_INFO_HEADER; 3438 3439typedef struct _ATOM_VOLTAGE_INFO 3440{ 3441 ATOM_COMMON_TABLE_HEADER sHeader; 3442 ATOM_VOLTAGE_INFO_HEADER viHeader; 3443 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry 3444}ATOM_VOLTAGE_INFO; 3445 3446 3447typedef struct _ATOM_VOLTAGE_FORMULA 3448{ 3449 USHORT usVoltageBaseLevel; // In number of 1mv unit 3450 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit 3451 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 3452 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv 3453 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep 3454 UCHAR ucReserved; 3455 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries 3456}ATOM_VOLTAGE_FORMULA; 3457 3458typedef struct _VOLTAGE_LUT_ENTRY 3459{ 3460 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code 3461 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 3462}VOLTAGE_LUT_ENTRY; 3463 3464typedef struct _ATOM_VOLTAGE_FORMULA_V2 3465{ 3466 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 3467 UCHAR ucReserved[3]; 3468 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries 3469}ATOM_VOLTAGE_FORMULA_V2; 3470 3471typedef struct _ATOM_VOLTAGE_CONTROL 3472{ 3473 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine 3474 UCHAR ucVoltageControlI2cLine; 3475 UCHAR ucVoltageControlAddress; 3476 UCHAR ucVoltageControlOffset; 3477 USHORT usGpioPin_AIndex; //GPIO_PAD register index 3478 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff 3479 UCHAR ucReserved; 3480}ATOM_VOLTAGE_CONTROL; 3481 3482// Define ucVoltageControlId 3483#define VOLTAGE_CONTROLLED_BY_HW 0x00 3484#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F 3485#define VOLTAGE_CONTROLLED_BY_GPIO 0x80 3486#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage 3487#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI 3488#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage 3489#define VOLTAGE_CONTROL_ID_DS4402 0x04 3490 3491typedef struct _ATOM_VOLTAGE_OBJECT 3492{ 3493 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 3494 UCHAR ucSize; //Size of Object 3495 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 3496 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID 3497}ATOM_VOLTAGE_OBJECT; 3498 3499typedef struct _ATOM_VOLTAGE_OBJECT_V2 3500{ 3501 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 3502 UCHAR ucSize; //Size of Object 3503 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 3504 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID 3505}ATOM_VOLTAGE_OBJECT_V2; 3506 3507typedef struct _ATOM_VOLTAGE_OBJECT_INFO 3508{ 3509 ATOM_COMMON_TABLE_HEADER sHeader; 3510 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control 3511}ATOM_VOLTAGE_OBJECT_INFO; 3512 3513typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 3514{ 3515 ATOM_COMMON_TABLE_HEADER sHeader; 3516 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control 3517}ATOM_VOLTAGE_OBJECT_INFO_V2; 3518 3519typedef struct _ATOM_LEAKID_VOLTAGE 3520{ 3521 UCHAR ucLeakageId; 3522 UCHAR ucReserved; 3523 USHORT usVoltage; 3524}ATOM_LEAKID_VOLTAGE; 3525 3526typedef struct _ATOM_ASIC_PROFILE_VOLTAGE 3527{ 3528 UCHAR ucProfileId; 3529 UCHAR ucReserved; 3530 USHORT usSize; 3531 USHORT usEfuseSpareStartAddr; 3532 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, 3533 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage 3534}ATOM_ASIC_PROFILE_VOLTAGE; 3535 3536//ucProfileId 3537#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 3538#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 3539#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 3540 3541typedef struct _ATOM_ASIC_PROFILING_INFO 3542{ 3543 ATOM_COMMON_TABLE_HEADER asHeader; 3544 ATOM_ASIC_PROFILE_VOLTAGE asVoltage; 3545}ATOM_ASIC_PROFILING_INFO; 3546 3547typedef struct _ATOM_POWER_SOURCE_OBJECT 3548{ 3549 UCHAR ucPwrSrcId; // Power source 3550 UCHAR ucPwrSensorType; // GPIO, I2C or none 3551 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id 3552 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect 3553 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect 3554 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect 3555 UCHAR ucPwrSensActiveState; // high active or low active 3556 UCHAR ucReserve[3]; // reserve 3557 USHORT usSensPwr; // in unit of watt 3558}ATOM_POWER_SOURCE_OBJECT; 3559 3560typedef struct _ATOM_POWER_SOURCE_INFO 3561{ 3562 ATOM_COMMON_TABLE_HEADER asHeader; 3563 UCHAR asPwrbehave[16]; 3564 ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; 3565}ATOM_POWER_SOURCE_INFO; 3566 3567 3568//Define ucPwrSrcId 3569#define POWERSOURCE_PCIE_ID1 0x00 3570#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 3571#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 3572#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 3573#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 3574 3575//define ucPwrSensorId 3576#define POWER_SENSOR_ALWAYS 0x00 3577#define POWER_SENSOR_GPIO 0x01 3578#define POWER_SENSOR_I2C 0x02 3579 3580typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 3581{ 3582 ATOM_COMMON_TABLE_HEADER sHeader; 3583 ULONG ulBootUpEngineClock; 3584 ULONG ulDentistVCOFreq; 3585 ULONG ulBootUpUMAClock; 3586 ULONG ulReserved1[8]; 3587 ULONG ulBootUpReqDisplayVector; 3588 ULONG ulOtherDisplayMisc; 3589 ULONG ulGPUCapInfo; 3590 ULONG ulReserved2[3]; 3591 ULONG ulSystemConfig; 3592 ULONG ulCPUCapInfo; 3593 USHORT usMaxNBVoltage; 3594 USHORT usMinNBVoltage; 3595 USHORT usBootUpNBVoltage; 3596 USHORT usExtDispConnInfoOffset; 3597 UCHAR ucHtcTmpLmt; 3598 UCHAR ucTjOffset; 3599 UCHAR ucMemoryType; 3600 UCHAR ucUMAChannelNumber; 3601 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; 3602 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; 3603 ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; 3604 ULONG ulReserved3[42]; 3605 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 3606}ATOM_INTEGRATED_SYSTEM_INFO_V6; 3607 3608/********************************************************************************************************************** 3609// ATOM_INTEGRATED_SYSTEM_INFO_V6 Description 3610//ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. 3611//ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 3612//ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 3613//ulReserved1[8] Reserved by now, must be 0x0. 3614//ulBootUpReqDisplayVector VBIOS boot up display IDs 3615// ATOM_DEVICE_CRT1_SUPPORT 0x0001 3616// ATOM_DEVICE_CRT2_SUPPORT 0x0010 3617// ATOM_DEVICE_DFP1_SUPPORT 0x0008 3618// ATOM_DEVICE_DFP6_SUPPORT 0x0040 3619// ATOM_DEVICE_DFP2_SUPPORT 0x0080 3620// ATOM_DEVICE_DFP3_SUPPORT 0x0200 3621// ATOM_DEVICE_DFP4_SUPPORT 0x0400 3622// ATOM_DEVICE_DFP5_SUPPORT 0x0800 3623// ATOM_DEVICE_LCD1_SUPPORT 0x0002 3624//ulOtherDisplayMisc Other display related flags, not defined yet. 3625//ulGPUCapInfo TBD 3626//ulReserved2[3] must be 0x0 for the reserved. 3627//ulSystemConfig TBD 3628//ulCPUCapInfo TBD 3629//usMaxNBVoltage High NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse. 3630//usMinNBVoltage Low NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse. 3631//usBootUpNBVoltage Boot up NB voltage in unit of mv. 3632//ucHtcTmpLmt Bit [22:16] of D24F3x64 Thermal Control (HTC) Register. 3633//ucTjOffset Bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed. 3634//ucMemoryType [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 3635//ucUMAChannelNumber System memory channel numbers. 3636//usExtDispConnectionInfoOffset ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO offset relative to beginning of this table. 3637//ulCSR_M3_ARB_CNTL_DEFAULT[10] Arrays with values for CSR M3 arbiter for default 3638//ulCSR_M3_ARB_CNTL_UVD[10] Arrays with values for CSR M3 arbiter for UVD playback. 3639//ulCSR_M3_ARB_CNTL_FS3D[10] Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 3640**********************************************************************************************************************/ 3641 3642/**************************************************************************/ 3643// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design 3644//Memory SS Info Table 3645//Define Memory Clock SS chip ID 3646#define ICS91719 1 3647#define ICS91720 2 3648 3649//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol 3650typedef struct _ATOM_I2C_DATA_RECORD 3651{ 3652 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" 3653 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually 3654}ATOM_I2C_DATA_RECORD; 3655 3656 3657//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information 3658typedef struct _ATOM_I2C_DEVICE_SETUP_INFO 3659{ 3660 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. 3661 UCHAR ucSSChipID; //SS chip being used 3662 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip 3663 UCHAR ucNumOfI2CDataRecords; //number of data block 3664 ATOM_I2C_DATA_RECORD asI2CData[1]; 3665}ATOM_I2C_DEVICE_SETUP_INFO; 3666 3667//========================================================================================== 3668typedef struct _ATOM_ASIC_MVDD_INFO 3669{ 3670 ATOM_COMMON_TABLE_HEADER sHeader; 3671 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; 3672}ATOM_ASIC_MVDD_INFO; 3673 3674//========================================================================================== 3675#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO 3676 3677//========================================================================================== 3678/**************************************************************************/ 3679 3680typedef struct _ATOM_ASIC_SS_ASSIGNMENT 3681{ 3682 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz 3683 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 3684 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq 3685 UCHAR ucClockIndication; //Indicate which clock source needs SS 3686 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. 3687 UCHAR ucReserved[2]; 3688}ATOM_ASIC_SS_ASSIGNMENT; 3689 3690//Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type. 3691//SS is not required or enabled if a match is not found. 3692#define ASIC_INTERNAL_MEMORY_SS 1 3693#define ASIC_INTERNAL_ENGINE_SS 2 3694#define ASIC_INTERNAL_UVD_SS 3 3695#define ASIC_INTERNAL_SS_ON_TMDS 4 3696#define ASIC_INTERNAL_SS_ON_HDMI 5 3697#define ASIC_INTERNAL_SS_ON_LVDS 6 3698#define ASIC_INTERNAL_SS_ON_DP 7 3699#define ASIC_INTERNAL_SS_ON_DCPLL 8 3700 3701typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 3702{ 3703 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 3704 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 3705 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 3706 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 3707 UCHAR ucClockIndication; //Indicate which clock source needs SS 3708 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 3709 UCHAR ucReserved[2]; 3710}ATOM_ASIC_SS_ASSIGNMENT_V2; 3711 3712//ucSpreadSpectrumMode 3713//#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 3714//#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 3715//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 3716//#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 3717//#define ATOM_INTERNAL_SS_MASK 0x00000000 3718//#define ATOM_EXTERNAL_SS_MASK 0x00000002 3719 3720typedef struct _ATOM_ASIC_INTERNAL_SS_INFO 3721{ 3722 ATOM_COMMON_TABLE_HEADER sHeader; 3723 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; 3724}ATOM_ASIC_INTERNAL_SS_INFO; 3725 3726typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 3727{ 3728 ATOM_COMMON_TABLE_HEADER sHeader; 3729 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. 3730}ATOM_ASIC_INTERNAL_SS_INFO_V2; 3731 3732typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 3733{ 3734 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 3735 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 3736 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 3737 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 3738 UCHAR ucClockIndication; //Indicate which clock source needs SS 3739 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 3740 UCHAR ucReserved[2]; 3741}ATOM_ASIC_SS_ASSIGNMENT_V3; 3742 3743typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 3744{ 3745 ATOM_COMMON_TABLE_HEADER sHeader; 3746 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. 3747}ATOM_ASIC_INTERNAL_SS_INFO_V3; 3748 3749 3750//==============================Scratch Pad Definition Portion=============================== 3751#define ATOM_DEVICE_CONNECT_INFO_DEF 0 3752#define ATOM_ROM_LOCATION_DEF 1 3753#define ATOM_TV_STANDARD_DEF 2 3754#define ATOM_ACTIVE_INFO_DEF 3 3755#define ATOM_LCD_INFO_DEF 4 3756#define ATOM_DOS_REQ_INFO_DEF 5 3757#define ATOM_ACC_CHANGE_INFO_DEF 6 3758#define ATOM_DOS_MODE_INFO_DEF 7 3759#define ATOM_I2C_CHANNEL_STATUS_DEF 8 3760#define ATOM_I2C_CHANNEL_STATUS1_DEF 9 3761 3762 3763// BIOS_0_SCRATCH Definition 3764#define ATOM_S0_CRT1_MONO 0x00000001L 3765#define ATOM_S0_CRT1_COLOR 0x00000002L 3766#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) 3767 3768#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L 3769#define ATOM_S0_TV1_SVIDEO_A 0x00000008L 3770#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) 3771 3772#define ATOM_S0_CV_A 0x00000010L 3773#define ATOM_S0_CV_DIN_A 0x00000020L 3774#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) 3775 3776 3777#define ATOM_S0_CRT2_MONO 0x00000100L 3778#define ATOM_S0_CRT2_COLOR 0x00000200L 3779#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) 3780 3781#define ATOM_S0_TV1_COMPOSITE 0x00000400L 3782#define ATOM_S0_TV1_SVIDEO 0x00000800L 3783#define ATOM_S0_TV1_SCART 0x00004000L 3784#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) 3785 3786#define ATOM_S0_CV 0x00001000L 3787#define ATOM_S0_CV_DIN 0x00002000L 3788#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) 3789 3790#define ATOM_S0_DFP1 0x00010000L 3791#define ATOM_S0_DFP2 0x00020000L 3792#define ATOM_S0_LCD1 0x00040000L 3793#define ATOM_S0_LCD2 0x00080000L 3794#define ATOM_S0_DFP6 0x00100000L 3795#define ATOM_S0_DFP3 0x00200000L 3796#define ATOM_S0_DFP4 0x00400000L 3797#define ATOM_S0_DFP5 0x00800000L 3798 3799#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 3800 3801#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with 3802 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx 3803 3804#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L 3805#define ATOM_S0_THERMAL_STATE_SHIFT 26 3806 3807#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L 3808#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 3809 3810#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 3811#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 3812#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 3813 3814//Byte aligned defintion for BIOS usage 3815#define ATOM_S0_CRT1_MONOb0 0x01 3816#define ATOM_S0_CRT1_COLORb0 0x02 3817#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 3818 3819#define ATOM_S0_TV1_COMPOSITEb0 0x04 3820#define ATOM_S0_TV1_SVIDEOb0 0x08 3821#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) 3822 3823#define ATOM_S0_CVb0 0x10 3824#define ATOM_S0_CV_DINb0 0x20 3825#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) 3826 3827#define ATOM_S0_CRT2_MONOb1 0x01 3828#define ATOM_S0_CRT2_COLORb1 0x02 3829#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) 3830 3831#define ATOM_S0_TV1_COMPOSITEb1 0x04 3832#define ATOM_S0_TV1_SVIDEOb1 0x08 3833#define ATOM_S0_TV1_SCARTb1 0x40 3834#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) 3835 3836#define ATOM_S0_CVb1 0x10 3837#define ATOM_S0_CV_DINb1 0x20 3838#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) 3839 3840#define ATOM_S0_DFP1b2 0x01 3841#define ATOM_S0_DFP2b2 0x02 3842#define ATOM_S0_LCD1b2 0x04 3843#define ATOM_S0_LCD2b2 0x08 3844#define ATOM_S0_DFP6b2 0x10 3845#define ATOM_S0_DFP3b2 0x20 3846#define ATOM_S0_DFP4b2 0x40 3847#define ATOM_S0_DFP5b2 0x80 3848 3849 3850#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C 3851#define ATOM_S0_THERMAL_STATE_SHIFTb3 2 3852 3853#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 3854#define ATOM_S0_LCD1_SHIFT 18 3855 3856// BIOS_1_SCRATCH Definition 3857#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL 3858#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L 3859 3860// BIOS_2_SCRATCH Definition 3861#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL 3862#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L 3863#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 3864 3865#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L 3866#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 3867#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L 3868 3869#define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L 3870#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L 3871 3872#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 3873#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 3874#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 3875#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 3876#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 3877#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 3878 3879 3880//Byte aligned defintion for BIOS usage 3881#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 3882#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 3883#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 3884 3885#define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF 3886#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C 3887#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10 3888#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 3889#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 3890 3891 3892// BIOS_3_SCRATCH Definition 3893#define ATOM_S3_CRT1_ACTIVE 0x00000001L 3894#define ATOM_S3_LCD1_ACTIVE 0x00000002L 3895#define ATOM_S3_TV1_ACTIVE 0x00000004L 3896#define ATOM_S3_DFP1_ACTIVE 0x00000008L 3897#define ATOM_S3_CRT2_ACTIVE 0x00000010L 3898#define ATOM_S3_LCD2_ACTIVE 0x00000020L 3899#define ATOM_S3_DFP6_ACTIVE 0x00000040L 3900#define ATOM_S3_DFP2_ACTIVE 0x00000080L 3901#define ATOM_S3_CV_ACTIVE 0x00000100L 3902#define ATOM_S3_DFP3_ACTIVE 0x00000200L 3903#define ATOM_S3_DFP4_ACTIVE 0x00000400L 3904#define ATOM_S3_DFP5_ACTIVE 0x00000800L 3905 3906#define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL 3907 3908#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L 3909#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L 3910 3911#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L 3912#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L 3913#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L 3914#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L 3915#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L 3916#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L 3917#define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L 3918#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L 3919#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L 3920#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L 3921#define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L 3922#define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L 3923 3924#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L 3925#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L 3926//Below two definitions are not supported in pplib, but in the old powerplay in DAL 3927#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 3928#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 3929 3930//Byte aligned defintion for BIOS usage 3931#define ATOM_S3_CRT1_ACTIVEb0 0x01 3932#define ATOM_S3_LCD1_ACTIVEb0 0x02 3933#define ATOM_S3_TV1_ACTIVEb0 0x04 3934#define ATOM_S3_DFP1_ACTIVEb0 0x08 3935#define ATOM_S3_CRT2_ACTIVEb0 0x10 3936#define ATOM_S3_LCD2_ACTIVEb0 0x20 3937#define ATOM_S3_DFP6_ACTIVEb0 0x40 3938#define ATOM_S3_DFP2_ACTIVEb0 0x80 3939#define ATOM_S3_CV_ACTIVEb1 0x01 3940#define ATOM_S3_DFP3_ACTIVEb1 0x02 3941#define ATOM_S3_DFP4_ACTIVEb1 0x04 3942#define ATOM_S3_DFP5_ACTIVEb1 0x08 3943 3944#define ATOM_S3_ACTIVE_CRTC1w0 0xFFF 3945 3946#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 3947#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 3948#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 3949#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 3950#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 3951#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 3952#define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 3953#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 3954#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 3955#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 3956#define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 3957#define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 3958 3959#define ATOM_S3_ACTIVE_CRTC2w1 0xFFF 3960 3961// BIOS_4_SCRATCH Definition 3962#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL 3963#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 3964#define ATOM_S4_LCD1_REFRESH_SHIFT 8 3965 3966//Byte aligned defintion for BIOS usage 3967#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 3968#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 3969#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 3970 3971// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! 3972#define ATOM_S5_DOS_REQ_CRT1b0 0x01 3973#define ATOM_S5_DOS_REQ_LCD1b0 0x02 3974#define ATOM_S5_DOS_REQ_TV1b0 0x04 3975#define ATOM_S5_DOS_REQ_DFP1b0 0x08 3976#define ATOM_S5_DOS_REQ_CRT2b0 0x10 3977#define ATOM_S5_DOS_REQ_LCD2b0 0x20 3978#define ATOM_S5_DOS_REQ_DFP6b0 0x40 3979#define ATOM_S5_DOS_REQ_DFP2b0 0x80 3980#define ATOM_S5_DOS_REQ_CVb1 0x01 3981#define ATOM_S5_DOS_REQ_DFP3b1 0x02 3982#define ATOM_S5_DOS_REQ_DFP4b1 0x04 3983#define ATOM_S5_DOS_REQ_DFP5b1 0x08 3984 3985#define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF 3986 3987#define ATOM_S5_DOS_REQ_CRT1 0x0001 3988#define ATOM_S5_DOS_REQ_LCD1 0x0002 3989#define ATOM_S5_DOS_REQ_TV1 0x0004 3990#define ATOM_S5_DOS_REQ_DFP1 0x0008 3991#define ATOM_S5_DOS_REQ_CRT2 0x0010 3992#define ATOM_S5_DOS_REQ_LCD2 0x0020 3993#define ATOM_S5_DOS_REQ_DFP6 0x0040 3994#define ATOM_S5_DOS_REQ_DFP2 0x0080 3995#define ATOM_S5_DOS_REQ_CV 0x0100 3996#define ATOM_S5_DOS_REQ_DFP3 0x0200 3997#define ATOM_S5_DOS_REQ_DFP4 0x0400 3998#define ATOM_S5_DOS_REQ_DFP5 0x0800 3999 4000#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 4001#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 4002#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 4003#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 4004#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ 4005 (ATOM_S5_DOS_FORCE_CVb3<<8)) 4006 4007// BIOS_6_SCRATCH Definition 4008#define ATOM_S6_DEVICE_CHANGE 0x00000001L 4009#define ATOM_S6_SCALER_CHANGE 0x00000002L 4010#define ATOM_S6_LID_CHANGE 0x00000004L 4011#define ATOM_S6_DOCKING_CHANGE 0x00000008L 4012#define ATOM_S6_ACC_MODE 0x00000010L 4013#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L 4014#define ATOM_S6_LID_STATE 0x00000040L 4015#define ATOM_S6_DOCK_STATE 0x00000080L 4016#define ATOM_S6_CRITICAL_STATE 0x00000100L 4017#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L 4018#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L 4019#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L 4020#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD 4021#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD 4022 4023#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion 4024#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion 4025 4026#define ATOM_S6_ACC_REQ_CRT1 0x00010000L 4027#define ATOM_S6_ACC_REQ_LCD1 0x00020000L 4028#define ATOM_S6_ACC_REQ_TV1 0x00040000L 4029#define ATOM_S6_ACC_REQ_DFP1 0x00080000L 4030#define ATOM_S6_ACC_REQ_CRT2 0x00100000L 4031#define ATOM_S6_ACC_REQ_LCD2 0x00200000L 4032#define ATOM_S6_ACC_REQ_DFP6 0x00400000L 4033#define ATOM_S6_ACC_REQ_DFP2 0x00800000L 4034#define ATOM_S6_ACC_REQ_CV 0x01000000L 4035#define ATOM_S6_ACC_REQ_DFP3 0x02000000L 4036#define ATOM_S6_ACC_REQ_DFP4 0x04000000L 4037#define ATOM_S6_ACC_REQ_DFP5 0x08000000L 4038 4039#define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L 4040#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L 4041#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L 4042#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 4043#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 4044 4045//Byte aligned defintion for BIOS usage 4046#define ATOM_S6_DEVICE_CHANGEb0 0x01 4047#define ATOM_S6_SCALER_CHANGEb0 0x02 4048#define ATOM_S6_LID_CHANGEb0 0x04 4049#define ATOM_S6_DOCKING_CHANGEb0 0x08 4050#define ATOM_S6_ACC_MODEb0 0x10 4051#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 4052#define ATOM_S6_LID_STATEb0 0x40 4053#define ATOM_S6_DOCK_STATEb0 0x80 4054#define ATOM_S6_CRITICAL_STATEb1 0x01 4055#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 4056#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 4057#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 4058#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 4059#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 4060 4061#define ATOM_S6_ACC_REQ_CRT1b2 0x01 4062#define ATOM_S6_ACC_REQ_LCD1b2 0x02 4063#define ATOM_S6_ACC_REQ_TV1b2 0x04 4064#define ATOM_S6_ACC_REQ_DFP1b2 0x08 4065#define ATOM_S6_ACC_REQ_CRT2b2 0x10 4066#define ATOM_S6_ACC_REQ_LCD2b2 0x20 4067#define ATOM_S6_ACC_REQ_DFP6b2 0x40 4068#define ATOM_S6_ACC_REQ_DFP2b2 0x80 4069#define ATOM_S6_ACC_REQ_CVb3 0x01 4070#define ATOM_S6_ACC_REQ_DFP3b3 0x02 4071#define ATOM_S6_ACC_REQ_DFP4b3 0x04 4072#define ATOM_S6_ACC_REQ_DFP5b3 0x08 4073 4074#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 4075#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 4076#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 4077#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 4078#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 4079 4080#define ATOM_S6_DEVICE_CHANGE_SHIFT 0 4081#define ATOM_S6_SCALER_CHANGE_SHIFT 1 4082#define ATOM_S6_LID_CHANGE_SHIFT 2 4083#define ATOM_S6_DOCKING_CHANGE_SHIFT 3 4084#define ATOM_S6_ACC_MODE_SHIFT 4 4085#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 4086#define ATOM_S6_LID_STATE_SHIFT 6 4087#define ATOM_S6_DOCK_STATE_SHIFT 7 4088#define ATOM_S6_CRITICAL_STATE_SHIFT 8 4089#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 4090#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 4091#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 4092#define ATOM_S6_REQ_SCALER_SHIFT 12 4093#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 4094#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 4095#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 4096#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 4097#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 4098#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 4099#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 4100 4101// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! 4102#define ATOM_S7_DOS_MODE_TYPEb0 0x03 4103#define ATOM_S7_DOS_MODE_VGAb0 0x00 4104#define ATOM_S7_DOS_MODE_VESAb0 0x01 4105#define ATOM_S7_DOS_MODE_EXTb0 0x02 4106#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 4107#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 4108#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 4109#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 4110 4111#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 4112 4113// BIOS_8_SCRATCH Definition 4114#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF 4115#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 4116 4117#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 4118#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 4119 4120// BIOS_9_SCRATCH Definition 4121#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 4122#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF 4123#endif 4124#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK 4125#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 4126#endif 4127#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 4128#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 4129#endif 4130#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 4131#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 4132#endif 4133 4134 4135#define ATOM_FLAG_SET 0x20 4136#define ATOM_FLAG_CLEAR 0 4137#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) 4138#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) 4139#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) 4140#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) 4141#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) 4142 4143#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) 4144#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) 4145 4146#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) 4147#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) 4148#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) 4149 4150#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) 4151#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) 4152#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) 4153 4154#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) 4155#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) 4156 4157#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) 4158#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) 4159 4160#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) 4161#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) 4162 4163#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 4164 4165#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 4166 4167#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) 4168#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) 4169#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) 4170#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) 4171 4172/****************************************************************************/ 4173//Portion II: Definitinos only used in Driver 4174/****************************************************************************/ 4175 4176// Macros used by driver 4177#ifdef __cplusplus 4178#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT)) 4179 4180#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) 4181#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) 4182#else // not __cplusplus 4183#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) 4184 4185#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) 4186#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) 4187#endif // __cplusplus 4188 4189#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION 4190#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION 4191 4192/****************************************************************************/ 4193//Portion III: Definitinos only used in VBIOS 4194/****************************************************************************/ 4195#define ATOM_DAC_SRC 0x80 4196#define ATOM_SRC_DAC1 0 4197#define ATOM_SRC_DAC2 0x80 4198 4199typedef struct _MEMORY_PLLINIT_PARAMETERS 4200{ 4201 ULONG ulTargetMemoryClock; //In 10Khz unit 4202 UCHAR ucAction; //not define yet 4203 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte 4204 UCHAR ucFbDiv; //FB value 4205 UCHAR ucPostDiv; //Post div 4206}MEMORY_PLLINIT_PARAMETERS; 4207 4208#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS 4209 4210 4211#define GPIO_PIN_WRITE 0x01 4212#define GPIO_PIN_READ 0x00 4213 4214typedef struct _GPIO_PIN_CONTROL_PARAMETERS 4215{ 4216 UCHAR ucGPIO_ID; //return value, read from GPIO pins 4217 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update 4218 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask 4219 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write 4220}GPIO_PIN_CONTROL_PARAMETERS; 4221 4222typedef struct _ENABLE_SCALER_PARAMETERS 4223{ 4224 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 4225 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION 4226 UCHAR ucTVStandard; // 4227 UCHAR ucPadding[1]; 4228}ENABLE_SCALER_PARAMETERS; 4229#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS 4230 4231//ucEnable: 4232#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 4233#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 4234#define SCALER_ENABLE_2TAP_ALPHA_MODE 2 4235#define SCALER_ENABLE_MULTITAP_MODE 3 4236 4237typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS 4238{ 4239 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position 4240 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset 4241 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset 4242 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 4243 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 4244}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; 4245 4246typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION 4247{ 4248 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; 4249 ENABLE_CRTC_PARAMETERS sReserved; 4250}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; 4251 4252typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS 4253{ 4254 USHORT usHight; // Image Hight 4255 USHORT usWidth; // Image Width 4256 UCHAR ucSurface; // Surface 1 or 2 4257 UCHAR ucPadding[3]; 4258}ENABLE_GRAPH_SURFACE_PARAMETERS; 4259 4260typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 4261{ 4262 USHORT usHight; // Image Hight 4263 USHORT usWidth; // Image Width 4264 UCHAR ucSurface; // Surface 1 or 2 4265 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 4266 UCHAR ucPadding[2]; 4267}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; 4268 4269typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 4270{ 4271 USHORT usHight; // Image Hight 4272 USHORT usWidth; // Image Width 4273 UCHAR ucSurface; // Surface 1 or 2 4274 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 4275 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. 4276}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; 4277 4278typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION 4279{ 4280 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; 4281 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one 4282}ENABLE_GRAPH_SURFACE_PS_ALLOCATION; 4283 4284typedef struct _MEMORY_CLEAN_UP_PARAMETERS 4285{ 4286 USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address 4287 USHORT usMemorySize; //8Kb blocks aligned 4288}MEMORY_CLEAN_UP_PARAMETERS; 4289#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS 4290 4291typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS 4292{ 4293 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 4294 USHORT usY_Size; 4295}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; 4296 4297typedef struct _INDIRECT_IO_ACCESS 4298{ 4299 ATOM_COMMON_TABLE_HEADER sHeader; 4300 UCHAR IOAccessSequence[256]; 4301} INDIRECT_IO_ACCESS; 4302 4303#define INDIRECT_READ 0x00 4304#define INDIRECT_WRITE 0x80 4305 4306#define INDIRECT_IO_MM 0 4307#define INDIRECT_IO_PLL 1 4308#define INDIRECT_IO_MC 2 4309#define INDIRECT_IO_PCIE 3 4310#define INDIRECT_IO_PCIEP 4 4311#define INDIRECT_IO_NBMISC 5 4312 4313#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ 4314#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE 4315#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ 4316#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE 4317#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ 4318#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE 4319#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ 4320#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE 4321#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ 4322#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE 4323 4324typedef struct _ATOM_OEM_INFO 4325{ 4326 ATOM_COMMON_TABLE_HEADER sHeader; 4327 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 4328}ATOM_OEM_INFO; 4329 4330typedef struct _ATOM_TV_MODE 4331{ 4332 UCHAR ucVMode_Num; //Video mode number 4333 UCHAR ucTV_Mode_Num; //Internal TV mode number 4334}ATOM_TV_MODE; 4335 4336typedef struct _ATOM_BIOS_INT_TVSTD_MODE 4337{ 4338 ATOM_COMMON_TABLE_HEADER sHeader; 4339 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table 4340 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table 4341 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table 4342 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 4343 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 4344}ATOM_BIOS_INT_TVSTD_MODE; 4345 4346 4347typedef struct _ATOM_TV_MODE_SCALER_PTR 4348{ 4349 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients 4350 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients 4351 UCHAR ucTV_Mode_Num; 4352}ATOM_TV_MODE_SCALER_PTR; 4353 4354typedef struct _ATOM_STANDARD_VESA_TIMING 4355{ 4356 ATOM_COMMON_TABLE_HEADER sHeader; 4357 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation 4358}ATOM_STANDARD_VESA_TIMING; 4359 4360 4361typedef struct _ATOM_STD_FORMAT 4362{ 4363 USHORT usSTD_HDisp; 4364 USHORT usSTD_VDisp; 4365 USHORT usSTD_RefreshRate; 4366 USHORT usReserved; 4367}ATOM_STD_FORMAT; 4368 4369typedef struct _ATOM_VESA_TO_EXTENDED_MODE 4370{ 4371 USHORT usVESA_ModeNumber; 4372 USHORT usExtendedModeNumber; 4373}ATOM_VESA_TO_EXTENDED_MODE; 4374 4375typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT 4376{ 4377 ATOM_COMMON_TABLE_HEADER sHeader; 4378 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; 4379}ATOM_VESA_TO_INTENAL_MODE_LUT; 4380 4381/*************** ATOM Memory Related Data Structure ***********************/ 4382typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ 4383 UCHAR ucMemoryType; 4384 UCHAR ucMemoryVendor; 4385 UCHAR ucAdjMCId; 4386 UCHAR ucDynClkId; 4387 ULONG ulDllResetClkRange; 4388}ATOM_MEMORY_VENDOR_BLOCK; 4389 4390 4391typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ 4392#if ATOM_BIG_ENDIAN 4393 ULONG ucMemBlkId:8; 4394 ULONG ulMemClockRange:24; 4395#else 4396 ULONG ulMemClockRange:24; 4397 ULONG ucMemBlkId:8; 4398#endif 4399}ATOM_MEMORY_SETTING_ID_CONFIG; 4400 4401typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS 4402{ 4403 ATOM_MEMORY_SETTING_ID_CONFIG slAccess; 4404 ULONG ulAccess; 4405}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; 4406 4407 4408typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ 4409 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; 4410 ULONG aulMemData[1]; 4411}ATOM_MEMORY_SETTING_DATA_BLOCK; 4412 4413 4414typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ 4415 USHORT usRegIndex; // MC register index 4416 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf 4417}ATOM_INIT_REG_INDEX_FORMAT; 4418 4419 4420typedef struct _ATOM_INIT_REG_BLOCK{ 4421 USHORT usRegIndexTblSize; //size of asRegIndexBuf 4422 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK 4423 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; 4424 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; 4425}ATOM_INIT_REG_BLOCK; 4426 4427#define END_OF_REG_INDEX_BLOCK 0x0ffff 4428#define END_OF_REG_DATA_BLOCK 0x00000000 4429#define ATOM_INIT_REG_MASK_FLAG 0x80 4430#define CLOCK_RANGE_HIGHEST 0x00ffffff 4431 4432#define VALUE_DWORD SIZEOF ULONG 4433#define VALUE_SAME_AS_ABOVE 0 4434#define VALUE_MASK_DWORD 0x84 4435 4436#define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) 4437#define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) 4438#define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) 4439 4440 4441typedef struct _ATOM_MC_INIT_PARAM_TABLE 4442{ 4443 ATOM_COMMON_TABLE_HEADER sHeader; 4444 USHORT usAdjustARB_SEQDataOffset; 4445 USHORT usMCInitMemTypeTblOffset; 4446 USHORT usMCInitCommonTblOffset; 4447 USHORT usMCInitPowerDownTblOffset; 4448 ULONG ulARB_SEQDataBuf[32]; 4449 ATOM_INIT_REG_BLOCK asMCInitMemType; 4450 ATOM_INIT_REG_BLOCK asMCInitCommon; 4451}ATOM_MC_INIT_PARAM_TABLE; 4452 4453 4454#define _4Mx16 0x2 4455#define _4Mx32 0x3 4456#define _8Mx16 0x12 4457#define _8Mx32 0x13 4458#define _16Mx16 0x22 4459#define _16Mx32 0x23 4460#define _32Mx16 0x32 4461#define _32Mx32 0x33 4462#define _64Mx8 0x41 4463#define _64Mx16 0x42 4464 4465#define SAMSUNG 0x1 4466#define INFINEON 0x2 4467#define ELPIDA 0x3 4468#define ETRON 0x4 4469#define NANYA 0x5 4470#define HYNIX 0x6 4471#define MOSEL 0x7 4472#define WINBOND 0x8 4473#define ESMT 0x9 4474#define MICRON 0xF 4475 4476#define QIMONDA INFINEON 4477#define PROMOS MOSEL 4478#define KRETON INFINEON 4479 4480/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// 4481 4482#define UCODE_ROM_START_ADDRESS 0x1c000 4483#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode 4484 4485//uCode block header for reference 4486 4487typedef struct _MCuCodeHeader 4488{ 4489 ULONG ulSignature; 4490 UCHAR ucRevision; 4491 UCHAR ucChecksum; 4492 UCHAR ucReserved1; 4493 UCHAR ucReserved2; 4494 USHORT usParametersLength; 4495 USHORT usUCodeLength; 4496 USHORT usReserved1; 4497 USHORT usReserved2; 4498} MCuCodeHeader; 4499 4500////////////////////////////////////////////////////////////////////////////////// 4501 4502#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 4503 4504#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF 4505typedef struct _ATOM_VRAM_MODULE_V1 4506{ 4507 ULONG ulReserved; 4508 USHORT usEMRSValue; 4509 USHORT usMRSValue; 4510 USHORT usReserved; 4511 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 4512 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; 4513 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender 4514 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 4515 UCHAR ucRow; // Number of Row,in power of 2; 4516 UCHAR ucColumn; // Number of Column,in power of 2; 4517 UCHAR ucBank; // Nunber of Bank; 4518 UCHAR ucRank; // Number of Rank, in power of 2 4519 UCHAR ucChannelNum; // Number of channel; 4520 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 4521 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 4522 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 4523 UCHAR ucReserved[2]; 4524}ATOM_VRAM_MODULE_V1; 4525 4526 4527typedef struct _ATOM_VRAM_MODULE_V2 4528{ 4529 ULONG ulReserved; 4530 ULONG ulFlags; // To enable/disable functionalities based on memory type 4531 ULONG ulEngineClock; // Override of default engine clock for particular memory type 4532 ULONG ulMemoryClock; // Override of default memory clock for particular memory type 4533 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 4534 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 4535 USHORT usEMRSValue; 4536 USHORT usMRSValue; 4537 USHORT usReserved; 4538 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 4539 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 4540 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 4541 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 4542 UCHAR ucRow; // Number of Row,in power of 2; 4543 UCHAR ucColumn; // Number of Column,in power of 2; 4544 UCHAR ucBank; // Nunber of Bank; 4545 UCHAR ucRank; // Number of Rank, in power of 2 4546 UCHAR ucChannelNum; // Number of channel; 4547 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 4548 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 4549 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 4550 UCHAR ucRefreshRateFactor; 4551 UCHAR ucReserved[3]; 4552}ATOM_VRAM_MODULE_V2; 4553 4554 4555typedef struct _ATOM_MEMORY_TIMING_FORMAT 4556{ 4557 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 4558 union{ 4559 USHORT usMRS; // mode register 4560 USHORT usDDR3_MR0; 4561 }; 4562 union{ 4563 USHORT usEMRS; // extended mode register 4564 USHORT usDDR3_MR1; 4565 }; 4566 UCHAR ucCL; // CAS latency 4567 UCHAR ucWL; // WRITE Latency 4568 UCHAR uctRAS; // tRAS 4569 UCHAR uctRC; // tRC 4570 UCHAR uctRFC; // tRFC 4571 UCHAR uctRCDR; // tRCDR 4572 UCHAR uctRCDW; // tRCDW 4573 UCHAR uctRP; // tRP 4574 UCHAR uctRRD; // tRRD 4575 UCHAR uctWR; // tWR 4576 UCHAR uctWTR; // tWTR 4577 UCHAR uctPDIX; // tPDIX 4578 UCHAR uctFAW; // tFAW 4579 UCHAR uctAOND; // tAOND 4580 union 4581 { 4582 struct { 4583 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 4584 UCHAR ucReserved; 4585 }; 4586 USHORT usDDR3_MR2; 4587 }; 4588}ATOM_MEMORY_TIMING_FORMAT; 4589 4590 4591typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 4592{ 4593 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 4594 USHORT usMRS; // mode register 4595 USHORT usEMRS; // extended mode register 4596 UCHAR ucCL; // CAS latency 4597 UCHAR ucWL; // WRITE Latency 4598 UCHAR uctRAS; // tRAS 4599 UCHAR uctRC; // tRC 4600 UCHAR uctRFC; // tRFC 4601 UCHAR uctRCDR; // tRCDR 4602 UCHAR uctRCDW; // tRCDW 4603 UCHAR uctRP; // tRP 4604 UCHAR uctRRD; // tRRD 4605 UCHAR uctWR; // tWR 4606 UCHAR uctWTR; // tWTR 4607 UCHAR uctPDIX; // tPDIX 4608 UCHAR uctFAW; // tFAW 4609 UCHAR uctAOND; // tAOND 4610 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 4611////////////////////////////////////GDDR parameters/////////////////////////////////// 4612 UCHAR uctCCDL; // 4613 UCHAR uctCRCRL; // 4614 UCHAR uctCRCWL; // 4615 UCHAR uctCKE; // 4616 UCHAR uctCKRSE; // 4617 UCHAR uctCKRSX; // 4618 UCHAR uctFAW32; // 4619 UCHAR ucMR5lo; // 4620 UCHAR ucMR5hi; // 4621 UCHAR ucTerminator; 4622}ATOM_MEMORY_TIMING_FORMAT_V1; 4623 4624typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 4625{ 4626 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 4627 USHORT usMRS; // mode register 4628 USHORT usEMRS; // extended mode register 4629 UCHAR ucCL; // CAS latency 4630 UCHAR ucWL; // WRITE Latency 4631 UCHAR uctRAS; // tRAS 4632 UCHAR uctRC; // tRC 4633 UCHAR uctRFC; // tRFC 4634 UCHAR uctRCDR; // tRCDR 4635 UCHAR uctRCDW; // tRCDW 4636 UCHAR uctRP; // tRP 4637 UCHAR uctRRD; // tRRD 4638 UCHAR uctWR; // tWR 4639 UCHAR uctWTR; // tWTR 4640 UCHAR uctPDIX; // tPDIX 4641 UCHAR uctFAW; // tFAW 4642 UCHAR uctAOND; // tAOND 4643 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 4644////////////////////////////////////GDDR parameters/////////////////////////////////// 4645 UCHAR uctCCDL; // 4646 UCHAR uctCRCRL; // 4647 UCHAR uctCRCWL; // 4648 UCHAR uctCKE; // 4649 UCHAR uctCKRSE; // 4650 UCHAR uctCKRSX; // 4651 UCHAR uctFAW32; // 4652 UCHAR ucMR4lo; // 4653 UCHAR ucMR4hi; // 4654 UCHAR ucMR5lo; // 4655 UCHAR ucMR5hi; // 4656 UCHAR ucTerminator; 4657 UCHAR ucReserved; 4658}ATOM_MEMORY_TIMING_FORMAT_V2; 4659 4660typedef struct _ATOM_MEMORY_FORMAT 4661{ 4662 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock 4663 union{ 4664 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 4665 USHORT usDDR3_Reserved; // Not used for DDR3 memory 4666 }; 4667 union{ 4668 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 4669 USHORT usDDR3_MR3; // Used for DDR3 memory 4670 }; 4671 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 4672 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 4673 UCHAR ucRow; // Number of Row,in power of 2; 4674 UCHAR ucColumn; // Number of Column,in power of 2; 4675 UCHAR ucBank; // Nunber of Bank; 4676 UCHAR ucRank; // Number of Rank, in power of 2 4677 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 4678 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) 4679 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms 4680 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 4681 UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble 4682 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc 4683 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock 4684}ATOM_MEMORY_FORMAT; 4685 4686 4687typedef struct _ATOM_VRAM_MODULE_V3 4688{ 4689 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination 4690 USHORT usSize; // size of ATOM_VRAM_MODULE_V3 4691 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage 4692 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage 4693 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 4694 UCHAR ucChannelNum; // board dependent parameter:Number of channel; 4695 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit 4696 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv 4697 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 4698 UCHAR ucFlag; // To enable/disable functionalities based on memory type 4699 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec 4700}ATOM_VRAM_MODULE_V3; 4701 4702 4703//ATOM_VRAM_MODULE_V3.ucNPL_RT 4704#define NPL_RT_MASK 0x0f 4705#define BATTERY_ODT_MASK 0xc0 4706 4707#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 4708 4709typedef struct _ATOM_VRAM_MODULE_V4 4710{ 4711 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 4712 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 4713 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 4714 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 4715 USHORT usReserved; 4716 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 4717 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 4718 UCHAR ucChannelNum; // Number of channels present in this module config 4719 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 4720 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 4721 UCHAR ucFlag; // To enable/disable functionalities based on memory type 4722 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 4723 UCHAR ucVREFI; // board dependent parameter 4724 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 4725 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 4726 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 4727 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 4728 UCHAR ucReserved[3]; 4729 4730//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 4731 union{ 4732 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 4733 USHORT usDDR3_Reserved; 4734 }; 4735 union{ 4736 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 4737 USHORT usDDR3_MR3; // Used for DDR3 memory 4738 }; 4739 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 4740 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 4741 UCHAR ucReserved2[2]; 4742 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 4743}ATOM_VRAM_MODULE_V4; 4744 4745#define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 4746#define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 4747#define VRAM_MODULE_V4_MISC_BL_MASK 0x4 4748#define VRAM_MODULE_V4_MISC_BL8 0x4 4749#define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 4750 4751typedef struct _ATOM_VRAM_MODULE_V5 4752{ 4753 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 4754 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 4755 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 4756 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 4757 USHORT usReserved; 4758 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 4759 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 4760 UCHAR ucChannelNum; // Number of channels present in this module config 4761 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 4762 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 4763 UCHAR ucFlag; // To enable/disable functionalities based on memory type 4764 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 4765 UCHAR ucVREFI; // board dependent parameter 4766 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 4767 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 4768 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 4769 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 4770 UCHAR ucReserved[3]; 4771 4772//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 4773 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 4774 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 4775 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 4776 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 4777 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 4778 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 4779 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 4780}ATOM_VRAM_MODULE_V5; 4781 4782typedef struct _ATOM_VRAM_MODULE_V6 4783{ 4784 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 4785 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 4786 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 4787 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 4788 USHORT usReserved; 4789 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 4790 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 4791 UCHAR ucChannelNum; // Number of channels present in this module config 4792 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 4793 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 4794 UCHAR ucFlag; // To enable/disable functionalities based on memory type 4795 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 4796 UCHAR ucVREFI; // board dependent parameter 4797 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 4798 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 4799 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 4800 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 4801 UCHAR ucReserved[3]; 4802 4803//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 4804 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 4805 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 4806 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 4807 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 4808 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 4809 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 4810 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 4811}ATOM_VRAM_MODULE_V6; 4812 4813 4814 4815typedef struct _ATOM_VRAM_INFO_V2 4816{ 4817 ATOM_COMMON_TABLE_HEADER sHeader; 4818 UCHAR ucNumOfVRAMModule; 4819 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 4820}ATOM_VRAM_INFO_V2; 4821 4822typedef struct _ATOM_VRAM_INFO_V3 4823{ 4824 ATOM_COMMON_TABLE_HEADER sHeader; 4825 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 4826 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 4827 USHORT usRerseved; 4828 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 4829 UCHAR ucNumOfVRAMModule; 4830 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 4831 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 4832 // ATOM_INIT_REG_BLOCK aMemAdjust; 4833}ATOM_VRAM_INFO_V3; 4834 4835#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 4836 4837typedef struct _ATOM_VRAM_INFO_V4 4838{ 4839 ATOM_COMMON_TABLE_HEADER sHeader; 4840 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 4841 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 4842 USHORT usRerseved; 4843 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 4844 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] 4845 UCHAR ucReservde[4]; 4846 UCHAR ucNumOfVRAMModule; 4847 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 4848 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 4849 // ATOM_INIT_REG_BLOCK aMemAdjust; 4850}ATOM_VRAM_INFO_V4; 4851 4852typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO 4853{ 4854 ATOM_COMMON_TABLE_HEADER sHeader; 4855 UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator 4856}ATOM_VRAM_GPIO_DETECTION_INFO; 4857 4858 4859typedef struct _ATOM_MEMORY_TRAINING_INFO 4860{ 4861 ATOM_COMMON_TABLE_HEADER sHeader; 4862 UCHAR ucTrainingLoop; 4863 UCHAR ucReserved[3]; 4864 ATOM_INIT_REG_BLOCK asMemTrainingSetting; 4865}ATOM_MEMORY_TRAINING_INFO; 4866 4867 4868typedef struct SW_I2C_CNTL_DATA_PARAMETERS 4869{ 4870 UCHAR ucControl; 4871 UCHAR ucData; 4872 UCHAR ucSatus; 4873 UCHAR ucTemp; 4874} SW_I2C_CNTL_DATA_PARAMETERS; 4875 4876#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS 4877 4878typedef struct _SW_I2C_IO_DATA_PARAMETERS 4879{ 4880 USHORT GPIO_Info; 4881 UCHAR ucAct; 4882 UCHAR ucData; 4883 } SW_I2C_IO_DATA_PARAMETERS; 4884 4885#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS 4886 4887/****************************SW I2C CNTL DEFINITIONS**********************/ 4888#define SW_I2C_IO_RESET 0 4889#define SW_I2C_IO_GET 1 4890#define SW_I2C_IO_DRIVE 2 4891#define SW_I2C_IO_SET 3 4892#define SW_I2C_IO_START 4 4893 4894#define SW_I2C_IO_CLOCK 0 4895#define SW_I2C_IO_DATA 0x80 4896 4897#define SW_I2C_IO_ZERO 0 4898#define SW_I2C_IO_ONE 0x100 4899 4900#define SW_I2C_CNTL_READ 0 4901#define SW_I2C_CNTL_WRITE 1 4902#define SW_I2C_CNTL_START 2 4903#define SW_I2C_CNTL_STOP 3 4904#define SW_I2C_CNTL_OPEN 4 4905#define SW_I2C_CNTL_CLOSE 5 4906#define SW_I2C_CNTL_WRITE1BIT 6 4907 4908//==============================VESA definition Portion=============================== 4909#define VESA_OEM_PRODUCT_REV "01.00" 4910#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support 4911#define VESA_MODE_WIN_ATTRIBUTE 7 4912#define VESA_WIN_SIZE 64 4913 4914typedef struct _PTR_32_BIT_STRUCTURE 4915{ 4916 USHORT Offset16; 4917 USHORT Segment16; 4918} PTR_32_BIT_STRUCTURE; 4919 4920typedef union _PTR_32_BIT_UNION 4921{ 4922 PTR_32_BIT_STRUCTURE SegmentOffset; 4923 ULONG Ptr32_Bit; 4924} PTR_32_BIT_UNION; 4925 4926typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE 4927{ 4928 UCHAR VbeSignature[4]; 4929 USHORT VbeVersion; 4930 PTR_32_BIT_UNION OemStringPtr; 4931 UCHAR Capabilities[4]; 4932 PTR_32_BIT_UNION VideoModePtr; 4933 USHORT TotalMemory; 4934} VBE_1_2_INFO_BLOCK_UPDATABLE; 4935 4936 4937typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE 4938{ 4939 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; 4940 USHORT OemSoftRev; 4941 PTR_32_BIT_UNION OemVendorNamePtr; 4942 PTR_32_BIT_UNION OemProductNamePtr; 4943 PTR_32_BIT_UNION OemProductRevPtr; 4944} VBE_2_0_INFO_BLOCK_UPDATABLE; 4945 4946typedef union _VBE_VERSION_UNION 4947{ 4948 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; 4949 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; 4950} VBE_VERSION_UNION; 4951 4952typedef struct _VBE_INFO_BLOCK 4953{ 4954 VBE_VERSION_UNION UpdatableVBE_Info; 4955 UCHAR Reserved[222]; 4956 UCHAR OemData[256]; 4957} VBE_INFO_BLOCK; 4958 4959typedef struct _VBE_FP_INFO 4960{ 4961 USHORT HSize; 4962 USHORT VSize; 4963 USHORT FPType; 4964 UCHAR RedBPP; 4965 UCHAR GreenBPP; 4966 UCHAR BlueBPP; 4967 UCHAR ReservedBPP; 4968 ULONG RsvdOffScrnMemSize; 4969 ULONG RsvdOffScrnMEmPtr; 4970 UCHAR Reserved[14]; 4971} VBE_FP_INFO; 4972 4973typedef struct _VESA_MODE_INFO_BLOCK 4974{ 4975// Mandatory information for all VBE revisions 4976 USHORT ModeAttributes; // dw ? ; mode attributes 4977 UCHAR WinAAttributes; // db ? ; window A attributes 4978 UCHAR WinBAttributes; // db ? ; window B attributes 4979 USHORT WinGranularity; // dw ? ; window granularity 4980 USHORT WinSize; // dw ? ; window size 4981 USHORT WinASegment; // dw ? ; window A start segment 4982 USHORT WinBSegment; // dw ? ; window B start segment 4983 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function 4984 USHORT BytesPerScanLine;// dw ? ; bytes per scan line 4985 4986//; Mandatory information for VBE 1.2 and above 4987 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters 4988 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters 4989 UCHAR XCharSize; // db ? ; character cell width in pixels 4990 UCHAR YCharSize; // db ? ; character cell height in pixels 4991 UCHAR NumberOfPlanes; // db ? ; number of memory planes 4992 UCHAR BitsPerPixel; // db ? ; bits per pixel 4993 UCHAR NumberOfBanks; // db ? ; number of banks 4994 UCHAR MemoryModel; // db ? ; memory model type 4995 UCHAR BankSize; // db ? ; bank size in KB 4996 UCHAR NumberOfImagePages;// db ? ; number of images 4997 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function 4998 4999//; Direct Color fields(required for direct/6 and YUV/7 memory models) 5000 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits 5001 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask 5002 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits 5003 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask 5004 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits 5005 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask 5006 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits 5007 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask 5008 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes 5009 5010//; Mandatory information for VBE 2.0 and above 5011 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer 5012 ULONG Reserved_1; // dd 0 ; reserved - always set to 0 5013 USHORT Reserved_2; // dw 0 ; reserved - always set to 0 5014 5015//; Mandatory information for VBE 3.0 and above 5016 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes 5017 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes 5018 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes 5019 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) 5020 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) 5021 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) 5022 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) 5023 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) 5024 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) 5025 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) 5026 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) 5027 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode 5028 UCHAR Reserved; // db 190 dup (0) 5029} VESA_MODE_INFO_BLOCK; 5030 5031// BIOS function CALLS 5032#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code 5033#define ATOM_BIOS_FUNCTION_COP_MODE 0x00 5034#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 5035#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 5036#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 5037#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B 5038#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E 5039#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F 5040#define ATOM_BIOS_FUNCTION_STV_STD 0x16 5041#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 5042#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 5043 5044#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 5045#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 5046#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 5047#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A 5048#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B 5049#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 5050#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 5051 5052#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D 5053#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E 5054#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F 5055#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 5056#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 5057#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state 5058#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state 5059#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 5060#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 5061#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported 5062 5063 5064#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS 5065#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 5066#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 5067#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. 5068#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY 5069#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND 5070#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF 5071#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) 5072 5073#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L 5074#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L 5075#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL 5076 5077// structure used for VBIOS only 5078 5079//DispOutInfoTable 5080typedef struct _ASIC_TRANSMITTER_INFO 5081{ 5082 USHORT usTransmitterObjId; 5083 USHORT usSupportDevice; 5084 UCHAR ucTransmitterCmdTblId; 5085 UCHAR ucConfig; 5086 UCHAR ucEncoderID; //available 1st encoder ( default ) 5087 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) 5088 UCHAR uc2ndEncoderID; 5089 UCHAR ucReserved; 5090}ASIC_TRANSMITTER_INFO; 5091 5092typedef struct _ASIC_ENCODER_INFO 5093{ 5094 UCHAR ucEncoderID; 5095 UCHAR ucEncoderConfig; 5096 USHORT usEncoderCmdTblId; 5097}ASIC_ENCODER_INFO; 5098 5099typedef struct _ATOM_DISP_OUT_INFO 5100{ 5101 ATOM_COMMON_TABLE_HEADER sHeader; 5102 USHORT ptrTransmitterInfo; 5103 USHORT ptrEncoderInfo; 5104 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 5105 ASIC_ENCODER_INFO asEncoderInfo[1]; 5106}ATOM_DISP_OUT_INFO; 5107 5108typedef struct _ATOM_DISP_OUT_INFO_V2 5109{ 5110 ATOM_COMMON_TABLE_HEADER sHeader; 5111 USHORT ptrTransmitterInfo; 5112 USHORT ptrEncoderInfo; 5113 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 5114 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 5115 ASIC_ENCODER_INFO asEncoderInfo[1]; 5116}ATOM_DISP_OUT_INFO_V2; 5117 5118// DispDevicePriorityInfo 5119typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO 5120{ 5121 ATOM_COMMON_TABLE_HEADER sHeader; 5122 USHORT asDevicePriority[16]; 5123}ATOM_DISPLAY_DEVICE_PRIORITY_INFO; 5124 5125//ProcessAuxChannelTransactionTable 5126typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 5127{ 5128 USHORT lpAuxRequest; 5129 USHORT lpDataOut; 5130 UCHAR ucChannelID; 5131 union 5132 { 5133 UCHAR ucReplyStatus; 5134 UCHAR ucDelay; 5135 }; 5136 UCHAR ucDataOutLen; 5137 UCHAR ucReserved; 5138}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; 5139 5140//ProcessAuxChannelTransactionTable 5141typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 5142{ 5143 USHORT lpAuxRequest; 5144 USHORT lpDataOut; 5145 UCHAR ucChannelID; 5146 union 5147 { 5148 UCHAR ucReplyStatus; 5149 UCHAR ucDelay; 5150 }; 5151 UCHAR ucDataOutLen; 5152 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 5153}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; 5154 5155#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 5156 5157//GetSinkType 5158 5159typedef struct _DP_ENCODER_SERVICE_PARAMETERS 5160{ 5161 USHORT ucLinkClock; 5162 union 5163 { 5164 UCHAR ucConfig; // for DP training command 5165 UCHAR ucI2cId; // use for GET_SINK_TYPE command 5166 }; 5167 UCHAR ucAction; 5168 UCHAR ucStatus; 5169 UCHAR ucLaneNum; 5170 UCHAR ucReserved[2]; 5171}DP_ENCODER_SERVICE_PARAMETERS; 5172 5173// ucAction 5174#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 5175/* obselete */ 5176#define ATOM_DP_ACTION_TRAINING_START 0x02 5177#define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 5178#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 5179#define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05 5180#define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 5181#define ATOM_DP_ACTION_BLANKING 0x07 5182 5183// ucConfig 5184#define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 5185#define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 5186#define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 5187#define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02 5188#define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 5189#define ATOM_DP_CONFIG_LINK_A 0x00 5190#define ATOM_DP_CONFIG_LINK_B 0x04 5191/* /obselete */ 5192#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 5193 5194// DP_TRAINING_TABLE 5195#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR 5196#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) 5197#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) 5198#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) 5199#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) 5200#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) 5201#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) 5202#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) 5203#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) 5204#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) 5205#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) 5206#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) 5207#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) 5208 5209typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 5210{ 5211 UCHAR ucI2CSpeed; 5212 union 5213 { 5214 UCHAR ucRegIndex; 5215 UCHAR ucStatus; 5216 }; 5217 USHORT lpI2CDataOut; 5218 UCHAR ucFlag; 5219 UCHAR ucTransBytes; 5220 UCHAR ucSlaveAddr; 5221 UCHAR ucLineNumber; 5222}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; 5223 5224#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 5225 5226//ucFlag 5227#define HW_I2C_WRITE 1 5228#define HW_I2C_READ 0 5229#define I2C_2BYTE_ADDR 0x02 5230 5231typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 5232{ 5233 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... 5234 UCHAR ucReserved[3]; 5235}SET_HWBLOCK_INSTANCE_PARAMETER_V2; 5236 5237#define HWBLKINST_INSTANCE_MASK 0x07 5238#define HWBLKINST_HWBLK_MASK 0xF0 5239#define HWBLKINST_HWBLK_SHIFT 0x04 5240 5241//ucHWBlock 5242#define SELECT_DISP_ENGINE 0 5243#define SELECT_DISP_PLL 1 5244#define SELECT_DCIO_UNIPHY_LINK0 2 5245#define SELECT_DCIO_UNIPHY_LINK1 3 5246#define SELECT_DCIO_IMPCAL 4 5247#define SELECT_DCIO_DIG 6 5248#define SELECT_CRTC_PIXEL_RATE 7 5249 5250/****************************************************************************/ 5251//Portion VI: Definitinos for vbios MC scratch registers that driver used 5252/****************************************************************************/ 5253 5254#define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 5255#define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 5256#define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 5257#define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 5258#define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 5259#define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 5260#define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 5261 5262/****************************************************************************/ 5263//Portion VI: Definitinos being oboselete 5264/****************************************************************************/ 5265 5266//========================================================================================== 5267//Remove the definitions below when driver is ready! 5268typedef struct _ATOM_DAC_INFO 5269{ 5270 ATOM_COMMON_TABLE_HEADER sHeader; 5271 USHORT usMaxFrequency; // in 10kHz unit 5272 USHORT usReserved; 5273}ATOM_DAC_INFO; 5274 5275 5276typedef struct _COMPASSIONATE_DATA 5277{ 5278 ATOM_COMMON_TABLE_HEADER sHeader; 5279 5280 //============================== DAC1 portion 5281 UCHAR ucDAC1_BG_Adjustment; 5282 UCHAR ucDAC1_DAC_Adjustment; 5283 USHORT usDAC1_FORCE_Data; 5284 //============================== DAC2 portion 5285 UCHAR ucDAC2_CRT2_BG_Adjustment; 5286 UCHAR ucDAC2_CRT2_DAC_Adjustment; 5287 USHORT usDAC2_CRT2_FORCE_Data; 5288 USHORT usDAC2_CRT2_MUX_RegisterIndex; 5289 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 5290 UCHAR ucDAC2_NTSC_BG_Adjustment; 5291 UCHAR ucDAC2_NTSC_DAC_Adjustment; 5292 USHORT usDAC2_TV1_FORCE_Data; 5293 USHORT usDAC2_TV1_MUX_RegisterIndex; 5294 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 5295 UCHAR ucDAC2_CV_BG_Adjustment; 5296 UCHAR ucDAC2_CV_DAC_Adjustment; 5297 USHORT usDAC2_CV_FORCE_Data; 5298 USHORT usDAC2_CV_MUX_RegisterIndex; 5299 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 5300 UCHAR ucDAC2_PAL_BG_Adjustment; 5301 UCHAR ucDAC2_PAL_DAC_Adjustment; 5302 USHORT usDAC2_TV2_FORCE_Data; 5303}COMPASSIONATE_DATA; 5304 5305/****************************Supported Device Info Table Definitions**********************/ 5306// ucConnectInfo: 5307// [7:4] - connector type 5308// = 1 - VGA connector 5309// = 2 - DVI-I 5310// = 3 - DVI-D 5311// = 4 - DVI-A 5312// = 5 - SVIDEO 5313// = 6 - COMPOSITE 5314// = 7 - LVDS 5315// = 8 - DIGITAL LINK 5316// = 9 - SCART 5317// = 0xA - HDMI_type A 5318// = 0xB - HDMI_type B 5319// = 0xE - Special case1 (DVI+DIN) 5320// Others=TBD 5321// [3:0] - DAC Associated 5322// = 0 - no DAC 5323// = 1 - DACA 5324// = 2 - DACB 5325// = 3 - External DAC 5326// Others=TBD 5327// 5328 5329typedef struct _ATOM_CONNECTOR_INFO 5330{ 5331#if ATOM_BIG_ENDIAN 5332 UCHAR bfConnectorType:4; 5333 UCHAR bfAssociatedDAC:4; 5334#else 5335 UCHAR bfAssociatedDAC:4; 5336 UCHAR bfConnectorType:4; 5337#endif 5338}ATOM_CONNECTOR_INFO; 5339 5340typedef union _ATOM_CONNECTOR_INFO_ACCESS 5341{ 5342 ATOM_CONNECTOR_INFO sbfAccess; 5343 UCHAR ucAccess; 5344}ATOM_CONNECTOR_INFO_ACCESS; 5345 5346typedef struct _ATOM_CONNECTOR_INFO_I2C 5347{ 5348 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; 5349 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 5350}ATOM_CONNECTOR_INFO_I2C; 5351 5352 5353typedef struct _ATOM_SUPPORTED_DEVICES_INFO 5354{ 5355 ATOM_COMMON_TABLE_HEADER sHeader; 5356 USHORT usDeviceSupport; 5357 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; 5358}ATOM_SUPPORTED_DEVICES_INFO; 5359 5360#define NO_INT_SRC_MAPPED 0xFF 5361 5362typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP 5363{ 5364 UCHAR ucIntSrcBitmap; 5365}ATOM_CONNECTOR_INC_SRC_BITMAP; 5366 5367typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 5368{ 5369 ATOM_COMMON_TABLE_HEADER sHeader; 5370 USHORT usDeviceSupport; 5371 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 5372 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 5373}ATOM_SUPPORTED_DEVICES_INFO_2; 5374 5375typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 5376{ 5377 ATOM_COMMON_TABLE_HEADER sHeader; 5378 USHORT usDeviceSupport; 5379 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; 5380 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; 5381}ATOM_SUPPORTED_DEVICES_INFO_2d1; 5382 5383#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 5384 5385 5386 5387typedef struct _ATOM_MISC_CONTROL_INFO 5388{ 5389 USHORT usFrequency; 5390 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control 5391 UCHAR ucPLL_DutyCycle; // PLL duty cycle control 5392 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control 5393 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control 5394}ATOM_MISC_CONTROL_INFO; 5395 5396 5397#define ATOM_MAX_MISC_INFO 4 5398 5399typedef struct _ATOM_TMDS_INFO 5400{ 5401 ATOM_COMMON_TABLE_HEADER sHeader; 5402 USHORT usMaxFrequency; // in 10Khz 5403 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; 5404}ATOM_TMDS_INFO; 5405 5406 5407typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE 5408{ 5409 UCHAR ucTVStandard; //Same as TV standards defined above, 5410 UCHAR ucPadding[1]; 5411}ATOM_ENCODER_ANALOG_ATTRIBUTE; 5412 5413typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE 5414{ 5415 UCHAR ucAttribute; //Same as other digital encoder attributes defined above 5416 UCHAR ucPadding[1]; 5417}ATOM_ENCODER_DIGITAL_ATTRIBUTE; 5418 5419typedef union _ATOM_ENCODER_ATTRIBUTE 5420{ 5421 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; 5422 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; 5423}ATOM_ENCODER_ATTRIBUTE; 5424 5425 5426typedef struct _DVO_ENCODER_CONTROL_PARAMETERS 5427{ 5428 USHORT usPixelClock; 5429 USHORT usEncoderID; 5430 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. 5431 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 5432 ATOM_ENCODER_ATTRIBUTE usDevAttr; 5433}DVO_ENCODER_CONTROL_PARAMETERS; 5434 5435typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION 5436{ 5437 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; 5438 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 5439}DVO_ENCODER_CONTROL_PS_ALLOCATION; 5440 5441 5442#define ATOM_XTMDS_ASIC_SI164_ID 1 5443#define ATOM_XTMDS_ASIC_SI178_ID 2 5444#define ATOM_XTMDS_ASIC_TFP513_ID 3 5445#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 5446#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 5447#define ATOM_XTMDS_MVPU_FPGA 0x00000004 5448 5449 5450typedef struct _ATOM_XTMDS_INFO 5451{ 5452 ATOM_COMMON_TABLE_HEADER sHeader; 5453 USHORT usSingleLinkMaxFrequency; 5454 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip 5455 UCHAR ucXtransimitterID; 5456 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported 5457 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters 5458 // due to design. This ID is used to alert driver that the sequence is not "standard"! 5459 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip 5460 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip 5461}ATOM_XTMDS_INFO; 5462 5463typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS 5464{ 5465 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off 5466 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... 5467 UCHAR ucPadding[2]; 5468}DFP_DPMS_STATUS_CHANGE_PARAMETERS; 5469 5470/****************************Legacy Power Play Table Definitions **********************/ 5471 5472//Definitions for ulPowerPlayMiscInfo 5473#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L 5474#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L 5475#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L 5476 5477#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L 5478#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L 5479 5480#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L 5481 5482#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L 5483#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L 5484#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program 5485 5486#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L 5487#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L 5488#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L 5489#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L 5490#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L 5491#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L 5492#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L 5493 5494#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L 5495#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L 5496#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L 5497#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L 5498#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L 5499 5500#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved 5501#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 5502 5503#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L 5504#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L 5505#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L 5506#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic 5507#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic 5508#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode 5509 5510#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) 5511#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 5512#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L 5513 5514#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L 5515#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L 5516#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L 5517#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L 5518#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L 5519#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L 5520#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. 5521 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback 5522#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L 5523#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L 5524#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L 5525 5526//ucTableFormatRevision=1 5527//ucTableContentRevision=1 5528typedef struct _ATOM_POWERMODE_INFO 5529{ 5530 ULONG ulMiscInfo; //The power level should be arranged in ascending order 5531 ULONG ulReserved1; // must set to 0 5532 ULONG ulReserved2; // must set to 0 5533 USHORT usEngineClock; 5534 USHORT usMemoryClock; 5535 UCHAR ucVoltageDropIndex; // index to GPIO table 5536 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 5537 UCHAR ucMinTemperature; 5538 UCHAR ucMaxTemperature; 5539 UCHAR ucNumPciELanes; // number of PCIE lanes 5540}ATOM_POWERMODE_INFO; 5541 5542//ucTableFormatRevision=2 5543//ucTableContentRevision=1 5544typedef struct _ATOM_POWERMODE_INFO_V2 5545{ 5546 ULONG ulMiscInfo; //The power level should be arranged in ascending order 5547 ULONG ulMiscInfo2; 5548 ULONG ulEngineClock; 5549 ULONG ulMemoryClock; 5550 UCHAR ucVoltageDropIndex; // index to GPIO table 5551 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 5552 UCHAR ucMinTemperature; 5553 UCHAR ucMaxTemperature; 5554 UCHAR ucNumPciELanes; // number of PCIE lanes 5555}ATOM_POWERMODE_INFO_V2; 5556 5557//ucTableFormatRevision=2 5558//ucTableContentRevision=2 5559typedef struct _ATOM_POWERMODE_INFO_V3 5560{ 5561 ULONG ulMiscInfo; //The power level should be arranged in ascending order 5562 ULONG ulMiscInfo2; 5563 ULONG ulEngineClock; 5564 ULONG ulMemoryClock; 5565 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table 5566 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 5567 UCHAR ucMinTemperature; 5568 UCHAR ucMaxTemperature; 5569 UCHAR ucNumPciELanes; // number of PCIE lanes 5570 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table 5571}ATOM_POWERMODE_INFO_V3; 5572 5573 5574#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 5575 5576#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 5577#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 5578 5579#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 5580#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 5581#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 5582#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 5583#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 5584#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 5585#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog 5586 5587 5588typedef struct _ATOM_POWERPLAY_INFO 5589{ 5590 ATOM_COMMON_TABLE_HEADER sHeader; 5591 UCHAR ucOverdriveThermalController; 5592 UCHAR ucOverdriveI2cLine; 5593 UCHAR ucOverdriveIntBitmap; 5594 UCHAR ucOverdriveControllerAddress; 5595 UCHAR ucSizeOfPowerModeEntry; 5596 UCHAR ucNumOfPowerModeEntries; 5597 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 5598}ATOM_POWERPLAY_INFO; 5599 5600typedef struct _ATOM_POWERPLAY_INFO_V2 5601{ 5602 ATOM_COMMON_TABLE_HEADER sHeader; 5603 UCHAR ucOverdriveThermalController; 5604 UCHAR ucOverdriveI2cLine; 5605 UCHAR ucOverdriveIntBitmap; 5606 UCHAR ucOverdriveControllerAddress; 5607 UCHAR ucSizeOfPowerModeEntry; 5608 UCHAR ucNumOfPowerModeEntries; 5609 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 5610}ATOM_POWERPLAY_INFO_V2; 5611 5612typedef struct _ATOM_POWERPLAY_INFO_V3 5613{ 5614 ATOM_COMMON_TABLE_HEADER sHeader; 5615 UCHAR ucOverdriveThermalController; 5616 UCHAR ucOverdriveI2cLine; 5617 UCHAR ucOverdriveIntBitmap; 5618 UCHAR ucOverdriveControllerAddress; 5619 UCHAR ucSizeOfPowerModeEntry; 5620 UCHAR ucNumOfPowerModeEntries; 5621 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 5622}ATOM_POWERPLAY_INFO_V3; 5623 5624/* New PPlib */ 5625/**************************************************************************/ 5626typedef struct _ATOM_PPLIB_THERMALCONTROLLER 5627 5628{ 5629 UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* 5630 UCHAR ucI2cLine; // as interpreted by DAL I2C 5631 UCHAR ucI2cAddress; 5632 UCHAR ucFanParameters; // Fan Control Parameters. 5633 UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. 5634 UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. 5635 UCHAR ucReserved; // ---- 5636 UCHAR ucFlags; // to be defined 5637} ATOM_PPLIB_THERMALCONTROLLER; 5638 5639#define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f 5640#define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. 5641 5642#define ATOM_PP_THERMALCONTROLLER_NONE 0 5643#define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib 5644#define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib 5645#define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib 5646#define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib 5647#define ATOM_PP_THERMALCONTROLLER_LM64 5 5648#define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib 5649#define ATOM_PP_THERMALCONTROLLER_RV6xx 7 5650#define ATOM_PP_THERMALCONTROLLER_RV770 8 5651#define ATOM_PP_THERMALCONTROLLER_ADT7473 9 5652#define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 5653#define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 5654#define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller 5655 5656typedef struct _ATOM_PPLIB_STATE 5657{ 5658 UCHAR ucNonClockStateIndex; 5659 UCHAR ucClockStateIndices[1]; // variable-sized 5660} ATOM_PPLIB_STATE; 5661 5662typedef struct _ATOM_PPLIB_FANTABLE 5663{ 5664 UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. 5665 UCHAR ucTHyst; // Temperature hysteresis. Integer. 5666 USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. 5667 USHORT usTMed; // The middle temperature where we change slopes. 5668 USHORT usTHigh; // The high point above TMed for adjusting the second slope. 5669 USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). 5670 USHORT usPWMMed; // The PWM value (in percent) at TMed. 5671 USHORT usPWMHigh; // The PWM value at THigh. 5672} ATOM_PPLIB_FANTABLE; 5673 5674typedef struct _ATOM_PPLIB_EXTENDEDHEADER 5675{ 5676 USHORT usSize; 5677 ULONG ulMaxEngineClock; // For Overdrive. 5678 ULONG ulMaxMemoryClock; // For Overdrive. 5679 // Add extra system parameters here, always adjust size to include all fields. 5680} ATOM_PPLIB_EXTENDEDHEADER; 5681 5682//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps 5683#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 5684#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 5685#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 5686#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 5687#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 5688#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 5689#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 5690#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 5691#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 5692#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 5693#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 5694#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 5695#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 5696#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. 5697#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). 5698#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. 5699#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. 5700#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. 5701 5702typedef struct _ATOM_PPLIB_POWERPLAYTABLE 5703{ 5704 ATOM_COMMON_TABLE_HEADER sHeader; 5705 5706 UCHAR ucDataRevision; 5707 5708 UCHAR ucNumStates; 5709 UCHAR ucStateEntrySize; 5710 UCHAR ucClockInfoSize; 5711 UCHAR ucNonClockSize; 5712 5713 // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures 5714 USHORT usStateArrayOffset; 5715 5716 // offset from start of this table to array of ASIC-specific structures, 5717 // currently ATOM_PPLIB_CLOCK_INFO. 5718 USHORT usClockInfoArrayOffset; 5719 5720 // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO 5721 USHORT usNonClockInfoArrayOffset; 5722 5723 USHORT usBackbiasTime; // in microseconds 5724 USHORT usVoltageTime; // in microseconds 5725 USHORT usTableSize; //the size of this structure, or the extended structure 5726 5727 ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* 5728 5729 ATOM_PPLIB_THERMALCONTROLLER sThermalController; 5730 5731 USHORT usBootClockInfoOffset; 5732 USHORT usBootNonClockInfoOffset; 5733 5734} ATOM_PPLIB_POWERPLAYTABLE; 5735 5736typedef struct _ATOM_PPLIB_POWERPLAYTABLE2 5737{ 5738 ATOM_PPLIB_POWERPLAYTABLE basicTable; 5739 UCHAR ucNumCustomThermalPolicy; 5740 USHORT usCustomThermalPolicyArrayOffset; 5741}ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; 5742 5743typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 5744{ 5745 ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; 5746 USHORT usFormatID; // To be used ONLY by PPGen. 5747 USHORT usFanTableOffset; 5748 USHORT usExtendendedHeaderOffset; 5749} ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; 5750 5751//// ATOM_PPLIB_NONCLOCK_INFO::usClassification 5752#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 5753#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 5754#define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 5755#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 5756#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 5757#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 5758// 2, 4, 6, 7 are reserved 5759 5760#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 5761#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 5762#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 5763#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 5764#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 5765#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 5766#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 5767#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 5768#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 5769#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 5770#define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 5771#define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 5772#define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 5773 5774//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings 5775#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 5776#define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 5777 5778// 0 is 2.5Gb/s, 1 is 5Gb/s 5779#define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 5780#define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 5781 5782// lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec 5783#define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 5784#define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 5785 5786// lookup into reduced refresh-rate table 5787#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 5788#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 5789 5790#define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 5791#define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 5792// 2-15 TBD as needed. 5793 5794#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 5795#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 5796#define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 5797#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 5798 5799//memory related flags 5800#define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 5801 5802//M3 Arb //2bits, current 3 sets of parameters in total 5803#define ATOM_PPLIB_M3ARB_MASK 0x00060000 5804#define ATOM_PPLIB_M3ARB_SHIFT 17 5805 5806// Contained in an array starting at the offset 5807// in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. 5808// referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex 5809typedef struct _ATOM_PPLIB_NONCLOCK_INFO 5810{ 5811 USHORT usClassification; 5812 UCHAR ucMinTemperature; 5813 UCHAR ucMaxTemperature; 5814 ULONG ulCapsAndSettings; 5815 UCHAR ucRequiredPower; 5816 UCHAR ucUnused1[3]; 5817} ATOM_PPLIB_NONCLOCK_INFO; 5818 5819// Contained in an array starting at the offset 5820// in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. 5821// referenced from ATOM_PPLIB_STATE::ucClockStateIndices 5822#define ATOM_PPLIB_NONCLOCKINFO_VER1 12 5823#define ATOM_PPLIB_NONCLOCKINFO_VER2 24 5824 5825typedef struct _ATOM_PPLIB_R600_CLOCK_INFO 5826{ 5827 USHORT usEngineClockLow; 5828 UCHAR ucEngineClockHigh; 5829 5830 USHORT usMemoryClockLow; 5831 UCHAR ucMemoryClockHigh; 5832 5833 USHORT usVDDC; 5834 USHORT usUnused1; 5835 USHORT usUnused2; 5836 5837 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 5838 5839} ATOM_PPLIB_R600_CLOCK_INFO; 5840 5841// ulFlags in ATOM_PPLIB_R600_CLOCK_INFO 5842#define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 5843#define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 5844#define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 5845#define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 5846#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 5847#define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). 5848 5849typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO 5850{ 5851 USHORT usEngineClockLow; 5852 UCHAR ucEngineClockHigh; 5853 5854 USHORT usMemoryClockLow; 5855 UCHAR ucMemoryClockHigh; 5856 5857 USHORT usVDDC; 5858 USHORT usVDDCI; 5859 USHORT usUnused; 5860 5861 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 5862 5863} ATOM_PPLIB_EVERGREEN_CLOCK_INFO; 5864 5865typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO 5866 5867{ 5868 USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). 5869 UCHAR ucLowEngineClockHigh; 5870 USHORT usHighEngineClockLow; // High Engine clock in MHz. 5871 UCHAR ucHighEngineClockHigh; 5872 USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. 5873 UCHAR ucMemoryClockHigh; // Currentyl unused. 5874 UCHAR ucPadding; // For proper alignment and size. 5875 USHORT usVDDC; // For the 780, use: None, Low, High, Variable 5876 UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} 5877 UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requirement. 5878 USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). 5879 ULONG ulFlags; 5880} ATOM_PPLIB_RS780_CLOCK_INFO; 5881 5882#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 5883#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 5884#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 5885#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 5886 5887#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. 5888#define ATOM_PPLIB_RS780_SPMCLK_LOW 1 5889#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 5890 5891#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 5892#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 5893#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 5894 5895/**************************************************************************/ 5896 5897 5898// Following definitions are for compatiblity issue in different SW components. 5899#define ATOM_MASTER_DATA_TABLE_REVISION 0x01 5900#define Object_Info Object_Header 5901#define AdjustARB_SEQ MC_InitParameter 5902#define VRAM_GPIO_DetectionInfo VoltageObjectInfo 5903#define ASIC_VDDCI_Info ASIC_ProfilingInfo 5904#define ASIC_MVDDQ_Info MemoryTrainingInfo 5905#define SS_Info PPLL_SS_Info 5906#define ASIC_MVDDC_Info ASIC_InternalSS_Info 5907#define DispDevicePriorityInfo SaveRestoreInfo 5908#define DispOutInfo TV_VideoMode 5909 5910 5911#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE 5912#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE 5913 5914//New device naming, remove them when both DAL/VBIOS is ready 5915#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 5916#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS 5917 5918#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 5919#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS 5920 5921#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS 5922#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION 5923 5924#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT 5925#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT 5926 5927#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX 5928#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX 5929 5930#define ATOM_DEVICE_DFP2I_INDEX 0x00000009 5931#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) 5932 5933#define ATOM_S0_DFP1I ATOM_S0_DFP1 5934#define ATOM_S0_DFP1X ATOM_S0_DFP2 5935 5936#define ATOM_S0_DFP2I 0x00200000L 5937#define ATOM_S0_DFP2Ib2 0x20 5938 5939#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE 5940#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE 5941 5942#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L 5943#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 5944 5945#define ATOM_S3_DFP2I_ACTIVEb1 0x02 5946 5947#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE 5948#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE 5949 5950#define ATOM_S3_DFP2I_ACTIVE 0x00000200L 5951 5952#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE 5953#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE 5954#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L 5955 5956#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 5957#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 5958 5959#define ATOM_S5_DOS_REQ_DFP2I 0x0200 5960#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 5961#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 5962 5963#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 5964#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L 5965 5966#define TMDS1XEncoderControl DVOEncoderControl 5967#define DFP1XOutputControl DVOOutputControl 5968 5969#define ExternalDFPOutputControl DFP1XOutputControl 5970#define EnableExternalTMDS_Encoder TMDS1XEncoderControl 5971 5972#define DFP1IOutputControl TMDSAOutputControl 5973#define DFP2IOutputControl LVTMAOutputControl 5974 5975#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 5976#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 5977 5978#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 5979#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 5980 5981#define ucDac1Standard ucDacStandard 5982#define ucDac2Standard ucDacStandard 5983 5984#define TMDS1EncoderControl TMDSAEncoderControl 5985#define TMDS2EncoderControl LVTMAEncoderControl 5986 5987#define DFP1OutputControl TMDSAOutputControl 5988#define DFP2OutputControl LVTMAOutputControl 5989#define CRT1OutputControl DAC1OutputControl 5990#define CRT2OutputControl DAC2OutputControl 5991 5992//These two lines will be removed for sure in a few days, will follow up with Michael V. 5993#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL 5994#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL 5995 5996//#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 5997//#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 5998//#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 5999//#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 6000//#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 6001 6002#define ATOM_S6_ACC_REQ_TV2 0x00400000L 6003#define ATOM_DEVICE_TV2_INDEX 0x00000006 6004#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) 6005#define ATOM_S0_TV2 0x00100000L 6006#define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE 6007#define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE 6008 6009// 6010#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 6011#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L 6012#define ATOM_S2_TV1_DPMS_STATE 0x00040000L 6013#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L 6014#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L 6015#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L 6016#define ATOM_S2_TV2_DPMS_STATE 0x00400000L 6017#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L 6018#define ATOM_S2_CV_DPMS_STATE 0x01000000L 6019#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L 6020#define ATOM_S2_DFP4_DPMS_STATE 0x04000000L 6021#define ATOM_S2_DFP5_DPMS_STATE 0x08000000L 6022 6023#define ATOM_S2_CRT1_DPMS_STATEb2 0x01 6024#define ATOM_S2_LCD1_DPMS_STATEb2 0x02 6025#define ATOM_S2_TV1_DPMS_STATEb2 0x04 6026#define ATOM_S2_DFP1_DPMS_STATEb2 0x08 6027#define ATOM_S2_CRT2_DPMS_STATEb2 0x10 6028#define ATOM_S2_LCD2_DPMS_STATEb2 0x20 6029#define ATOM_S2_TV2_DPMS_STATEb2 0x40 6030#define ATOM_S2_DFP2_DPMS_STATEb2 0x80 6031#define ATOM_S2_CV_DPMS_STATEb3 0x01 6032#define ATOM_S2_DFP3_DPMS_STATEb3 0x02 6033#define ATOM_S2_DFP4_DPMS_STATEb3 0x04 6034#define ATOM_S2_DFP5_DPMS_STATEb3 0x08 6035 6036#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 6037#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 6038#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 6039 6040/*********************************************************************************/ 6041 6042#pragma pack() // BIOS data must use byte aligment 6043 6044#endif /* _ATOMBIOS_H */ 6045