1/* 2 * Copyright 1993-2003 NVIDIA, Corporation 3 * Copyright 2006 Dave Airlie 4 * Copyright 2007 Maarten Maathuis 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 26#include "drmP.h" 27#include "drm_crtc_helper.h" 28 29#include "nouveau_drv.h" 30#include "nouveau_encoder.h" 31#include "nouveau_connector.h" 32#include "nouveau_crtc.h" 33#include "nouveau_fb.h" 34#include "nouveau_hw.h" 35#include "nvreg.h" 36 37static int 38nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 39 struct drm_framebuffer *old_fb); 40 41static void 42crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) 43{ 44 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, 45 crtcstate->CRTC[index]); 46} 47 48static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level) 49{ 50 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 51 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 52 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; 53 54 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; 55 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { 56 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; 57 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; 58 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); 59 } 60 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); 61} 62 63static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level) 64{ 65 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 66 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 67 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; 68 69 nv_crtc->sharpness = level; 70 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */ 71 level += 0x40; 72 regp->ramdac_634 = level; 73 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); 74} 75 76#define PLLSEL_VPLL1_MASK \ 77 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \ 78 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2) 79#define PLLSEL_VPLL2_MASK \ 80 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \ 81 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2) 82#define PLLSEL_TV_MASK \ 83 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \ 84 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \ 85 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \ 86 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2) 87 88/* NV4x 0x40.. pll notes: 89 * gpu pll: 0x4000 + 0x4004 90 * ?gpu? pll: 0x4008 + 0x400c 91 * vpll1: 0x4010 + 0x4014 92 * vpll2: 0x4018 + 0x401c 93 * mpll: 0x4020 + 0x4024 94 * mpll: 0x4038 + 0x403c 95 * 96 * the first register of each pair has some unknown details: 97 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?) 98 * bits 20-23: (mpll) something to do with post divider? 99 * bits 28-31: related to single stage mode? (bit 8/12) 100 */ 101 102static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock) 103{ 104 struct drm_device *dev = crtc->dev; 105 struct drm_nouveau_private *dev_priv = dev->dev_private; 106 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 107 struct nv04_mode_state *state = &dev_priv->mode_reg; 108 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; 109 struct nouveau_pll_vals *pv = ®p->pllvals; 110 struct pll_lims pll_lim; 111 112 if (get_pll_limits(dev, nv_crtc->index ? VPLL2 : VPLL1, &pll_lim)) 113 return; 114 115 /* NM2 == 0 is used to determine single stage mode on two stage plls */ 116 pv->NM2 = 0; 117 118 /* for newer nv4x the blob uses only the first stage of the vpll below a 119 * certain clock. for a certain nv4b this is 150MHz. since the max 120 * output frequency of the first stage for this card is 300MHz, it is 121 * assumed the threshold is given by vco1 maxfreq/2 122 */ 123 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6, 124 * not 8, others unknown), the blob always uses both plls. no problem 125 * has yet been observed in allowing the use a single stage pll on all 126 * nv43 however. the behaviour of single stage use is untested on nv40 127 */ 128 if (dev_priv->chipset > 0x40 && dot_clock <= (pll_lim.vco1.maxfreq / 2)) 129 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); 130 131 if (!nouveau_calc_pll_mnp(dev, &pll_lim, dot_clock, pv)) 132 return; 133 134 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK; 135 136 /* The blob uses this always, so let's do the same */ 137 if (dev_priv->card_type == NV_40) 138 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE; 139 /* again nv40 and some nv43 act more like nv3x as described above */ 140 if (dev_priv->chipset < 0x41) 141 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL | 142 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL; 143 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; 144 145 if (pv->NM2) 146 NV_DEBUG_KMS(dev, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", 147 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); 148 else 149 NV_DEBUG_KMS(dev, "vpll: n %d m %d log2p %d\n", 150 pv->N1, pv->M1, pv->log2P); 151 152 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 153} 154 155static void 156nv_crtc_dpms(struct drm_crtc *crtc, int mode) 157{ 158 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 159 struct drm_device *dev = crtc->dev; 160 struct drm_connector *connector; 161 unsigned char seq1 = 0, crtc17 = 0; 162 unsigned char crtc1A; 163 164 NV_DEBUG_KMS(dev, "Setting dpms mode %d on CRTC %d\n", mode, 165 nv_crtc->index); 166 167 if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */ 168 return; 169 170 nv_crtc->last_dpms = mode; 171 172 if (nv_two_heads(dev)) 173 NVSetOwner(dev, nv_crtc->index); 174 175 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */ 176 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, 177 NV_CIO_CRE_RPC1_INDEX) & ~0xC0; 178 switch (mode) { 179 case DRM_MODE_DPMS_STANDBY: 180 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */ 181 seq1 = 0x20; 182 crtc17 = 0x80; 183 crtc1A |= 0x80; 184 break; 185 case DRM_MODE_DPMS_SUSPEND: 186 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */ 187 seq1 = 0x20; 188 crtc17 = 0x80; 189 crtc1A |= 0x40; 190 break; 191 case DRM_MODE_DPMS_OFF: 192 /* Screen: Off; HSync: Off, VSync: Off */ 193 seq1 = 0x20; 194 crtc17 = 0x00; 195 crtc1A |= 0xC0; 196 break; 197 case DRM_MODE_DPMS_ON: 198 default: 199 /* Screen: On; HSync: On, VSync: On */ 200 seq1 = 0x00; 201 crtc17 = 0x80; 202 break; 203 } 204 205 NVVgaSeqReset(dev, nv_crtc->index, true); 206 /* Each head has it's own sequencer, so we can turn it off when we want */ 207 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); 208 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); 209 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); 210 mdelay(10); 211 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); 212 NVVgaSeqReset(dev, nv_crtc->index, false); 213 214 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); 215 216 /* Update connector polling modes */ 217 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 218 nouveau_connector_set_polling(connector); 219} 220 221static bool 222nv_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode, 223 struct drm_display_mode *adjusted_mode) 224{ 225 return true; 226} 227 228static void 229nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) 230{ 231 struct drm_device *dev = crtc->dev; 232 struct drm_nouveau_private *dev_priv = dev->dev_private; 233 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 234 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; 235 struct drm_framebuffer *fb = crtc->fb; 236 237 /* Calculate our timings */ 238 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; 239 int horizStart = (mode->crtc_hsync_start >> 3) + 1; 240 int horizEnd = (mode->crtc_hsync_end >> 3) + 1; 241 int horizTotal = (mode->crtc_htotal >> 3) - 5; 242 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1; 243 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1; 244 int vertDisplay = mode->crtc_vdisplay - 1; 245 int vertStart = mode->crtc_vsync_start - 1; 246 int vertEnd = mode->crtc_vsync_end - 1; 247 int vertTotal = mode->crtc_vtotal - 2; 248 int vertBlankStart = mode->crtc_vdisplay - 1; 249 int vertBlankEnd = mode->crtc_vtotal - 1; 250 251 struct drm_encoder *encoder; 252 bool fp_output = false; 253 254 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 255 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 256 257 if (encoder->crtc == crtc && 258 (nv_encoder->dcb->type == OUTPUT_LVDS || 259 nv_encoder->dcb->type == OUTPUT_TMDS)) 260 fp_output = true; 261 } 262 263 if (fp_output) { 264 vertStart = vertTotal - 3; 265 vertEnd = vertTotal - 2; 266 vertBlankStart = vertStart; 267 horizStart = horizTotal - 5; 268 horizEnd = horizTotal - 2; 269 horizBlankEnd = horizTotal + 4; 270 } 271 272 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 273 vertTotal |= 1; 274 275 276 /* 277 * compute correct Hsync & Vsync polarity 278 */ 279 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)) 280 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) { 281 282 regp->MiscOutReg = 0x23; 283 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 284 regp->MiscOutReg |= 0x40; 285 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 286 regp->MiscOutReg |= 0x80; 287 } else { 288 int vdisplay = mode->vdisplay; 289 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 290 vdisplay *= 2; 291 if (mode->vscan > 1) 292 vdisplay *= mode->vscan; 293 if (vdisplay < 400) 294 regp->MiscOutReg = 0xA3; /* +hsync -vsync */ 295 else if (vdisplay < 480) 296 regp->MiscOutReg = 0x63; /* -hsync +vsync */ 297 else if (vdisplay < 768) 298 regp->MiscOutReg = 0xE3; /* -hsync -vsync */ 299 else 300 regp->MiscOutReg = 0x23; /* +hsync +vsync */ 301 } 302 303 regp->MiscOutReg |= (mode->clock_index & 0x03) << 2; 304 305 /* 306 * Time Sequencer 307 */ 308 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; 309 /* 0x20 disables the sequencer */ 310 if (mode->flags & DRM_MODE_FLAG_CLKDIV2) 311 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; 312 else 313 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; 314 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; 315 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; 316 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; 317 318 /* 319 * CRTC 320 */ 321 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; 322 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; 323 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; 324 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | 325 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0); 326 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; 327 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | 328 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0); 329 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; 330 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | 331 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) | 332 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) | 333 (1 << 4) | 334 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) | 335 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) | 336 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) | 337 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8); 338 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; 339 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | 340 1 << 6 | 341 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9); 342 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; 343 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; 344 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; 345 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; 346 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; 347 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; 348 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; 349 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); 350 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; 351 /* framebuffer can be larger than crtc scanout area. */ 352 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitch / 8; 353 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; 354 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; 355 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; 356 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; 357 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; 358 359 /* 360 * Some extended CRTC registers (they are not saved with the rest of the vga regs). 361 */ 362 363 /* framebuffer can be larger than crtc scanout area. */ 364 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = XLATE(fb->pitch / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 365 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? 366 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; 367 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | 368 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) | 369 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) | 370 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) | 371 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10); 372 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | 373 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) | 374 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) | 375 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8); 376 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | 377 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) | 378 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) | 379 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11); 380 381 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 382 horizTotal = (horizTotal >> 1) & ~1; 383 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; 384 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); 385 } else 386 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ 387 388 /* 389 * Graphics Display Controller 390 */ 391 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; 392 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; 393 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; 394 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; 395 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; 396 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ 397 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ 398 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; 399 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; 400 401 regp->Attribute[0] = 0x00; /* standard colormap translation */ 402 regp->Attribute[1] = 0x01; 403 regp->Attribute[2] = 0x02; 404 regp->Attribute[3] = 0x03; 405 regp->Attribute[4] = 0x04; 406 regp->Attribute[5] = 0x05; 407 regp->Attribute[6] = 0x06; 408 regp->Attribute[7] = 0x07; 409 regp->Attribute[8] = 0x08; 410 regp->Attribute[9] = 0x09; 411 regp->Attribute[10] = 0x0A; 412 regp->Attribute[11] = 0x0B; 413 regp->Attribute[12] = 0x0C; 414 regp->Attribute[13] = 0x0D; 415 regp->Attribute[14] = 0x0E; 416 regp->Attribute[15] = 0x0F; 417 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ 418 /* Non-vga */ 419 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; 420 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ 421 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; 422 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; 423} 424 425/** 426 * Sets up registers for the given mode/adjusted_mode pair. 427 * 428 * The clocks, CRTCs and outputs attached to this CRTC must be off. 429 * 430 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 431 * be easily turned on/off after this. 432 */ 433static void 434nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) 435{ 436 struct drm_device *dev = crtc->dev; 437 struct drm_nouveau_private *dev_priv = dev->dev_private; 438 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 439 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; 440 struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index]; 441 struct drm_encoder *encoder; 442 bool lvds_output = false, tmds_output = false, tv_output = false, 443 off_chip_digital = false; 444 445 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 446 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 447 bool digital = false; 448 449 if (encoder->crtc != crtc) 450 continue; 451 452 if (nv_encoder->dcb->type == OUTPUT_LVDS) 453 digital = lvds_output = true; 454 if (nv_encoder->dcb->type == OUTPUT_TV) 455 tv_output = true; 456 if (nv_encoder->dcb->type == OUTPUT_TMDS) 457 digital = tmds_output = true; 458 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital) 459 off_chip_digital = true; 460 } 461 462 /* Registers not directly related to the (s)vga mode */ 463 464 /* What is the meaning of this register? */ 465 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */ 466 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); 467 468 regp->crtc_eng_ctrl = 0; 469 /* Except for rare conditions I2C is enabled on the primary crtc */ 470 if (nv_crtc->index == 0) 471 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C; 472 473 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */ 474 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | 475 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | 476 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM; 477 if (dev_priv->chipset >= 0x11) 478 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; 479 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 480 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; 481 482 /* Unblock some timings */ 483 regp->CRTC[NV_CIO_CRE_53] = 0; 484 regp->CRTC[NV_CIO_CRE_54] = 0; 485 486 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ 487 if (lvds_output) 488 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; 489 else if (tmds_output) 490 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; 491 else 492 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; 493 494 /* These values seem to vary */ 495 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */ 496 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; 497 498 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); 499 500 /* probably a scratch reg, but kept for cargo-cult purposes: 501 * bit0: crtc0?, head A 502 * bit6: lvds, head A 503 * bit7: (only in X), head A 504 */ 505 if (nv_crtc->index == 0) 506 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; 507 508 /* The blob seems to take the current value from crtc 0, add 4 to that 509 * and reuse the old value for crtc 1 */ 510 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = dev_priv->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY]; 511 if (!nv_crtc->index) 512 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; 513 514 /* the blob sometimes sets |= 0x10 (which is the same as setting |= 515 * 1 << 30 on 0x60.830), for no apparent reason */ 516 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; 517 518 if (dev_priv->card_type >= NV_30) 519 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; 520 521 regp->crtc_830 = mode->crtc_vdisplay - 3; 522 regp->crtc_834 = mode->crtc_vdisplay - 1; 523 524 if (dev_priv->card_type == NV_40) 525 /* This is what the blob does */ 526 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); 527 528 if (dev_priv->card_type >= NV_30) 529 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); 530 531 regp->crtc_cfg = NV_PCRTC_CONFIG_START_ADDRESS_HSYNC; 532 533 /* Some misc regs */ 534 if (dev_priv->card_type == NV_40) { 535 regp->CRTC[NV_CIO_CRE_85] = 0xFF; 536 regp->CRTC[NV_CIO_CRE_86] = 0x1; 537 } 538 539 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->fb->depth + 1) / 8; 540 /* Enable slaved mode (called MODE_TV in nv4ref.h) */ 541 if (lvds_output || tmds_output || tv_output) 542 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); 543 544 /* Generic PRAMDAC regs */ 545 546 if (dev_priv->card_type >= NV_10) 547 /* Only bit that bios and blob set. */ 548 regp->nv10_cursync = (1 << 25); 549 550 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | 551 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | 552 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; 553 if (crtc->fb->depth == 16) 554 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 555 if (dev_priv->chipset >= 0x11) 556 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; 557 558 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ 559 regp->tv_setup = 0; 560 561 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); 562 563 /* Some values the blob sets */ 564 regp->ramdac_8c0 = 0x100; 565 regp->ramdac_a20 = 0x0; 566 regp->ramdac_a24 = 0xfffff; 567 regp->ramdac_a34 = 0x1; 568} 569 570/** 571 * Sets up registers for the given mode/adjusted_mode pair. 572 * 573 * The clocks, CRTCs and outputs attached to this CRTC must be off. 574 * 575 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 576 * be easily turned on/off after this. 577 */ 578static int 579nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 580 struct drm_display_mode *adjusted_mode, 581 int x, int y, struct drm_framebuffer *old_fb) 582{ 583 struct drm_device *dev = crtc->dev; 584 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 585 struct drm_nouveau_private *dev_priv = dev->dev_private; 586 587 NV_DEBUG_KMS(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index); 588 drm_mode_debug_printmodeline(adjusted_mode); 589 590 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ 591 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); 592 593 nv_crtc_mode_set_vga(crtc, adjusted_mode); 594 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ 595 if (dev_priv->card_type == NV_40) 596 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk); 597 nv_crtc_mode_set_regs(crtc, adjusted_mode); 598 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); 599 return 0; 600} 601 602static void nv_crtc_save(struct drm_crtc *crtc) 603{ 604 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 605 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 606 struct nv04_mode_state *state = &dev_priv->mode_reg; 607 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; 608 struct nv04_mode_state *saved = &dev_priv->saved_reg; 609 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; 610 611 if (nv_two_heads(crtc->dev)) 612 NVSetOwner(crtc->dev, nv_crtc->index); 613 614 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); 615 616 /* init some state to saved value */ 617 state->sel_clk = saved->sel_clk & ~(0x5 << 16); 618 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; 619 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK); 620 crtc_state->gpio_ext = crtc_saved->gpio_ext; 621} 622 623static void nv_crtc_restore(struct drm_crtc *crtc) 624{ 625 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 626 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 627 int head = nv_crtc->index; 628 uint8_t saved_cr21 = dev_priv->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; 629 630 if (nv_two_heads(crtc->dev)) 631 NVSetOwner(crtc->dev, head); 632 633 nouveau_hw_load_state(crtc->dev, head, &dev_priv->saved_reg); 634 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); 635 636 nv_crtc->last_dpms = NV_DPMS_CLEARED; 637} 638 639static void nv_crtc_prepare(struct drm_crtc *crtc) 640{ 641 struct drm_device *dev = crtc->dev; 642 struct drm_nouveau_private *dev_priv = dev->dev_private; 643 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 644 struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 645 646 if (nv_two_heads(dev)) 647 NVSetOwner(dev, nv_crtc->index); 648 649 funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 650 651 NVBlankScreen(dev, nv_crtc->index, true); 652 653 /* Some more preperation. */ 654 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); 655 if (dev_priv->card_type == NV_40) { 656 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); 657 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); 658 } 659} 660 661static void nv_crtc_commit(struct drm_crtc *crtc) 662{ 663 struct drm_device *dev = crtc->dev; 664 struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 665 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 666 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 667 668 nouveau_hw_load_state(dev, nv_crtc->index, &dev_priv->mode_reg); 669 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); 670 671#ifdef __BIG_ENDIAN 672 /* turn on LFB swapping */ 673 { 674 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); 675 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG); 676 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); 677 } 678#endif 679 680 funcs->dpms(crtc, DRM_MODE_DPMS_ON); 681} 682 683static void nv_crtc_destroy(struct drm_crtc *crtc) 684{ 685 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 686 687 NV_DEBUG_KMS(crtc->dev, "\n"); 688 689 if (!nv_crtc) 690 return; 691 692 drm_crtc_cleanup(crtc); 693 694 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 695 kfree(nv_crtc); 696} 697 698static void 699nv_crtc_gamma_load(struct drm_crtc *crtc) 700{ 701 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 702 struct drm_device *dev = nv_crtc->base.dev; 703 struct drm_nouveau_private *dev_priv = dev->dev_private; 704 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs; 705 int i; 706 707 rgbs = (struct rgb *)dev_priv->mode_reg.crtc_reg[nv_crtc->index].DAC; 708 for (i = 0; i < 256; i++) { 709 rgbs[i].r = nv_crtc->lut.r[i] >> 8; 710 rgbs[i].g = nv_crtc->lut.g[i] >> 8; 711 rgbs[i].b = nv_crtc->lut.b[i] >> 8; 712 } 713 714 nouveau_hw_load_state_palette(dev, nv_crtc->index, &dev_priv->mode_reg); 715} 716 717static void 718nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start, 719 uint32_t size) 720{ 721 int end = (start + size > 256) ? 256 : start + size, i; 722 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 723 724 for (i = start; i < end; i++) { 725 nv_crtc->lut.r[i] = r[i]; 726 nv_crtc->lut.g[i] = g[i]; 727 nv_crtc->lut.b[i] = b[i]; 728 } 729 730 /* We need to know the depth before we upload, but it's possible to 731 * get called before a framebuffer is bound. If this is the case, 732 * mark the lut values as dirty by setting depth==0, and it'll be 733 * uploaded on the first mode_set_base() 734 */ 735 if (!nv_crtc->base.fb) { 736 nv_crtc->lut.depth = 0; 737 return; 738 } 739 740 nv_crtc_gamma_load(crtc); 741} 742 743static int 744nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 745 struct drm_framebuffer *old_fb) 746{ 747 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 748 struct drm_device *dev = crtc->dev; 749 struct drm_nouveau_private *dev_priv = dev->dev_private; 750 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; 751 struct drm_framebuffer *drm_fb = nv_crtc->base.fb; 752 struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb); 753 int arb_burst, arb_lwm; 754 int ret; 755 756 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM); 757 if (ret) 758 return ret; 759 760 if (old_fb) { 761 struct nouveau_framebuffer *ofb = nouveau_framebuffer(old_fb); 762 nouveau_bo_unpin(ofb->nvbo); 763 } 764 765 nv_crtc->fb.offset = fb->nvbo->bo.offset; 766 767 if (nv_crtc->lut.depth != drm_fb->depth) { 768 nv_crtc->lut.depth = drm_fb->depth; 769 nv_crtc_gamma_load(crtc); 770 } 771 772 /* Update the framebuffer format. */ 773 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; 774 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->fb->depth + 1) / 8; 775 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 776 if (crtc->fb->depth == 16) 777 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 778 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); 779 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, 780 regp->ramdac_gen_ctrl); 781 782 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitch >> 3; 783 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 784 XLATE(drm_fb->pitch >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 785 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); 786 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); 787 788 /* Update the framebuffer location. */ 789 regp->fb_start = nv_crtc->fb.offset & ~3; 790 regp->fb_start += (y * drm_fb->pitch) + (x * drm_fb->bits_per_pixel / 8); 791 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_START, regp->fb_start); 792 793 /* Update the arbitration parameters. */ 794 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel, 795 &arb_burst, &arb_lwm); 796 797 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; 798 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; 799 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); 800 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); 801 802 if (dev_priv->card_type >= NV_30) { 803 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; 804 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); 805 } 806 807 return 0; 808} 809 810static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 811 struct nouveau_bo *dst) 812{ 813 int width = nv_cursor_width(dev); 814 uint32_t pixel; 815 int i, j; 816 817 for (i = 0; i < width; i++) { 818 for (j = 0; j < width; j++) { 819 pixel = nouveau_bo_rd32(src, i*64 + j); 820 821 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16 822 | (pixel & 0xf80000) >> 9 823 | (pixel & 0xf800) >> 6 824 | (pixel & 0xf8) >> 3); 825 } 826 } 827} 828 829static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 830 struct nouveau_bo *dst) 831{ 832 uint32_t pixel; 833 int alpha, i; 834 835 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha 836 * cursors (though NPM in combination with fp dithering may not work on 837 * nv11, from "nv" driver history) 838 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the 839 * blob uses, however we get given PM cursors so we use PM mode 840 */ 841 for (i = 0; i < 64 * 64; i++) { 842 pixel = nouveau_bo_rd32(src, i); 843 844 /* hw gets unhappy if alpha <= rgb values. for a PM image "less 845 * than" shouldn't happen; fix "equal to" case by adding one to 846 * alpha channel (slightly inaccurate, but so is attempting to 847 * get back to NPM images, due to limits of integer precision) 848 */ 849 alpha = pixel >> 24; 850 if (alpha > 0 && alpha < 255) 851 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24); 852 853#ifdef __BIG_ENDIAN 854 { 855 struct drm_nouveau_private *dev_priv = dev->dev_private; 856 857 if (dev_priv->chipset == 0x11) { 858 pixel = ((pixel & 0x000000ff) << 24) | 859 ((pixel & 0x0000ff00) << 8) | 860 ((pixel & 0x00ff0000) >> 8) | 861 ((pixel & 0xff000000) >> 24); 862 } 863 } 864#endif 865 866 nouveau_bo_wr32(dst, i, pixel); 867 } 868} 869 870static int 871nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 872 uint32_t buffer_handle, uint32_t width, uint32_t height) 873{ 874 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 875 struct drm_device *dev = dev_priv->dev; 876 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 877 struct nouveau_bo *cursor = NULL; 878 struct drm_gem_object *gem; 879 int ret = 0; 880 881 if (width != 64 || height != 64) 882 return -EINVAL; 883 884 if (!buffer_handle) { 885 nv_crtc->cursor.hide(nv_crtc, true); 886 return 0; 887 } 888 889 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); 890 if (!gem) 891 return -ENOENT; 892 cursor = nouveau_gem_object(gem); 893 894 ret = nouveau_bo_map(cursor); 895 if (ret) 896 goto out; 897 898 if (dev_priv->chipset >= 0x11) 899 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 900 else 901 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 902 903 nouveau_bo_unmap(cursor); 904 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset; 905 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 906 nv_crtc->cursor.show(nv_crtc, true); 907out: 908 drm_gem_object_unreference_unlocked(gem); 909 return ret; 910} 911 912static int 913nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 914{ 915 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 916 917 nv_crtc->cursor.set_pos(nv_crtc, x, y); 918 return 0; 919} 920 921static const struct drm_crtc_funcs nv04_crtc_funcs = { 922 .save = nv_crtc_save, 923 .restore = nv_crtc_restore, 924 .cursor_set = nv04_crtc_cursor_set, 925 .cursor_move = nv04_crtc_cursor_move, 926 .gamma_set = nv_crtc_gamma_set, 927 .set_config = drm_crtc_helper_set_config, 928 .destroy = nv_crtc_destroy, 929}; 930 931static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { 932 .dpms = nv_crtc_dpms, 933 .prepare = nv_crtc_prepare, 934 .commit = nv_crtc_commit, 935 .mode_fixup = nv_crtc_mode_fixup, 936 .mode_set = nv_crtc_mode_set, 937 .mode_set_base = nv04_crtc_mode_set_base, 938 .load_lut = nv_crtc_gamma_load, 939}; 940 941int 942nv04_crtc_create(struct drm_device *dev, int crtc_num) 943{ 944 struct nouveau_crtc *nv_crtc; 945 int ret, i; 946 947 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); 948 if (!nv_crtc) 949 return -ENOMEM; 950 951 for (i = 0; i < 256; i++) { 952 nv_crtc->lut.r[i] = i << 8; 953 nv_crtc->lut.g[i] = i << 8; 954 nv_crtc->lut.b[i] = i << 8; 955 } 956 nv_crtc->lut.depth = 0; 957 958 nv_crtc->index = crtc_num; 959 nv_crtc->last_dpms = NV_DPMS_CLEARED; 960 961 drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs); 962 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); 963 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); 964 965 ret = nouveau_bo_new(dev, NULL, 64*64*4, 0x100, TTM_PL_FLAG_VRAM, 966 0, 0x0000, false, true, &nv_crtc->cursor.nvbo); 967 if (!ret) { 968 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); 969 if (!ret) 970 ret = nouveau_bo_map(nv_crtc->cursor.nvbo); 971 if (ret) 972 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 973 } 974 975 nv04_cursor_init(nv_crtc); 976 977 return 0; 978} 979