1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3/* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30#ifndef _I915_DRV_H_ 31#define _I915_DRV_H_ 32 33#include "i915_reg.h" 34#include "intel_bios.h" 35#include "intel_ringbuffer.h" 36#include <linux/io-mapping.h> 37 38/* General customization: 39 */ 40 41#define DRIVER_AUTHOR "Tungsten Graphics, Inc." 42 43#define DRIVER_NAME "i915" 44#define DRIVER_DESC "Intel Graphics" 45#define DRIVER_DATE "20080730" 46 47enum pipe { 48 PIPE_A = 0, 49 PIPE_B, 50}; 51 52enum plane { 53 PLANE_A = 0, 54 PLANE_B, 55}; 56 57#define I915_NUM_PIPE 2 58 59#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 60 61/* Interface history: 62 * 63 * 1.1: Original. 64 * 1.2: Add Power Management 65 * 1.3: Add vblank support 66 * 1.4: Fix cmdbuffer path, add heap destroy 67 * 1.5: Add vblank pipe configuration 68 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 69 * - Support vertical blank on secondary display pipe 70 */ 71#define DRIVER_MAJOR 1 72#define DRIVER_MINOR 6 73#define DRIVER_PATCHLEVEL 0 74 75#define WATCH_COHERENCY 0 76#define WATCH_BUF 0 77#define WATCH_EXEC 0 78#define WATCH_LRU 0 79#define WATCH_RELOC 0 80#define WATCH_INACTIVE 0 81#define WATCH_PWRITE 0 82 83#define I915_GEM_PHYS_CURSOR_0 1 84#define I915_GEM_PHYS_CURSOR_1 2 85#define I915_GEM_PHYS_OVERLAY_REGS 3 86#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 87 88struct drm_i915_gem_phys_object { 89 int id; 90 struct page **page_list; 91 drm_dma_handle_t *handle; 92 struct drm_gem_object *cur_obj; 93}; 94 95struct mem_block { 96 struct mem_block *next; 97 struct mem_block *prev; 98 int start; 99 int size; 100 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 101}; 102 103struct opregion_header; 104struct opregion_acpi; 105struct opregion_swsci; 106struct opregion_asle; 107 108struct intel_opregion { 109 struct opregion_header *header; 110 struct opregion_acpi *acpi; 111 struct opregion_swsci *swsci; 112 struct opregion_asle *asle; 113 int enabled; 114}; 115 116struct intel_overlay; 117struct intel_overlay_error_state; 118 119struct drm_i915_master_private { 120 drm_local_map_t *sarea; 121 struct _drm_i915_sarea *sarea_priv; 122}; 123#define I915_FENCE_REG_NONE -1 124 125struct drm_i915_fence_reg { 126 struct drm_gem_object *obj; 127 struct list_head lru_list; 128}; 129 130struct sdvo_device_mapping { 131 u8 dvo_port; 132 u8 slave_addr; 133 u8 dvo_wiring; 134 u8 initialized; 135 u8 ddc_pin; 136}; 137 138struct drm_i915_error_state { 139 u32 eir; 140 u32 pgtbl_er; 141 u32 pipeastat; 142 u32 pipebstat; 143 u32 ipeir; 144 u32 ipehr; 145 u32 instdone; 146 u32 acthd; 147 u32 instpm; 148 u32 instps; 149 u32 instdone1; 150 u32 seqno; 151 u64 bbaddr; 152 struct timeval time; 153 struct drm_i915_error_object { 154 int page_count; 155 u32 gtt_offset; 156 u32 *pages[0]; 157 } *ringbuffer, *batchbuffer[2]; 158 struct drm_i915_error_buffer { 159 size_t size; 160 u32 name; 161 u32 seqno; 162 u32 gtt_offset; 163 u32 read_domains; 164 u32 write_domain; 165 u32 fence_reg; 166 s32 pinned:2; 167 u32 tiling:2; 168 u32 dirty:1; 169 u32 purgeable:1; 170 } *active_bo; 171 u32 active_bo_count; 172 struct intel_overlay_error_state *overlay; 173}; 174 175struct drm_i915_display_funcs { 176 void (*dpms)(struct drm_crtc *crtc, int mode); 177 bool (*fbc_enabled)(struct drm_device *dev); 178 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 179 void (*disable_fbc)(struct drm_device *dev); 180 int (*get_display_clock_speed)(struct drm_device *dev); 181 int (*get_fifo_size)(struct drm_device *dev, int plane); 182 void (*update_wm)(struct drm_device *dev, int planea_clock, 183 int planeb_clock, int sr_hdisplay, int sr_htotal, 184 int pixel_size); 185 /* clock updates for mode set */ 186 /* cursor updates */ 187 /* render clock increase/decrease */ 188 /* display clock increase/decrease */ 189 /* pll clock increase/decrease */ 190 /* clock gating init */ 191}; 192 193struct intel_device_info { 194 u8 gen; 195 u8 is_mobile : 1; 196 u8 is_i8xx : 1; 197 u8 is_i85x : 1; 198 u8 is_i915g : 1; 199 u8 is_i9xx : 1; 200 u8 is_i945gm : 1; 201 u8 is_i965g : 1; 202 u8 is_i965gm : 1; 203 u8 is_g33 : 1; 204 u8 need_gfx_hws : 1; 205 u8 is_g4x : 1; 206 u8 is_pineview : 1; 207 u8 is_broadwater : 1; 208 u8 is_crestline : 1; 209 u8 is_ironlake : 1; 210 u8 has_fbc : 1; 211 u8 has_rc6 : 1; 212 u8 has_pipe_cxsr : 1; 213 u8 has_hotplug : 1; 214 u8 cursor_needs_physical : 1; 215}; 216 217enum no_fbc_reason { 218 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 219 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 220 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 221 FBC_BAD_PLANE, /* fbc not supported on plane */ 222 FBC_NOT_TILED, /* buffer not tiled */ 223 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 224}; 225 226enum intel_pch { 227 PCH_IBX, /* Ibexpeak PCH */ 228 PCH_CPT, /* Cougarpoint PCH */ 229}; 230 231#define QUIRK_PIPEA_FORCE (1<<0) 232 233struct intel_fbdev; 234 235typedef struct drm_i915_private { 236 struct drm_device *dev; 237 238 const struct intel_device_info *info; 239 240 int has_gem; 241 242 void __iomem *regs; 243 244 struct pci_dev *bridge_dev; 245 struct intel_ring_buffer render_ring; 246 struct intel_ring_buffer bsd_ring; 247 uint32_t next_seqno; 248 249 drm_dma_handle_t *status_page_dmah; 250 void *seqno_page; 251 dma_addr_t dma_status_page; 252 uint32_t counter; 253 unsigned int seqno_gfx_addr; 254 drm_local_map_t hws_map; 255 struct drm_gem_object *seqno_obj; 256 struct drm_gem_object *pwrctx; 257 struct drm_gem_object *renderctx; 258 259 struct resource mch_res; 260 261 unsigned int cpp; 262 int back_offset; 263 int front_offset; 264 int current_page; 265 int page_flipping; 266 267 wait_queue_head_t irq_queue; 268 atomic_t irq_received; 269 /** Protects user_irq_refcount and irq_mask_reg */ 270 spinlock_t user_irq_lock; 271 u32 trace_irq_seqno; 272 /** Cached value of IMR to avoid reads in updating the bitfield */ 273 u32 irq_mask_reg; 274 u32 pipestat[2]; 275 /** splitted irq regs for graphics and display engine on Ironlake, 276 irq_mask_reg is still used for display irq. */ 277 u32 gt_irq_mask_reg; 278 u32 gt_irq_enable_reg; 279 u32 de_irq_enable_reg; 280 u32 pch_irq_mask_reg; 281 u32 pch_irq_enable_reg; 282 283 u32 hotplug_supported_mask; 284 struct work_struct hotplug_work; 285 286 int tex_lru_log_granularity; 287 int allow_batchbuffer; 288 struct mem_block *agp_heap; 289 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 290 int vblank_pipe; 291 int num_pipe; 292 u32 flush_rings; 293#define FLUSH_RENDER_RING 0x1 294#define FLUSH_BSD_RING 0x2 295 296 /* For hangcheck timer */ 297#define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */ 298 struct timer_list hangcheck_timer; 299 int hangcheck_count; 300 uint32_t last_acthd; 301 uint32_t last_instdone; 302 uint32_t last_instdone1; 303 304 struct drm_mm vram; 305 306 unsigned long cfb_size; 307 unsigned long cfb_pitch; 308 int cfb_fence; 309 int cfb_plane; 310 311 int irq_enabled; 312 313 struct intel_opregion opregion; 314 315 /* overlay */ 316 struct intel_overlay *overlay; 317 318 /* LVDS info */ 319 int backlight_duty_cycle; /* restore backlight to this value */ 320 bool panel_wants_dither; 321 struct drm_display_mode *panel_fixed_mode; 322 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 323 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 324 325 /* Feature bits from the VBIOS */ 326 unsigned int int_tv_support:1; 327 unsigned int lvds_dither:1; 328 unsigned int lvds_vbt:1; 329 unsigned int int_crt_support:1; 330 unsigned int lvds_use_ssc:1; 331 unsigned int edp_support:1; 332 int lvds_ssc_freq; 333 int edp_bpp; 334 335 struct notifier_block lid_notifier; 336 337 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */ 338 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ 339 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 340 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 341 342 unsigned int fsb_freq, mem_freq, is_ddr3; 343 344 spinlock_t error_lock; 345 struct drm_i915_error_state *first_error; 346 struct work_struct error_work; 347 struct workqueue_struct *wq; 348 349 /* Display functions */ 350 struct drm_i915_display_funcs display; 351 352 /* PCH chipset type */ 353 enum intel_pch pch_type; 354 355 unsigned long quirks; 356 357 /* Register state */ 358 bool modeset_on_lid; 359 u8 saveLBB; 360 u32 saveDSPACNTR; 361 u32 saveDSPBCNTR; 362 u32 saveDSPARB; 363 u32 saveHWS; 364 u32 savePIPEACONF; 365 u32 savePIPEBCONF; 366 u32 savePIPEASRC; 367 u32 savePIPEBSRC; 368 u32 saveFPA0; 369 u32 saveFPA1; 370 u32 saveDPLL_A; 371 u32 saveDPLL_A_MD; 372 u32 saveHTOTAL_A; 373 u32 saveHBLANK_A; 374 u32 saveHSYNC_A; 375 u32 saveVTOTAL_A; 376 u32 saveVBLANK_A; 377 u32 saveVSYNC_A; 378 u32 saveBCLRPAT_A; 379 u32 saveTRANSACONF; 380 u32 saveTRANS_HTOTAL_A; 381 u32 saveTRANS_HBLANK_A; 382 u32 saveTRANS_HSYNC_A; 383 u32 saveTRANS_VTOTAL_A; 384 u32 saveTRANS_VBLANK_A; 385 u32 saveTRANS_VSYNC_A; 386 u32 savePIPEASTAT; 387 u32 saveDSPASTRIDE; 388 u32 saveDSPASIZE; 389 u32 saveDSPAPOS; 390 u32 saveDSPAADDR; 391 u32 saveDSPASURF; 392 u32 saveDSPATILEOFF; 393 u32 savePFIT_PGM_RATIOS; 394 u32 saveBLC_HIST_CTL; 395 u32 saveBLC_PWM_CTL; 396 u32 saveBLC_PWM_CTL2; 397 u32 saveBLC_CPU_PWM_CTL; 398 u32 saveBLC_CPU_PWM_CTL2; 399 u32 saveFPB0; 400 u32 saveFPB1; 401 u32 saveDPLL_B; 402 u32 saveDPLL_B_MD; 403 u32 saveHTOTAL_B; 404 u32 saveHBLANK_B; 405 u32 saveHSYNC_B; 406 u32 saveVTOTAL_B; 407 u32 saveVBLANK_B; 408 u32 saveVSYNC_B; 409 u32 saveBCLRPAT_B; 410 u32 saveTRANSBCONF; 411 u32 saveTRANS_HTOTAL_B; 412 u32 saveTRANS_HBLANK_B; 413 u32 saveTRANS_HSYNC_B; 414 u32 saveTRANS_VTOTAL_B; 415 u32 saveTRANS_VBLANK_B; 416 u32 saveTRANS_VSYNC_B; 417 u32 savePIPEBSTAT; 418 u32 saveDSPBSTRIDE; 419 u32 saveDSPBSIZE; 420 u32 saveDSPBPOS; 421 u32 saveDSPBADDR; 422 u32 saveDSPBSURF; 423 u32 saveDSPBTILEOFF; 424 u32 saveVGA0; 425 u32 saveVGA1; 426 u32 saveVGA_PD; 427 u32 saveVGACNTRL; 428 u32 saveADPA; 429 u32 saveLVDS; 430 u32 savePP_ON_DELAYS; 431 u32 savePP_OFF_DELAYS; 432 u32 saveDVOA; 433 u32 saveDVOB; 434 u32 saveDVOC; 435 u32 savePP_ON; 436 u32 savePP_OFF; 437 u32 savePP_CONTROL; 438 u32 savePP_DIVISOR; 439 u32 savePFIT_CONTROL; 440 u32 save_palette_a[256]; 441 u32 save_palette_b[256]; 442 u32 saveDPFC_CB_BASE; 443 u32 saveFBC_CFB_BASE; 444 u32 saveFBC_LL_BASE; 445 u32 saveFBC_CONTROL; 446 u32 saveFBC_CONTROL2; 447 u32 saveIER; 448 u32 saveIIR; 449 u32 saveIMR; 450 u32 saveDEIER; 451 u32 saveDEIMR; 452 u32 saveGTIER; 453 u32 saveGTIMR; 454 u32 saveFDI_RXA_IMR; 455 u32 saveFDI_RXB_IMR; 456 u32 saveCACHE_MODE_0; 457 u32 saveMI_ARB_STATE; 458 u32 saveSWF0[16]; 459 u32 saveSWF1[16]; 460 u32 saveSWF2[3]; 461 u8 saveMSR; 462 u8 saveSR[8]; 463 u8 saveGR[25]; 464 u8 saveAR_INDEX; 465 u8 saveAR[21]; 466 u8 saveDACMASK; 467 u8 saveCR[37]; 468 uint64_t saveFENCE[16]; 469 u32 saveCURACNTR; 470 u32 saveCURAPOS; 471 u32 saveCURABASE; 472 u32 saveCURBCNTR; 473 u32 saveCURBPOS; 474 u32 saveCURBBASE; 475 u32 saveCURSIZE; 476 u32 saveDP_B; 477 u32 saveDP_C; 478 u32 saveDP_D; 479 u32 savePIPEA_GMCH_DATA_M; 480 u32 savePIPEB_GMCH_DATA_M; 481 u32 savePIPEA_GMCH_DATA_N; 482 u32 savePIPEB_GMCH_DATA_N; 483 u32 savePIPEA_DP_LINK_M; 484 u32 savePIPEB_DP_LINK_M; 485 u32 savePIPEA_DP_LINK_N; 486 u32 savePIPEB_DP_LINK_N; 487 u32 saveFDI_RXA_CTL; 488 u32 saveFDI_TXA_CTL; 489 u32 saveFDI_RXB_CTL; 490 u32 saveFDI_TXB_CTL; 491 u32 savePFA_CTL_1; 492 u32 savePFB_CTL_1; 493 u32 savePFA_WIN_SZ; 494 u32 savePFB_WIN_SZ; 495 u32 savePFA_WIN_POS; 496 u32 savePFB_WIN_POS; 497 u32 savePCH_DREF_CONTROL; 498 u32 saveDISP_ARB_CTL; 499 u32 savePIPEA_DATA_M1; 500 u32 savePIPEA_DATA_N1; 501 u32 savePIPEA_LINK_M1; 502 u32 savePIPEA_LINK_N1; 503 u32 savePIPEB_DATA_M1; 504 u32 savePIPEB_DATA_N1; 505 u32 savePIPEB_LINK_M1; 506 u32 savePIPEB_LINK_N1; 507 u32 saveMCHBAR_RENDER_STANDBY; 508 509 struct { 510 struct drm_mm gtt_space; 511 512 struct io_mapping *gtt_mapping; 513 int gtt_mtrr; 514 515 /** 516 * Membership on list of all loaded devices, used to evict 517 * inactive buffers under memory pressure. 518 * 519 * Modifications should only be done whilst holding the 520 * shrink_list_lock spinlock. 521 */ 522 struct list_head shrink_list; 523 524 spinlock_t active_list_lock; 525 526 /** 527 * List of objects which are not in the ringbuffer but which 528 * still have a write_domain which needs to be flushed before 529 * unbinding. 530 * 531 * last_rendering_seqno is 0 while an object is in this list. 532 * 533 * A reference is held on the buffer while on this list. 534 */ 535 struct list_head flushing_list; 536 537 /** 538 * List of objects currently pending a GPU write flush. 539 * 540 * All elements on this list will belong to either the 541 * active_list or flushing_list, last_rendering_seqno can 542 * be used to differentiate between the two elements. 543 */ 544 struct list_head gpu_write_list; 545 546 /** 547 * LRU list of objects which are not in the ringbuffer and 548 * are ready to unbind, but are still in the GTT. 549 * 550 * last_rendering_seqno is 0 while an object is in this list. 551 * 552 * A reference is not held on the buffer while on this list, 553 * as merely being GTT-bound shouldn't prevent its being 554 * freed, and we'll pull it off the list in the free path. 555 */ 556 struct list_head inactive_list; 557 558 /** LRU list of objects with fence regs on them. */ 559 struct list_head fence_list; 560 561 /** 562 * List of objects currently pending being freed. 563 * 564 * These objects are no longer in use, but due to a signal 565 * we were prevented from freeing them at the appointed time. 566 */ 567 struct list_head deferred_free_list; 568 569 /** 570 * We leave the user IRQ off as much as possible, 571 * but this means that requests will finish and never 572 * be retired once the system goes idle. Set a timer to 573 * fire periodically while the ring is running. When it 574 * fires, go retire requests. 575 */ 576 struct delayed_work retire_work; 577 578 /** 579 * Waiting sequence number, if any 580 */ 581 uint32_t waiting_gem_seqno; 582 583 /** 584 * Last seq seen at irq time 585 */ 586 uint32_t irq_gem_seqno; 587 588 /** 589 * Flag if the X Server, and thus DRM, is not currently in 590 * control of the device. 591 * 592 * This is set between LeaveVT and EnterVT. It needs to be 593 * replaced with a semaphore. It also needs to be 594 * transitioned away from for kernel modesetting. 595 */ 596 int suspended; 597 598 /** 599 * Flag if the hardware appears to be wedged. 600 * 601 * This is set when attempts to idle the device timeout. 602 * It prevents command submission from occuring and makes 603 * every pending request fail 604 */ 605 atomic_t wedged; 606 607 /** Bit 6 swizzling required for X tiling */ 608 uint32_t bit_6_swizzle_x; 609 /** Bit 6 swizzling required for Y tiling */ 610 uint32_t bit_6_swizzle_y; 611 612 /* storage for physical objects */ 613 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 614 } mm; 615 struct sdvo_device_mapping sdvo_mappings[2]; 616 /* indicate whether the LVDS_BORDER should be enabled or not */ 617 unsigned int lvds_border_bits; 618 /* Panel fitter placement and size for Ironlake+ */ 619 u32 pch_pf_pos, pch_pf_size; 620 621 struct drm_crtc *plane_to_crtc_mapping[2]; 622 struct drm_crtc *pipe_to_crtc_mapping[2]; 623 wait_queue_head_t pending_flip_queue; 624 bool flip_pending_is_done; 625 626 /* Reclocking support */ 627 bool render_reclock_avail; 628 bool lvds_downclock_avail; 629 /* indicate whether the LVDS EDID is OK */ 630 bool lvds_edid_good; 631 /* indicates the reduced downclock for LVDS*/ 632 int lvds_downclock; 633 struct work_struct idle_work; 634 struct timer_list idle_timer; 635 bool busy; 636 u16 orig_clock; 637 int child_dev_num; 638 struct child_device_config *child_dev; 639 struct drm_connector *int_lvds_connector; 640 641 bool mchbar_need_disable; 642 643 u8 cur_delay; 644 u8 min_delay; 645 u8 max_delay; 646 u8 fmax; 647 u8 fstart; 648 649 u64 last_count1; 650 unsigned long last_time1; 651 u64 last_count2; 652 struct timespec last_time2; 653 unsigned long gfx_power; 654 int c_m; 655 int r_t; 656 u8 corr; 657 spinlock_t *mchdev_lock; 658 659 enum no_fbc_reason no_fbc_reason; 660 661 struct drm_mm_node *compressed_fb; 662 struct drm_mm_node *compressed_llb; 663 664 /* list of fbdev register on this device */ 665 struct intel_fbdev *fbdev; 666} drm_i915_private_t; 667 668/** driver private structure attached to each drm_gem_object */ 669struct drm_i915_gem_object { 670 struct drm_gem_object base; 671 672 /** Current space allocated to this object in the GTT, if any. */ 673 struct drm_mm_node *gtt_space; 674 675 /** This object's place on the active/flushing/inactive lists */ 676 struct list_head list; 677 /** This object's place on GPU write list */ 678 struct list_head gpu_write_list; 679 /** This object's place on eviction list */ 680 struct list_head evict_list; 681 682 /** 683 * This is set if the object is on the active or flushing lists 684 * (has pending rendering), and is not set if it's on inactive (ready 685 * to be unbound). 686 */ 687 unsigned int active : 1; 688 689 /** 690 * This is set if the object has been written to since last bound 691 * to the GTT 692 */ 693 unsigned int dirty : 1; 694 695 /** 696 * Fence register bits (if any) for this object. Will be set 697 * as needed when mapped into the GTT. 698 * Protected by dev->struct_mutex. 699 * 700 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE) 701 */ 702 signed int fence_reg : 5; 703 704 /** 705 * Used for checking the object doesn't appear more than once 706 * in an execbuffer object list. 707 */ 708 unsigned int in_execbuffer : 1; 709 710 /** 711 * Advice: are the backing pages purgeable? 712 */ 713 unsigned int madv : 2; 714 715 /** 716 * Refcount for the pages array. With the current locking scheme, there 717 * are at most two concurrent users: Binding a bo to the gtt and 718 * pwrite/pread using physical addresses. So two bits for a maximum 719 * of two users are enough. 720 */ 721 unsigned int pages_refcount : 2; 722#define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3 723 724 /** 725 * Current tiling mode for the object. 726 */ 727 unsigned int tiling_mode : 2; 728 729 /** How many users have pinned this object in GTT space. The following 730 * users can each hold at most one reference: pwrite/pread, pin_ioctl 731 * (via user_pin_count), execbuffer (objects are not allowed multiple 732 * times for the same batchbuffer), and the framebuffer code. When 733 * switching/pageflipping, the framebuffer code has at most two buffers 734 * pinned per crtc. 735 * 736 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 737 * bits with absolutely no headroom. So use 4 bits. */ 738 unsigned int pin_count : 4; 739#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 740 741 /** AGP memory structure for our GTT binding. */ 742 DRM_AGP_MEM *agp_mem; 743 744 struct page **pages; 745 746 /** 747 * Current offset of the object in GTT space. 748 * 749 * This is the same as gtt_space->start 750 */ 751 uint32_t gtt_offset; 752 753 /* Which ring is refering to is this object */ 754 struct intel_ring_buffer *ring; 755 756 /** 757 * Fake offset for use by mmap(2) 758 */ 759 uint64_t mmap_offset; 760 761 /** Breadcrumb of last rendering to the buffer. */ 762 uint32_t last_rendering_seqno; 763 764 /** Current tiling stride for the object, if it's tiled. */ 765 uint32_t stride; 766 767 /** Record of address bit 17 of each page at last unbind. */ 768 unsigned long *bit_17; 769 770 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ 771 uint32_t agp_type; 772 773 /** 774 * If present, while GEM_DOMAIN_CPU is in the read domain this array 775 * flags which individual pages are valid. 776 */ 777 uint8_t *page_cpu_valid; 778 779 /** User space pin count and filp owning the pin */ 780 uint32_t user_pin_count; 781 struct drm_file *pin_filp; 782 783 /** for phy allocated objects */ 784 struct drm_i915_gem_phys_object *phys_obj; 785 786 /** 787 * Number of crtcs where this object is currently the fb, but 788 * will be page flipped away on the next vblank. When it 789 * reaches 0, dev_priv->pending_flip_queue will be woken up. 790 */ 791 atomic_t pending_flip; 792}; 793 794#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 795 796/** 797 * Request queue structure. 798 * 799 * The request queue allows us to note sequence numbers that have been emitted 800 * and may be associated with active buffers to be retired. 801 * 802 * By keeping this list, we can avoid having to do questionable 803 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 804 * an emission time with seqnos for tracking how far ahead of the GPU we are. 805 */ 806struct drm_i915_gem_request { 807 /** On Which ring this request was generated */ 808 struct intel_ring_buffer *ring; 809 810 /** GEM sequence number associated with this request. */ 811 uint32_t seqno; 812 813 /** Time at which this request was emitted, in jiffies. */ 814 unsigned long emitted_jiffies; 815 816 /** global list entry for this request */ 817 struct list_head list; 818 819 /** file_priv list entry for this request */ 820 struct list_head client_list; 821}; 822 823struct drm_i915_file_private { 824 struct { 825 struct list_head request_list; 826 } mm; 827}; 828 829enum intel_chip_family { 830 CHIP_I8XX = 0x01, 831 CHIP_I9XX = 0x02, 832 CHIP_I915 = 0x04, 833 CHIP_I965 = 0x08, 834}; 835 836extern struct drm_ioctl_desc i915_ioctls[]; 837extern int i915_max_ioctl; 838extern unsigned int i915_fbpercrtc; 839extern unsigned int i915_powersave; 840extern unsigned int i915_lvds_downclock; 841 842extern int i915_suspend(struct drm_device *dev, pm_message_t state); 843extern int i915_resume(struct drm_device *dev); 844extern void i915_save_display(struct drm_device *dev); 845extern void i915_restore_display(struct drm_device *dev); 846extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 847extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 848 849 /* i915_dma.c */ 850extern void i915_kernel_lost_context(struct drm_device * dev); 851extern int i915_driver_load(struct drm_device *, unsigned long flags); 852extern int i915_driver_unload(struct drm_device *); 853extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 854extern void i915_driver_lastclose(struct drm_device * dev); 855extern void i915_driver_preclose(struct drm_device *dev, 856 struct drm_file *file_priv); 857extern void i915_driver_postclose(struct drm_device *dev, 858 struct drm_file *file_priv); 859extern int i915_driver_device_is_agp(struct drm_device * dev); 860extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 861 unsigned long arg); 862extern int i915_emit_box(struct drm_device *dev, 863 struct drm_clip_rect *boxes, 864 int i, int DR1, int DR4); 865extern int i965_reset(struct drm_device *dev, u8 flags); 866extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 867extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 868extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 869extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 870 871 872/* i915_irq.c */ 873void i915_hangcheck_elapsed(unsigned long data); 874void i915_destroy_error_state(struct drm_device *dev); 875extern int i915_irq_emit(struct drm_device *dev, void *data, 876 struct drm_file *file_priv); 877extern int i915_irq_wait(struct drm_device *dev, void *data, 878 struct drm_file *file_priv); 879void i915_trace_irq_get(struct drm_device *dev, u32 seqno); 880extern void i915_enable_interrupt (struct drm_device *dev); 881 882extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 883extern void i915_driver_irq_preinstall(struct drm_device * dev); 884extern int i915_driver_irq_postinstall(struct drm_device *dev); 885extern void i915_driver_irq_uninstall(struct drm_device * dev); 886extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 887 struct drm_file *file_priv); 888extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 889 struct drm_file *file_priv); 890extern int i915_enable_vblank(struct drm_device *dev, int crtc); 891extern void i915_disable_vblank(struct drm_device *dev, int crtc); 892extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 893extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); 894extern int i915_vblank_swap(struct drm_device *dev, void *data, 895 struct drm_file *file_priv); 896extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); 897extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask); 898extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, 899 u32 mask); 900extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, 901 u32 mask); 902 903void 904i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 905 906void 907i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 908 909void intel_enable_asle (struct drm_device *dev); 910 911 912/* i915_mem.c */ 913extern int i915_mem_alloc(struct drm_device *dev, void *data, 914 struct drm_file *file_priv); 915extern int i915_mem_free(struct drm_device *dev, void *data, 916 struct drm_file *file_priv); 917extern int i915_mem_init_heap(struct drm_device *dev, void *data, 918 struct drm_file *file_priv); 919extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, 920 struct drm_file *file_priv); 921extern void i915_mem_takedown(struct mem_block **heap); 922extern void i915_mem_release(struct drm_device * dev, 923 struct drm_file *file_priv, struct mem_block *heap); 924/* i915_gem.c */ 925int i915_gem_init_ioctl(struct drm_device *dev, void *data, 926 struct drm_file *file_priv); 927int i915_gem_create_ioctl(struct drm_device *dev, void *data, 928 struct drm_file *file_priv); 929int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 930 struct drm_file *file_priv); 931int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 932 struct drm_file *file_priv); 933int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 934 struct drm_file *file_priv); 935int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 936 struct drm_file *file_priv); 937int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 938 struct drm_file *file_priv); 939int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 940 struct drm_file *file_priv); 941int i915_gem_execbuffer(struct drm_device *dev, void *data, 942 struct drm_file *file_priv); 943int i915_gem_execbuffer2(struct drm_device *dev, void *data, 944 struct drm_file *file_priv); 945int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 946 struct drm_file *file_priv); 947int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 948 struct drm_file *file_priv); 949int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 950 struct drm_file *file_priv); 951int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 952 struct drm_file *file_priv); 953int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 954 struct drm_file *file_priv); 955int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 956 struct drm_file *file_priv); 957int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 958 struct drm_file *file_priv); 959int i915_gem_set_tiling(struct drm_device *dev, void *data, 960 struct drm_file *file_priv); 961int i915_gem_get_tiling(struct drm_device *dev, void *data, 962 struct drm_file *file_priv); 963int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 964 struct drm_file *file_priv); 965void i915_gem_load(struct drm_device *dev); 966int i915_gem_init_object(struct drm_gem_object *obj); 967struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, 968 size_t size); 969void i915_gem_free_object(struct drm_gem_object *obj); 970int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); 971void i915_gem_object_unpin(struct drm_gem_object *obj); 972int i915_gem_object_unbind(struct drm_gem_object *obj); 973void i915_gem_release_mmap(struct drm_gem_object *obj); 974void i915_gem_lastclose(struct drm_device *dev); 975uint32_t i915_get_gem_seqno(struct drm_device *dev, 976 struct intel_ring_buffer *ring); 977bool i915_seqno_passed(uint32_t seq1, uint32_t seq2); 978int i915_gem_object_get_fence_reg(struct drm_gem_object *obj); 979int i915_gem_object_put_fence_reg(struct drm_gem_object *obj); 980void i915_gem_retire_requests(struct drm_device *dev); 981void i915_gem_retire_work_handler(struct work_struct *work); 982void i915_gem_clflush_object(struct drm_gem_object *obj); 983int i915_gem_object_set_domain(struct drm_gem_object *obj, 984 uint32_t read_domains, 985 uint32_t write_domain); 986int i915_gem_init_ringbuffer(struct drm_device *dev); 987void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 988int i915_gem_do_init(struct drm_device *dev, unsigned long start, 989 unsigned long end); 990int i915_gpu_idle(struct drm_device *dev); 991int i915_gem_idle(struct drm_device *dev); 992uint32_t i915_add_request(struct drm_device *dev, 993 struct drm_file *file_priv, 994 uint32_t flush_domains, 995 struct intel_ring_buffer *ring); 996int i915_do_wait_request(struct drm_device *dev, 997 uint32_t seqno, int interruptible, 998 struct intel_ring_buffer *ring); 999int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 1000int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, 1001 int write); 1002int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj); 1003int i915_gem_attach_phys_object(struct drm_device *dev, 1004 struct drm_gem_object *obj, 1005 int id, 1006 int align); 1007void i915_gem_detach_phys_object(struct drm_device *dev, 1008 struct drm_gem_object *obj); 1009void i915_gem_free_all_phys_object(struct drm_device *dev); 1010int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask); 1011void i915_gem_object_put_pages(struct drm_gem_object *obj); 1012void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); 1013int i915_gem_object_flush_write_domain(struct drm_gem_object *obj); 1014 1015void i915_gem_shrinker_init(void); 1016void i915_gem_shrinker_exit(void); 1017 1018/* i915_gem_evict.c */ 1019int i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignment); 1020int i915_gem_evict_everything(struct drm_device *dev); 1021int i915_gem_evict_inactive(struct drm_device *dev); 1022 1023/* i915_gem_tiling.c */ 1024void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1025void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); 1026void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); 1027bool i915_tiling_ok(struct drm_device *dev, int stride, int size, 1028 int tiling_mode); 1029bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, 1030 int tiling_mode); 1031 1032/* i915_gem_debug.c */ 1033void i915_gem_dump_object(struct drm_gem_object *obj, int len, 1034 const char *where, uint32_t mark); 1035#if WATCH_INACTIVE 1036void i915_verify_inactive(struct drm_device *dev, char *file, int line); 1037#else 1038#define i915_verify_inactive(dev, file, line) 1039#endif 1040void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); 1041void i915_gem_dump_object(struct drm_gem_object *obj, int len, 1042 const char *where, uint32_t mark); 1043void i915_dump_lru(struct drm_device *dev, const char *where); 1044 1045/* i915_debugfs.c */ 1046int i915_debugfs_init(struct drm_minor *minor); 1047void i915_debugfs_cleanup(struct drm_minor *minor); 1048 1049/* i915_suspend.c */ 1050extern int i915_save_state(struct drm_device *dev); 1051extern int i915_restore_state(struct drm_device *dev); 1052 1053/* i915_suspend.c */ 1054extern int i915_save_state(struct drm_device *dev); 1055extern int i915_restore_state(struct drm_device *dev); 1056 1057#ifdef CONFIG_ACPI 1058/* i915_opregion.c */ 1059extern int intel_opregion_init(struct drm_device *dev, int resume); 1060extern void intel_opregion_free(struct drm_device *dev, int suspend); 1061extern void opregion_asle_intr(struct drm_device *dev); 1062extern void ironlake_opregion_gse_intr(struct drm_device *dev); 1063extern void opregion_enable_asle(struct drm_device *dev); 1064#else 1065static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; } 1066static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; } 1067static inline void opregion_asle_intr(struct drm_device *dev) { return; } 1068static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; } 1069static inline void opregion_enable_asle(struct drm_device *dev) { return; } 1070#endif 1071 1072/* modesetting */ 1073extern void intel_modeset_init(struct drm_device *dev); 1074extern void intel_modeset_cleanup(struct drm_device *dev); 1075extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1076extern void i8xx_disable_fbc(struct drm_device *dev); 1077extern void g4x_disable_fbc(struct drm_device *dev); 1078extern void ironlake_disable_fbc(struct drm_device *dev); 1079extern void intel_disable_fbc(struct drm_device *dev); 1080extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); 1081extern bool intel_fbc_enabled(struct drm_device *dev); 1082extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1083extern void intel_detect_pch (struct drm_device *dev); 1084extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); 1085 1086/* overlay */ 1087extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 1088extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); 1089 1090/** 1091 * Lock test for when it's just for synchronization of ring access. 1092 * 1093 * In that case, we don't need to do it when GEM is initialized as nobody else 1094 * has access to the ring. 1095 */ 1096#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ 1097 if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \ 1098 == NULL) \ 1099 LOCK_TEST_WITH_RETURN(dev, file_priv); \ 1100} while (0) 1101 1102#define I915_READ(reg) readl(dev_priv->regs + (reg)) 1103#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg)) 1104#define I915_READ16(reg) readw(dev_priv->regs + (reg)) 1105#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) 1106#define I915_READ8(reg) readb(dev_priv->regs + (reg)) 1107#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg)) 1108#define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg)) 1109#define I915_READ64(reg) readq(dev_priv->regs + (reg)) 1110#define POSTING_READ(reg) (void)I915_READ(reg) 1111#define POSTING_READ16(reg) (void)I915_READ16(reg) 1112 1113#define I915_VERBOSE 0 1114 1115#define BEGIN_LP_RING(n) do { \ 1116 drm_i915_private_t *dev_priv__ = dev->dev_private; \ 1117 if (I915_VERBOSE) \ 1118 DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \ 1119 intel_ring_begin(dev, &dev_priv__->render_ring, (n)); \ 1120} while (0) 1121 1122 1123#define OUT_RING(x) do { \ 1124 drm_i915_private_t *dev_priv__ = dev->dev_private; \ 1125 if (I915_VERBOSE) \ 1126 DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \ 1127 intel_ring_emit(dev, &dev_priv__->render_ring, x); \ 1128} while (0) 1129 1130#define ADVANCE_LP_RING() do { \ 1131 drm_i915_private_t *dev_priv__ = dev->dev_private; \ 1132 if (I915_VERBOSE) \ 1133 DRM_DEBUG("ADVANCE_LP_RING %x\n", \ 1134 dev_priv__->render_ring.tail); \ 1135 intel_ring_advance(dev, &dev_priv__->render_ring); \ 1136} while(0) 1137 1138/** 1139 * Reads a dword out of the status page, which is written to from the command 1140 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 1141 * MI_STORE_DATA_IMM. 1142 * 1143 * The following dwords have a reserved meaning: 1144 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 1145 * 0x04: ring 0 head pointer 1146 * 0x05: ring 1 head pointer (915-class) 1147 * 0x06: ring 2 head pointer (915-class) 1148 * 0x10-0x1b: Context status DWords (GM45) 1149 * 0x1f: Last written status offset. (GM45) 1150 * 1151 * The area from dword 0x20 to 0x3ff is available for driver usage. 1152 */ 1153#define READ_HWSP(dev_priv, reg) (((volatile u32 *)\ 1154 (dev_priv->render_ring.status_page.page_addr))[reg]) 1155#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 1156#define I915_GEM_HWS_INDEX 0x20 1157#define I915_BREADCRUMB_INDEX 0x21 1158 1159#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1160 1161#define IS_I830(dev) ((dev)->pci_device == 0x3577) 1162#define IS_845G(dev) ((dev)->pci_device == 0x2562) 1163#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1164#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1165#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1166#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1167#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1168#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1169#define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g) 1170#define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm) 1171#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1172#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1173#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1174#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1175#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1176#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1177#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1178#define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1179#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1180#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1181#define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake) 1182#define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx) 1183#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1184 1185#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1186#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1187#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1188#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1189#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1190 1191#define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev)) 1192#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1193 1194/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1195 * rows, which changed the alignment requirements and fence programming. 1196 */ 1197#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ 1198 IS_I915GM(dev))) 1199#define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev)) 1200#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1201#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1202#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1203#define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \ 1204 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \ 1205 !IS_GEN6(dev)) 1206#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1207/* dsparb controlled by hw only */ 1208#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1209 1210#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev)) 1211#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1212#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1213#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) 1214 1215#define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \ 1216 IS_GEN6(dev)) 1217#define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev)) 1218 1219#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1220#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1221 1222#define PRIMARY_RINGBUFFER_SIZE (128*1024) 1223 1224#endif 1225