1/* 2 * driver/dma/coh901318.c 3 * 4 * Copyright (C) 2007-2009 ST-Ericsson 5 * License terms: GNU General Public License (GPL) version 2 6 * DMA driver for COH 901 318 7 * Author: Per Friden <per.friden@stericsson.com> 8 */ 9 10#include <linux/init.h> 11#include <linux/module.h> 12#include <linux/kernel.h> /* printk() */ 13#include <linux/fs.h> /* everything... */ 14#include <linux/slab.h> /* kmalloc() */ 15#include <linux/dmaengine.h> 16#include <linux/platform_device.h> 17#include <linux/device.h> 18#include <linux/irqreturn.h> 19#include <linux/interrupt.h> 20#include <linux/io.h> 21#include <linux/uaccess.h> 22#include <linux/debugfs.h> 23#include <mach/coh901318.h> 24 25#include "coh901318_lli.h" 26 27#define COHC_2_DEV(cohc) (&cohc->chan.dev->device) 28 29#ifdef VERBOSE_DEBUG 30#define COH_DBG(x) ({ if (1) x; 0; }) 31#else 32#define COH_DBG(x) ({ if (0) x; 0; }) 33#endif 34 35struct coh901318_desc { 36 struct dma_async_tx_descriptor desc; 37 struct list_head node; 38 struct scatterlist *sg; 39 unsigned int sg_len; 40 struct coh901318_lli *lli; 41 enum dma_data_direction dir; 42 unsigned long flags; 43}; 44 45struct coh901318_base { 46 struct device *dev; 47 void __iomem *virtbase; 48 struct coh901318_pool pool; 49 struct powersave pm; 50 struct dma_device dma_slave; 51 struct dma_device dma_memcpy; 52 struct coh901318_chan *chans; 53 struct coh901318_platform *platform; 54}; 55 56struct coh901318_chan { 57 spinlock_t lock; 58 int allocated; 59 int completed; 60 int id; 61 int stopped; 62 63 struct work_struct free_work; 64 struct dma_chan chan; 65 66 struct tasklet_struct tasklet; 67 68 struct list_head active; 69 struct list_head queue; 70 struct list_head free; 71 72 unsigned long nbr_active_done; 73 unsigned long busy; 74 75 u32 runtime_addr; 76 u32 runtime_ctrl; 77 78 struct coh901318_base *base; 79}; 80 81static void coh901318_list_print(struct coh901318_chan *cohc, 82 struct coh901318_lli *lli) 83{ 84 struct coh901318_lli *l = lli; 85 int i = 0; 86 87 while (l) { 88 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x" 89 ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n", 90 i, l, l->control, l->src_addr, l->dst_addr, 91 l->link_addr, l->virt_link_addr); 92 i++; 93 l = l->virt_link_addr; 94 } 95} 96 97#ifdef CONFIG_DEBUG_FS 98 99#define COH901318_DEBUGFS_ASSIGN(x, y) (x = y) 100 101static struct coh901318_base *debugfs_dma_base; 102static struct dentry *dma_dentry; 103 104static int coh901318_debugfs_open(struct inode *inode, struct file *file) 105{ 106 107 file->private_data = inode->i_private; 108 return 0; 109} 110 111static int coh901318_debugfs_read(struct file *file, char __user *buf, 112 size_t count, loff_t *f_pos) 113{ 114 u64 started_channels = debugfs_dma_base->pm.started_channels; 115 int pool_count = debugfs_dma_base->pool.debugfs_pool_counter; 116 int i; 117 int ret = 0; 118 char *dev_buf; 119 char *tmp; 120 int dev_size; 121 122 dev_buf = kmalloc(4*1024, GFP_KERNEL); 123 if (dev_buf == NULL) 124 goto err_kmalloc; 125 tmp = dev_buf; 126 127 tmp += sprintf(tmp, "DMA -- enabled dma channels\n"); 128 129 for (i = 0; i < debugfs_dma_base->platform->max_channels; i++) 130 if (started_channels & (1 << i)) 131 tmp += sprintf(tmp, "channel %d\n", i); 132 133 tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count); 134 dev_size = tmp - dev_buf; 135 136 /* No more to read if offset != 0 */ 137 if (*f_pos > dev_size) 138 goto out; 139 140 if (count > dev_size - *f_pos) 141 count = dev_size - *f_pos; 142 143 if (copy_to_user(buf, dev_buf + *f_pos, count)) 144 ret = -EINVAL; 145 ret = count; 146 *f_pos += count; 147 148 out: 149 kfree(dev_buf); 150 return ret; 151 152 err_kmalloc: 153 return 0; 154} 155 156static const struct file_operations coh901318_debugfs_status_operations = { 157 .owner = THIS_MODULE, 158 .open = coh901318_debugfs_open, 159 .read = coh901318_debugfs_read, 160}; 161 162 163static int __init init_coh901318_debugfs(void) 164{ 165 166 dma_dentry = debugfs_create_dir("dma", NULL); 167 168 (void) debugfs_create_file("status", 169 S_IFREG | S_IRUGO, 170 dma_dentry, NULL, 171 &coh901318_debugfs_status_operations); 172 return 0; 173} 174 175static void __exit exit_coh901318_debugfs(void) 176{ 177 debugfs_remove_recursive(dma_dentry); 178} 179 180module_init(init_coh901318_debugfs); 181module_exit(exit_coh901318_debugfs); 182#else 183 184#define COH901318_DEBUGFS_ASSIGN(x, y) 185 186#endif /* CONFIG_DEBUG_FS */ 187 188static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan) 189{ 190 return container_of(chan, struct coh901318_chan, chan); 191} 192 193static inline dma_addr_t 194cohc_dev_addr(struct coh901318_chan *cohc) 195{ 196 /* Runtime supplied address will take precedence */ 197 if (cohc->runtime_addr) 198 return cohc->runtime_addr; 199 return cohc->base->platform->chan_conf[cohc->id].dev_addr; 200} 201 202static inline const struct coh901318_params * 203cohc_chan_param(struct coh901318_chan *cohc) 204{ 205 return &cohc->base->platform->chan_conf[cohc->id].param; 206} 207 208static inline const struct coh_dma_channel * 209cohc_chan_conf(struct coh901318_chan *cohc) 210{ 211 return &cohc->base->platform->chan_conf[cohc->id]; 212} 213 214static void enable_powersave(struct coh901318_chan *cohc) 215{ 216 unsigned long flags; 217 struct powersave *pm = &cohc->base->pm; 218 219 spin_lock_irqsave(&pm->lock, flags); 220 221 pm->started_channels &= ~(1ULL << cohc->id); 222 223 if (!pm->started_channels) { 224 /* DMA no longer intends to access memory */ 225 cohc->base->platform->access_memory_state(cohc->base->dev, 226 false); 227 } 228 229 spin_unlock_irqrestore(&pm->lock, flags); 230} 231static void disable_powersave(struct coh901318_chan *cohc) 232{ 233 unsigned long flags; 234 struct powersave *pm = &cohc->base->pm; 235 236 spin_lock_irqsave(&pm->lock, flags); 237 238 if (!pm->started_channels) { 239 /* DMA intends to access memory */ 240 cohc->base->platform->access_memory_state(cohc->base->dev, 241 true); 242 } 243 244 pm->started_channels |= (1ULL << cohc->id); 245 246 spin_unlock_irqrestore(&pm->lock, flags); 247} 248 249static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control) 250{ 251 int channel = cohc->id; 252 void __iomem *virtbase = cohc->base->virtbase; 253 254 writel(control, 255 virtbase + COH901318_CX_CTRL + 256 COH901318_CX_CTRL_SPACING * channel); 257 return 0; 258} 259 260static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf) 261{ 262 int channel = cohc->id; 263 void __iomem *virtbase = cohc->base->virtbase; 264 265 writel(conf, 266 virtbase + COH901318_CX_CFG + 267 COH901318_CX_CFG_SPACING*channel); 268 return 0; 269} 270 271 272static int coh901318_start(struct coh901318_chan *cohc) 273{ 274 u32 val; 275 int channel = cohc->id; 276 void __iomem *virtbase = cohc->base->virtbase; 277 278 disable_powersave(cohc); 279 280 val = readl(virtbase + COH901318_CX_CFG + 281 COH901318_CX_CFG_SPACING * channel); 282 283 /* Enable channel */ 284 val |= COH901318_CX_CFG_CH_ENABLE; 285 writel(val, virtbase + COH901318_CX_CFG + 286 COH901318_CX_CFG_SPACING * channel); 287 288 return 0; 289} 290 291static int coh901318_prep_linked_list(struct coh901318_chan *cohc, 292 struct coh901318_lli *lli) 293{ 294 int channel = cohc->id; 295 void __iomem *virtbase = cohc->base->virtbase; 296 297 BUG_ON(readl(virtbase + COH901318_CX_STAT + 298 COH901318_CX_STAT_SPACING*channel) & 299 COH901318_CX_STAT_ACTIVE); 300 301 writel(lli->src_addr, 302 virtbase + COH901318_CX_SRC_ADDR + 303 COH901318_CX_SRC_ADDR_SPACING * channel); 304 305 writel(lli->dst_addr, virtbase + 306 COH901318_CX_DST_ADDR + 307 COH901318_CX_DST_ADDR_SPACING * channel); 308 309 writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR + 310 COH901318_CX_LNK_ADDR_SPACING * channel); 311 312 writel(lli->control, virtbase + COH901318_CX_CTRL + 313 COH901318_CX_CTRL_SPACING * channel); 314 315 return 0; 316} 317static dma_cookie_t 318coh901318_assign_cookie(struct coh901318_chan *cohc, 319 struct coh901318_desc *cohd) 320{ 321 dma_cookie_t cookie = cohc->chan.cookie; 322 323 if (++cookie < 0) 324 cookie = 1; 325 326 cohc->chan.cookie = cookie; 327 cohd->desc.cookie = cookie; 328 329 return cookie; 330} 331 332static struct coh901318_desc * 333coh901318_desc_get(struct coh901318_chan *cohc) 334{ 335 struct coh901318_desc *desc; 336 337 if (list_empty(&cohc->free)) { 338 /* alloc new desc because we're out of used ones 339 * TODO: alloc a pile of descs instead of just one, 340 * avoid many small allocations. 341 */ 342 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT); 343 if (desc == NULL) 344 goto out; 345 INIT_LIST_HEAD(&desc->node); 346 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan); 347 } else { 348 /* Reuse an old desc. */ 349 desc = list_first_entry(&cohc->free, 350 struct coh901318_desc, 351 node); 352 list_del(&desc->node); 353 /* Initialize it a bit so it's not insane */ 354 desc->sg = NULL; 355 desc->sg_len = 0; 356 desc->desc.callback = NULL; 357 desc->desc.callback_param = NULL; 358 } 359 360 out: 361 return desc; 362} 363 364static void 365coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd) 366{ 367 list_add_tail(&cohd->node, &cohc->free); 368} 369 370/* call with irq lock held */ 371static void 372coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc) 373{ 374 list_add_tail(&desc->node, &cohc->active); 375} 376 377static struct coh901318_desc * 378coh901318_first_active_get(struct coh901318_chan *cohc) 379{ 380 struct coh901318_desc *d; 381 382 if (list_empty(&cohc->active)) 383 return NULL; 384 385 d = list_first_entry(&cohc->active, 386 struct coh901318_desc, 387 node); 388 return d; 389} 390 391static void 392coh901318_desc_remove(struct coh901318_desc *cohd) 393{ 394 list_del(&cohd->node); 395} 396 397static void 398coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc) 399{ 400 list_add_tail(&desc->node, &cohc->queue); 401} 402 403static struct coh901318_desc * 404coh901318_first_queued(struct coh901318_chan *cohc) 405{ 406 struct coh901318_desc *d; 407 408 if (list_empty(&cohc->queue)) 409 return NULL; 410 411 d = list_first_entry(&cohc->queue, 412 struct coh901318_desc, 413 node); 414 return d; 415} 416 417static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli) 418{ 419 struct coh901318_lli *lli = in_lli; 420 u32 bytes = 0; 421 422 while (lli) { 423 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK; 424 lli = lli->virt_link_addr; 425 } 426 return bytes; 427} 428 429/* 430 * Get the number of bytes left to transfer on this channel, 431 * it is unwise to call this before stopping the channel for 432 * absolute measures, but for a rough guess you can still call 433 * it. 434 */ 435static u32 coh901318_get_bytes_left(struct dma_chan *chan) 436{ 437 struct coh901318_chan *cohc = to_coh901318_chan(chan); 438 struct coh901318_desc *cohd; 439 struct list_head *pos; 440 unsigned long flags; 441 u32 left = 0; 442 int i = 0; 443 444 spin_lock_irqsave(&cohc->lock, flags); 445 446 /* 447 * If there are many queued jobs, we iterate and add the 448 * size of them all. We take a special look on the first 449 * job though, since it is probably active. 450 */ 451 list_for_each(pos, &cohc->active) { 452 /* 453 * The first job in the list will be working on the 454 * hardware. The job can be stopped but still active, 455 * so that the transfer counter is somewhere inside 456 * the buffer. 457 */ 458 cohd = list_entry(pos, struct coh901318_desc, node); 459 460 if (i == 0) { 461 struct coh901318_lli *lli; 462 dma_addr_t ladd; 463 464 /* Read current transfer count value */ 465 left = readl(cohc->base->virtbase + 466 COH901318_CX_CTRL + 467 COH901318_CX_CTRL_SPACING * cohc->id) & 468 COH901318_CX_CTRL_TC_VALUE_MASK; 469 470 /* See if the transfer is linked... */ 471 ladd = readl(cohc->base->virtbase + 472 COH901318_CX_LNK_ADDR + 473 COH901318_CX_LNK_ADDR_SPACING * 474 cohc->id) & 475 ~COH901318_CX_LNK_LINK_IMMEDIATE; 476 /* Single transaction */ 477 if (!ladd) 478 continue; 479 480 /* 481 * Linked transaction, follow the lli, find the 482 * currently processing lli, and proceed to the next 483 */ 484 lli = cohd->lli; 485 while (lli && lli->link_addr != ladd) 486 lli = lli->virt_link_addr; 487 488 if (lli) 489 lli = lli->virt_link_addr; 490 491 /* 492 * Follow remaining lli links around to count the total 493 * number of bytes left 494 */ 495 left += coh901318_get_bytes_in_lli(lli); 496 } else { 497 left += coh901318_get_bytes_in_lli(cohd->lli); 498 } 499 i++; 500 } 501 502 /* Also count bytes in the queued jobs */ 503 list_for_each(pos, &cohc->queue) { 504 cohd = list_entry(pos, struct coh901318_desc, node); 505 left += coh901318_get_bytes_in_lli(cohd->lli); 506 } 507 508 spin_unlock_irqrestore(&cohc->lock, flags); 509 510 return left; 511} 512 513/* 514 * Pauses a transfer without losing data. Enables power save. 515 * Use this function in conjunction with coh901318_resume. 516 */ 517static void coh901318_pause(struct dma_chan *chan) 518{ 519 u32 val; 520 unsigned long flags; 521 struct coh901318_chan *cohc = to_coh901318_chan(chan); 522 int channel = cohc->id; 523 void __iomem *virtbase = cohc->base->virtbase; 524 525 spin_lock_irqsave(&cohc->lock, flags); 526 527 /* Disable channel in HW */ 528 val = readl(virtbase + COH901318_CX_CFG + 529 COH901318_CX_CFG_SPACING * channel); 530 531 /* Stopping infinit transfer */ 532 if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 && 533 (val & COH901318_CX_CFG_CH_ENABLE)) 534 cohc->stopped = 1; 535 536 537 val &= ~COH901318_CX_CFG_CH_ENABLE; 538 writel(val, virtbase + COH901318_CX_CFG + 539 COH901318_CX_CFG_SPACING * channel); 540 writel(val, virtbase + COH901318_CX_CFG + 541 COH901318_CX_CFG_SPACING * channel); 542 543 /* Spin-wait for it to actually go inactive */ 544 while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING * 545 channel) & COH901318_CX_STAT_ACTIVE) 546 cpu_relax(); 547 548 /* Check if we stopped an active job */ 549 if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING * 550 channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0) 551 cohc->stopped = 1; 552 553 enable_powersave(cohc); 554 555 spin_unlock_irqrestore(&cohc->lock, flags); 556} 557 558/* Resumes a transfer that has been stopped via 300_dma_stop(..). 559 Power save is handled. 560*/ 561static void coh901318_resume(struct dma_chan *chan) 562{ 563 u32 val; 564 unsigned long flags; 565 struct coh901318_chan *cohc = to_coh901318_chan(chan); 566 int channel = cohc->id; 567 568 spin_lock_irqsave(&cohc->lock, flags); 569 570 disable_powersave(cohc); 571 572 if (cohc->stopped) { 573 /* Enable channel in HW */ 574 val = readl(cohc->base->virtbase + COH901318_CX_CFG + 575 COH901318_CX_CFG_SPACING * channel); 576 577 val |= COH901318_CX_CFG_CH_ENABLE; 578 579 writel(val, cohc->base->virtbase + COH901318_CX_CFG + 580 COH901318_CX_CFG_SPACING*channel); 581 582 cohc->stopped = 0; 583 } 584 585 spin_unlock_irqrestore(&cohc->lock, flags); 586} 587 588bool coh901318_filter_id(struct dma_chan *chan, void *chan_id) 589{ 590 unsigned int ch_nr = (unsigned int) chan_id; 591 592 if (ch_nr == to_coh901318_chan(chan)->id) 593 return true; 594 595 return false; 596} 597EXPORT_SYMBOL(coh901318_filter_id); 598 599/* 600 * DMA channel allocation 601 */ 602static int coh901318_config(struct coh901318_chan *cohc, 603 struct coh901318_params *param) 604{ 605 unsigned long flags; 606 const struct coh901318_params *p; 607 int channel = cohc->id; 608 void __iomem *virtbase = cohc->base->virtbase; 609 610 spin_lock_irqsave(&cohc->lock, flags); 611 612 if (param) 613 p = param; 614 else 615 p = &cohc->base->platform->chan_conf[channel].param; 616 617 /* Clear any pending BE or TC interrupt */ 618 if (channel < 32) { 619 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1); 620 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1); 621 } else { 622 writel(1 << (channel - 32), virtbase + 623 COH901318_BE_INT_CLEAR2); 624 writel(1 << (channel - 32), virtbase + 625 COH901318_TC_INT_CLEAR2); 626 } 627 628 coh901318_set_conf(cohc, p->config); 629 coh901318_set_ctrl(cohc, p->ctrl_lli_last); 630 631 spin_unlock_irqrestore(&cohc->lock, flags); 632 633 return 0; 634} 635 636/* must lock when calling this function 637 * start queued jobs, if any 638 * TODO: start all queued jobs in one go 639 * 640 * Returns descriptor if queued job is started otherwise NULL. 641 * If the queue is empty NULL is returned. 642 */ 643static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc) 644{ 645 struct coh901318_desc *cohd; 646 647 /* 648 * start queued jobs, if any 649 * TODO: transmit all queued jobs in one go 650 */ 651 cohd = coh901318_first_queued(cohc); 652 653 if (cohd != NULL) { 654 /* Remove from queue */ 655 coh901318_desc_remove(cohd); 656 /* initiate DMA job */ 657 cohc->busy = 1; 658 659 coh901318_desc_submit(cohc, cohd); 660 661 coh901318_prep_linked_list(cohc, cohd->lli); 662 663 /* start dma job on this channel */ 664 coh901318_start(cohc); 665 666 } 667 668 return cohd; 669} 670 671/* 672 * This tasklet is called from the interrupt handler to 673 * handle each descriptor (DMA job) that is sent to a channel. 674 */ 675static void dma_tasklet(unsigned long data) 676{ 677 struct coh901318_chan *cohc = (struct coh901318_chan *) data; 678 struct coh901318_desc *cohd_fin; 679 unsigned long flags; 680 dma_async_tx_callback callback; 681 void *callback_param; 682 683 dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d" 684 " nbr_active_done %ld\n", __func__, 685 cohc->id, cohc->nbr_active_done); 686 687 spin_lock_irqsave(&cohc->lock, flags); 688 689 /* get first active descriptor entry from list */ 690 cohd_fin = coh901318_first_active_get(cohc); 691 692 if (cohd_fin == NULL) 693 goto err; 694 695 /* locate callback to client */ 696 callback = cohd_fin->desc.callback; 697 callback_param = cohd_fin->desc.callback_param; 698 699 /* sign this job as completed on the channel */ 700 cohc->completed = cohd_fin->desc.cookie; 701 702 /* release the lli allocation and remove the descriptor */ 703 coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli); 704 705 /* return desc to free-list */ 706 coh901318_desc_remove(cohd_fin); 707 coh901318_desc_free(cohc, cohd_fin); 708 709 spin_unlock_irqrestore(&cohc->lock, flags); 710 711 /* Call the callback when we're done */ 712 if (callback) 713 callback(callback_param); 714 715 spin_lock_irqsave(&cohc->lock, flags); 716 717 /* 718 * If another interrupt fired while the tasklet was scheduling, 719 * we don't get called twice, so we have this number of active 720 * counter that keep track of the number of IRQs expected to 721 * be handled for this channel. If there happen to be more than 722 * one IRQ to be ack:ed, we simply schedule this tasklet again. 723 */ 724 cohc->nbr_active_done--; 725 if (cohc->nbr_active_done) { 726 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs " 727 "came in while we were scheduling this tasklet\n"); 728 if (cohc_chan_conf(cohc)->priority_high) 729 tasklet_hi_schedule(&cohc->tasklet); 730 else 731 tasklet_schedule(&cohc->tasklet); 732 } 733 734 spin_unlock_irqrestore(&cohc->lock, flags); 735 736 return; 737 738 err: 739 spin_unlock_irqrestore(&cohc->lock, flags); 740 dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__); 741} 742 743 744/* called from interrupt context */ 745static void dma_tc_handle(struct coh901318_chan *cohc) 746{ 747 /* 748 * If the channel is not allocated, then we shouldn't have 749 * any TC interrupts on it. 750 */ 751 if (!cohc->allocated) { 752 dev_err(COHC_2_DEV(cohc), "spurious interrupt from " 753 "unallocated channel\n"); 754 return; 755 } 756 757 spin_lock(&cohc->lock); 758 759 /* 760 * When we reach this point, at least one queue item 761 * should have been moved over from cohc->queue to 762 * cohc->active and run to completion, that is why we're 763 * getting a terminal count interrupt is it not? 764 * If you get this BUG() the most probable cause is that 765 * the individual nodes in the lli chain have IRQ enabled, 766 * so check your platform config for lli chain ctrl. 767 */ 768 BUG_ON(list_empty(&cohc->active)); 769 770 cohc->nbr_active_done++; 771 772 /* 773 * This attempt to take a job from cohc->queue, put it 774 * into cohc->active and start it. 775 */ 776 if (coh901318_queue_start(cohc) == NULL) 777 cohc->busy = 0; 778 779 spin_unlock(&cohc->lock); 780 781 /* 782 * This tasklet will remove items from cohc->active 783 * and thus terminates them. 784 */ 785 if (cohc_chan_conf(cohc)->priority_high) 786 tasklet_hi_schedule(&cohc->tasklet); 787 else 788 tasklet_schedule(&cohc->tasklet); 789} 790 791 792static irqreturn_t dma_irq_handler(int irq, void *dev_id) 793{ 794 u32 status1; 795 u32 status2; 796 int i; 797 int ch; 798 struct coh901318_base *base = dev_id; 799 struct coh901318_chan *cohc; 800 void __iomem *virtbase = base->virtbase; 801 802 status1 = readl(virtbase + COH901318_INT_STATUS1); 803 status2 = readl(virtbase + COH901318_INT_STATUS2); 804 805 if (unlikely(status1 == 0 && status2 == 0)) { 806 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n"); 807 return IRQ_HANDLED; 808 } 809 810 /* TODO: consider handle IRQ in tasklet here to 811 * minimize interrupt latency */ 812 813 /* Check the first 32 DMA channels for IRQ */ 814 while (status1) { 815 /* Find first bit set, return as a number. */ 816 i = ffs(status1) - 1; 817 ch = i; 818 819 cohc = &base->chans[ch]; 820 spin_lock(&cohc->lock); 821 822 /* Mask off this bit */ 823 status1 &= ~(1 << i); 824 /* Check the individual channel bits */ 825 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) { 826 dev_crit(COHC_2_DEV(cohc), 827 "DMA bus error on channel %d!\n", ch); 828 BUG_ON(1); 829 /* Clear BE interrupt */ 830 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1); 831 } else { 832 /* Caused by TC, really? */ 833 if (unlikely(!test_bit(i, virtbase + 834 COH901318_TC_INT_STATUS1))) { 835 dev_warn(COHC_2_DEV(cohc), 836 "ignoring interrupt not caused by terminal count on channel %d\n", ch); 837 /* Clear TC interrupt */ 838 BUG_ON(1); 839 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1); 840 } else { 841 /* Enable powersave if transfer has finished */ 842 if (!(readl(virtbase + COH901318_CX_STAT + 843 COH901318_CX_STAT_SPACING*ch) & 844 COH901318_CX_STAT_ENABLED)) { 845 enable_powersave(cohc); 846 } 847 848 /* Must clear TC interrupt before calling 849 * dma_tc_handle 850 * in case tc_handle initate a new dma job 851 */ 852 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1); 853 854 dma_tc_handle(cohc); 855 } 856 } 857 spin_unlock(&cohc->lock); 858 } 859 860 /* Check the remaining 32 DMA channels for IRQ */ 861 while (status2) { 862 /* Find first bit set, return as a number. */ 863 i = ffs(status2) - 1; 864 ch = i + 32; 865 cohc = &base->chans[ch]; 866 spin_lock(&cohc->lock); 867 868 /* Mask off this bit */ 869 status2 &= ~(1 << i); 870 /* Check the individual channel bits */ 871 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) { 872 dev_crit(COHC_2_DEV(cohc), 873 "DMA bus error on channel %d!\n", ch); 874 /* Clear BE interrupt */ 875 BUG_ON(1); 876 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2); 877 } else { 878 /* Caused by TC, really? */ 879 if (unlikely(!test_bit(i, virtbase + 880 COH901318_TC_INT_STATUS2))) { 881 dev_warn(COHC_2_DEV(cohc), 882 "ignoring interrupt not caused by terminal count on channel %d\n", ch); 883 /* Clear TC interrupt */ 884 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2); 885 BUG_ON(1); 886 } else { 887 /* Enable powersave if transfer has finished */ 888 if (!(readl(virtbase + COH901318_CX_STAT + 889 COH901318_CX_STAT_SPACING*ch) & 890 COH901318_CX_STAT_ENABLED)) { 891 enable_powersave(cohc); 892 } 893 /* Must clear TC interrupt before calling 894 * dma_tc_handle 895 * in case tc_handle initate a new dma job 896 */ 897 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2); 898 899 dma_tc_handle(cohc); 900 } 901 } 902 spin_unlock(&cohc->lock); 903 } 904 905 return IRQ_HANDLED; 906} 907 908static int coh901318_alloc_chan_resources(struct dma_chan *chan) 909{ 910 struct coh901318_chan *cohc = to_coh901318_chan(chan); 911 unsigned long flags; 912 913 dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n", 914 __func__, cohc->id); 915 916 if (chan->client_count > 1) 917 return -EBUSY; 918 919 spin_lock_irqsave(&cohc->lock, flags); 920 921 coh901318_config(cohc, NULL); 922 923 cohc->allocated = 1; 924 cohc->completed = chan->cookie = 1; 925 926 spin_unlock_irqrestore(&cohc->lock, flags); 927 928 return 1; 929} 930 931static void 932coh901318_free_chan_resources(struct dma_chan *chan) 933{ 934 struct coh901318_chan *cohc = to_coh901318_chan(chan); 935 int channel = cohc->id; 936 unsigned long flags; 937 938 spin_lock_irqsave(&cohc->lock, flags); 939 940 /* Disable HW */ 941 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG + 942 COH901318_CX_CFG_SPACING*channel); 943 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL + 944 COH901318_CX_CTRL_SPACING*channel); 945 946 cohc->allocated = 0; 947 948 spin_unlock_irqrestore(&cohc->lock, flags); 949 950 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); 951} 952 953 954static dma_cookie_t 955coh901318_tx_submit(struct dma_async_tx_descriptor *tx) 956{ 957 struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc, 958 desc); 959 struct coh901318_chan *cohc = to_coh901318_chan(tx->chan); 960 unsigned long flags; 961 962 spin_lock_irqsave(&cohc->lock, flags); 963 964 tx->cookie = coh901318_assign_cookie(cohc, cohd); 965 966 coh901318_desc_queue(cohc, cohd); 967 968 spin_unlock_irqrestore(&cohc->lock, flags); 969 970 return tx->cookie; 971} 972 973static struct dma_async_tx_descriptor * 974coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 975 size_t size, unsigned long flags) 976{ 977 struct coh901318_lli *lli; 978 struct coh901318_desc *cohd; 979 unsigned long flg; 980 struct coh901318_chan *cohc = to_coh901318_chan(chan); 981 int lli_len; 982 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last; 983 int ret; 984 985 spin_lock_irqsave(&cohc->lock, flg); 986 987 dev_vdbg(COHC_2_DEV(cohc), 988 "[%s] channel %d src 0x%x dest 0x%x size %d\n", 989 __func__, cohc->id, src, dest, size); 990 991 if (flags & DMA_PREP_INTERRUPT) 992 /* Trigger interrupt after last lli */ 993 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE; 994 995 lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT; 996 if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size) 997 lli_len++; 998 999 lli = coh901318_lli_alloc(&cohc->base->pool, lli_len); 1000 1001 if (lli == NULL) 1002 goto err; 1003 1004 ret = coh901318_lli_fill_memcpy( 1005 &cohc->base->pool, lli, src, size, dest, 1006 cohc_chan_param(cohc)->ctrl_lli_chained, 1007 ctrl_last); 1008 if (ret) 1009 goto err; 1010 1011 COH_DBG(coh901318_list_print(cohc, lli)); 1012 1013 /* Pick a descriptor to handle this transfer */ 1014 cohd = coh901318_desc_get(cohc); 1015 cohd->lli = lli; 1016 cohd->flags = flags; 1017 cohd->desc.tx_submit = coh901318_tx_submit; 1018 1019 spin_unlock_irqrestore(&cohc->lock, flg); 1020 1021 return &cohd->desc; 1022 err: 1023 spin_unlock_irqrestore(&cohc->lock, flg); 1024 return NULL; 1025} 1026 1027static struct dma_async_tx_descriptor * 1028coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 1029 unsigned int sg_len, enum dma_data_direction direction, 1030 unsigned long flags) 1031{ 1032 struct coh901318_chan *cohc = to_coh901318_chan(chan); 1033 struct coh901318_lli *lli; 1034 struct coh901318_desc *cohd; 1035 const struct coh901318_params *params; 1036 struct scatterlist *sg; 1037 int len = 0; 1038 int size; 1039 int i; 1040 u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained; 1041 u32 ctrl = cohc_chan_param(cohc)->ctrl_lli; 1042 u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last; 1043 u32 config; 1044 unsigned long flg; 1045 int ret; 1046 1047 if (!sgl) 1048 goto out; 1049 if (sgl->length == 0) 1050 goto out; 1051 1052 spin_lock_irqsave(&cohc->lock, flg); 1053 1054 dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n", 1055 __func__, sg_len, direction); 1056 1057 if (flags & DMA_PREP_INTERRUPT) 1058 /* Trigger interrupt after last lli */ 1059 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE; 1060 1061 params = cohc_chan_param(cohc); 1062 config = params->config; 1063 /* 1064 * Add runtime-specific control on top, make 1065 * sure the bits you set per peripheral channel are 1066 * cleared in the default config from the platform. 1067 */ 1068 ctrl_chained |= cohc->runtime_ctrl; 1069 ctrl_last |= cohc->runtime_ctrl; 1070 ctrl |= cohc->runtime_ctrl; 1071 1072 if (direction == DMA_TO_DEVICE) { 1073 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE | 1074 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE; 1075 1076 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY; 1077 ctrl_chained |= tx_flags; 1078 ctrl_last |= tx_flags; 1079 ctrl |= tx_flags; 1080 } else if (direction == DMA_FROM_DEVICE) { 1081 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST | 1082 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE; 1083 1084 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY; 1085 ctrl_chained |= rx_flags; 1086 ctrl_last |= rx_flags; 1087 ctrl |= rx_flags; 1088 } else 1089 goto err_direction; 1090 1091 coh901318_set_conf(cohc, config); 1092 1093 /* The dma only supports transmitting packages up to 1094 * MAX_DMA_PACKET_SIZE. Calculate to total number of 1095 * dma elemts required to send the entire sg list 1096 */ 1097 for_each_sg(sgl, sg, sg_len, i) { 1098 unsigned int factor; 1099 size = sg_dma_len(sg); 1100 1101 if (size <= MAX_DMA_PACKET_SIZE) { 1102 len++; 1103 continue; 1104 } 1105 1106 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT; 1107 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size) 1108 factor++; 1109 1110 len += factor; 1111 } 1112 1113 pr_debug("Allocate %d lli:s for this transfer\n", len); 1114 lli = coh901318_lli_alloc(&cohc->base->pool, len); 1115 1116 if (lli == NULL) 1117 goto err_dma_alloc; 1118 1119 /* initiate allocated lli list */ 1120 ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len, 1121 cohc_dev_addr(cohc), 1122 ctrl_chained, 1123 ctrl, 1124 ctrl_last, 1125 direction, COH901318_CX_CTRL_TC_IRQ_ENABLE); 1126 if (ret) 1127 goto err_lli_fill; 1128 1129 /* 1130 * Set the default ctrl for the channel to the one from the lli, 1131 * things may have changed due to odd buffer alignment etc. 1132 */ 1133 coh901318_set_ctrl(cohc, lli->control); 1134 1135 COH_DBG(coh901318_list_print(cohc, lli)); 1136 1137 /* Pick a descriptor to handle this transfer */ 1138 cohd = coh901318_desc_get(cohc); 1139 cohd->dir = direction; 1140 cohd->flags = flags; 1141 cohd->desc.tx_submit = coh901318_tx_submit; 1142 cohd->lli = lli; 1143 1144 spin_unlock_irqrestore(&cohc->lock, flg); 1145 1146 return &cohd->desc; 1147 err_lli_fill: 1148 err_dma_alloc: 1149 err_direction: 1150 spin_unlock_irqrestore(&cohc->lock, flg); 1151 out: 1152 return NULL; 1153} 1154 1155static enum dma_status 1156coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 1157 struct dma_tx_state *txstate) 1158{ 1159 struct coh901318_chan *cohc = to_coh901318_chan(chan); 1160 dma_cookie_t last_used; 1161 dma_cookie_t last_complete; 1162 int ret; 1163 1164 last_complete = cohc->completed; 1165 last_used = chan->cookie; 1166 1167 ret = dma_async_is_complete(cookie, last_complete, last_used); 1168 1169 dma_set_tx_state(txstate, last_complete, last_used, 1170 coh901318_get_bytes_left(chan)); 1171 if (ret == DMA_IN_PROGRESS && cohc->stopped) 1172 ret = DMA_PAUSED; 1173 1174 return ret; 1175} 1176 1177static void 1178coh901318_issue_pending(struct dma_chan *chan) 1179{ 1180 struct coh901318_chan *cohc = to_coh901318_chan(chan); 1181 unsigned long flags; 1182 1183 spin_lock_irqsave(&cohc->lock, flags); 1184 1185 /* 1186 * Busy means that pending jobs are already being processed, 1187 * and then there is no point in starting the queue: the 1188 * terminal count interrupt on the channel will take the next 1189 * job on the queue and execute it anyway. 1190 */ 1191 if (!cohc->busy) 1192 coh901318_queue_start(cohc); 1193 1194 spin_unlock_irqrestore(&cohc->lock, flags); 1195} 1196 1197/* 1198 * Here we wrap in the runtime dma control interface 1199 */ 1200struct burst_table { 1201 int burst_8bit; 1202 int burst_16bit; 1203 int burst_32bit; 1204 u32 reg; 1205}; 1206 1207static const struct burst_table burst_sizes[] = { 1208 { 1209 .burst_8bit = 64, 1210 .burst_16bit = 32, 1211 .burst_32bit = 16, 1212 .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES, 1213 }, 1214 { 1215 .burst_8bit = 48, 1216 .burst_16bit = 24, 1217 .burst_32bit = 12, 1218 .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES, 1219 }, 1220 { 1221 .burst_8bit = 32, 1222 .burst_16bit = 16, 1223 .burst_32bit = 8, 1224 .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES, 1225 }, 1226 { 1227 .burst_8bit = 16, 1228 .burst_16bit = 8, 1229 .burst_32bit = 4, 1230 .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES, 1231 }, 1232 { 1233 .burst_8bit = 8, 1234 .burst_16bit = 4, 1235 .burst_32bit = 2, 1236 .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES, 1237 }, 1238 { 1239 .burst_8bit = 4, 1240 .burst_16bit = 2, 1241 .burst_32bit = 1, 1242 .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES, 1243 }, 1244 { 1245 .burst_8bit = 2, 1246 .burst_16bit = 1, 1247 .burst_32bit = 0, 1248 .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES, 1249 }, 1250 { 1251 .burst_8bit = 1, 1252 .burst_16bit = 0, 1253 .burst_32bit = 0, 1254 .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE, 1255 }, 1256}; 1257 1258static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan, 1259 struct dma_slave_config *config) 1260{ 1261 struct coh901318_chan *cohc = to_coh901318_chan(chan); 1262 dma_addr_t addr; 1263 enum dma_slave_buswidth addr_width; 1264 u32 maxburst; 1265 u32 runtime_ctrl = 0; 1266 int i = 0; 1267 1268 /* We only support mem to per or per to mem transfers */ 1269 if (config->direction == DMA_FROM_DEVICE) { 1270 addr = config->src_addr; 1271 addr_width = config->src_addr_width; 1272 maxburst = config->src_maxburst; 1273 } else if (config->direction == DMA_TO_DEVICE) { 1274 addr = config->dst_addr; 1275 addr_width = config->dst_addr_width; 1276 maxburst = config->dst_maxburst; 1277 } else { 1278 dev_err(COHC_2_DEV(cohc), "illegal channel mode\n"); 1279 return; 1280 } 1281 1282 dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n", 1283 addr_width); 1284 switch (addr_width) { 1285 case DMA_SLAVE_BUSWIDTH_1_BYTE: 1286 runtime_ctrl |= 1287 COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS | 1288 COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS; 1289 1290 while (i < ARRAY_SIZE(burst_sizes)) { 1291 if (burst_sizes[i].burst_8bit <= maxburst) 1292 break; 1293 i++; 1294 } 1295 1296 break; 1297 case DMA_SLAVE_BUSWIDTH_2_BYTES: 1298 runtime_ctrl |= 1299 COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS | 1300 COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS; 1301 1302 while (i < ARRAY_SIZE(burst_sizes)) { 1303 if (burst_sizes[i].burst_16bit <= maxburst) 1304 break; 1305 i++; 1306 } 1307 1308 break; 1309 case DMA_SLAVE_BUSWIDTH_4_BYTES: 1310 /* Direction doesn't matter here, it's 32/32 bits */ 1311 runtime_ctrl |= 1312 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | 1313 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS; 1314 1315 while (i < ARRAY_SIZE(burst_sizes)) { 1316 if (burst_sizes[i].burst_32bit <= maxburst) 1317 break; 1318 i++; 1319 } 1320 1321 break; 1322 default: 1323 dev_err(COHC_2_DEV(cohc), 1324 "bad runtimeconfig: alien address width\n"); 1325 return; 1326 } 1327 1328 runtime_ctrl |= burst_sizes[i].reg; 1329 dev_dbg(COHC_2_DEV(cohc), 1330 "selected burst size %d bytes for address width %d bytes, maxburst %d\n", 1331 burst_sizes[i].burst_8bit, addr_width, maxburst); 1332 1333 cohc->runtime_addr = addr; 1334 cohc->runtime_ctrl = runtime_ctrl; 1335} 1336 1337static int 1338coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 1339 unsigned long arg) 1340{ 1341 unsigned long flags; 1342 struct coh901318_chan *cohc = to_coh901318_chan(chan); 1343 struct coh901318_desc *cohd; 1344 void __iomem *virtbase = cohc->base->virtbase; 1345 1346 if (cmd == DMA_SLAVE_CONFIG) { 1347 struct dma_slave_config *config = 1348 (struct dma_slave_config *) arg; 1349 1350 coh901318_dma_set_runtimeconfig(chan, config); 1351 return 0; 1352 } 1353 1354 if (cmd == DMA_PAUSE) { 1355 coh901318_pause(chan); 1356 return 0; 1357 } 1358 1359 if (cmd == DMA_RESUME) { 1360 coh901318_resume(chan); 1361 return 0; 1362 } 1363 1364 if (cmd != DMA_TERMINATE_ALL) 1365 return -ENXIO; 1366 1367 /* The remainder of this function terminates the transfer */ 1368 coh901318_pause(chan); 1369 spin_lock_irqsave(&cohc->lock, flags); 1370 1371 /* Clear any pending BE or TC interrupt */ 1372 if (cohc->id < 32) { 1373 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1); 1374 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1); 1375 } else { 1376 writel(1 << (cohc->id - 32), virtbase + 1377 COH901318_BE_INT_CLEAR2); 1378 writel(1 << (cohc->id - 32), virtbase + 1379 COH901318_TC_INT_CLEAR2); 1380 } 1381 1382 enable_powersave(cohc); 1383 1384 while ((cohd = coh901318_first_active_get(cohc))) { 1385 /* release the lli allocation*/ 1386 coh901318_lli_free(&cohc->base->pool, &cohd->lli); 1387 1388 /* return desc to free-list */ 1389 coh901318_desc_remove(cohd); 1390 coh901318_desc_free(cohc, cohd); 1391 } 1392 1393 while ((cohd = coh901318_first_queued(cohc))) { 1394 /* release the lli allocation*/ 1395 coh901318_lli_free(&cohc->base->pool, &cohd->lli); 1396 1397 /* return desc to free-list */ 1398 coh901318_desc_remove(cohd); 1399 coh901318_desc_free(cohc, cohd); 1400 } 1401 1402 1403 cohc->nbr_active_done = 0; 1404 cohc->busy = 0; 1405 1406 spin_unlock_irqrestore(&cohc->lock, flags); 1407 1408 return 0; 1409} 1410 1411void coh901318_base_init(struct dma_device *dma, const int *pick_chans, 1412 struct coh901318_base *base) 1413{ 1414 int chans_i; 1415 int i = 0; 1416 struct coh901318_chan *cohc; 1417 1418 INIT_LIST_HEAD(&dma->channels); 1419 1420 for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) { 1421 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) { 1422 cohc = &base->chans[i]; 1423 1424 cohc->base = base; 1425 cohc->chan.device = dma; 1426 cohc->id = i; 1427 1428 /* TODO: do we really need this lock if only one 1429 * client is connected to each channel? 1430 */ 1431 1432 spin_lock_init(&cohc->lock); 1433 1434 cohc->nbr_active_done = 0; 1435 cohc->busy = 0; 1436 INIT_LIST_HEAD(&cohc->free); 1437 INIT_LIST_HEAD(&cohc->active); 1438 INIT_LIST_HEAD(&cohc->queue); 1439 1440 tasklet_init(&cohc->tasklet, dma_tasklet, 1441 (unsigned long) cohc); 1442 1443 list_add_tail(&cohc->chan.device_node, 1444 &dma->channels); 1445 } 1446 } 1447} 1448 1449static int __init coh901318_probe(struct platform_device *pdev) 1450{ 1451 int err = 0; 1452 struct coh901318_platform *pdata; 1453 struct coh901318_base *base; 1454 int irq; 1455 struct resource *io; 1456 1457 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1458 if (!io) 1459 goto err_get_resource; 1460 1461 /* Map DMA controller registers to virtual memory */ 1462 if (request_mem_region(io->start, 1463 resource_size(io), 1464 pdev->dev.driver->name) == NULL) { 1465 err = -EBUSY; 1466 goto err_request_mem; 1467 } 1468 1469 pdata = pdev->dev.platform_data; 1470 if (!pdata) 1471 goto err_no_platformdata; 1472 1473 base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) + 1474 pdata->max_channels * 1475 sizeof(struct coh901318_chan), 1476 GFP_KERNEL); 1477 if (!base) 1478 goto err_alloc_coh_dma_channels; 1479 1480 base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4); 1481 1482 base->virtbase = ioremap(io->start, resource_size(io)); 1483 if (!base->virtbase) { 1484 err = -ENOMEM; 1485 goto err_no_ioremap; 1486 } 1487 1488 base->dev = &pdev->dev; 1489 base->platform = pdata; 1490 spin_lock_init(&base->pm.lock); 1491 base->pm.started_channels = 0; 1492 1493 COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base); 1494 1495 platform_set_drvdata(pdev, base); 1496 1497 irq = platform_get_irq(pdev, 0); 1498 if (irq < 0) 1499 goto err_no_irq; 1500 1501 err = request_irq(irq, dma_irq_handler, IRQF_DISABLED, 1502 "coh901318", base); 1503 if (err) { 1504 dev_crit(&pdev->dev, 1505 "Cannot allocate IRQ for DMA controller!\n"); 1506 goto err_request_irq; 1507 } 1508 1509 err = coh901318_pool_create(&base->pool, &pdev->dev, 1510 sizeof(struct coh901318_lli), 1511 32); 1512 if (err) 1513 goto err_pool_create; 1514 1515 /* init channels for device transfers */ 1516 coh901318_base_init(&base->dma_slave, base->platform->chans_slave, 1517 base); 1518 1519 dma_cap_zero(base->dma_slave.cap_mask); 1520 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); 1521 1522 base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources; 1523 base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources; 1524 base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg; 1525 base->dma_slave.device_tx_status = coh901318_tx_status; 1526 base->dma_slave.device_issue_pending = coh901318_issue_pending; 1527 base->dma_slave.device_control = coh901318_control; 1528 base->dma_slave.dev = &pdev->dev; 1529 1530 err = dma_async_device_register(&base->dma_slave); 1531 1532 if (err) 1533 goto err_register_slave; 1534 1535 /* init channels for memcpy */ 1536 coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy, 1537 base); 1538 1539 dma_cap_zero(base->dma_memcpy.cap_mask); 1540 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); 1541 1542 base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources; 1543 base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources; 1544 base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy; 1545 base->dma_memcpy.device_tx_status = coh901318_tx_status; 1546 base->dma_memcpy.device_issue_pending = coh901318_issue_pending; 1547 base->dma_memcpy.device_control = coh901318_control; 1548 base->dma_memcpy.dev = &pdev->dev; 1549 /* 1550 * This controller can only access address at even 32bit boundaries, 1551 * i.e. 2^2 1552 */ 1553 base->dma_memcpy.copy_align = 2; 1554 err = dma_async_device_register(&base->dma_memcpy); 1555 1556 if (err) 1557 goto err_register_memcpy; 1558 1559 dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n", 1560 (u32) base->virtbase); 1561 1562 return err; 1563 1564 err_register_memcpy: 1565 dma_async_device_unregister(&base->dma_slave); 1566 err_register_slave: 1567 coh901318_pool_destroy(&base->pool); 1568 err_pool_create: 1569 free_irq(platform_get_irq(pdev, 0), base); 1570 err_request_irq: 1571 err_no_irq: 1572 iounmap(base->virtbase); 1573 err_no_ioremap: 1574 kfree(base); 1575 err_alloc_coh_dma_channels: 1576 err_no_platformdata: 1577 release_mem_region(pdev->resource->start, 1578 resource_size(pdev->resource)); 1579 err_request_mem: 1580 err_get_resource: 1581 return err; 1582} 1583 1584static int __exit coh901318_remove(struct platform_device *pdev) 1585{ 1586 struct coh901318_base *base = platform_get_drvdata(pdev); 1587 1588 dma_async_device_unregister(&base->dma_memcpy); 1589 dma_async_device_unregister(&base->dma_slave); 1590 coh901318_pool_destroy(&base->pool); 1591 free_irq(platform_get_irq(pdev, 0), base); 1592 iounmap(base->virtbase); 1593 kfree(base); 1594 release_mem_region(pdev->resource->start, 1595 resource_size(pdev->resource)); 1596 return 0; 1597} 1598 1599 1600static struct platform_driver coh901318_driver = { 1601 .remove = __exit_p(coh901318_remove), 1602 .driver = { 1603 .name = "coh901318", 1604 }, 1605}; 1606 1607int __init coh901318_init(void) 1608{ 1609 return platform_driver_probe(&coh901318_driver, coh901318_probe); 1610} 1611subsys_initcall(coh901318_init); 1612 1613void __exit coh901318_exit(void) 1614{ 1615 platform_driver_unregister(&coh901318_driver); 1616} 1617module_exit(coh901318_exit); 1618 1619MODULE_LICENSE("GPL"); 1620MODULE_AUTHOR("Per Friden"); 1621