1/* 2 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru> 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20#include <linux/kernel.h> 21#include <linux/module.h> 22#include <linux/moduleparam.h> 23#include <linux/mod_devicetable.h> 24#include <linux/interrupt.h> 25#include <linux/pci.h> 26#include <linux/slab.h> 27#include <linux/delay.h> 28#include <linux/mm.h> 29#include <linux/dma-mapping.h> 30#include <linux/scatterlist.h> 31#include <linux/highmem.h> 32#include <linux/crypto.h> 33#include <linux/hw_random.h> 34#include <linux/ktime.h> 35 36#include <crypto/algapi.h> 37#include <crypto/des.h> 38 39#include <asm/kmap_types.h> 40 41//#define HIFN_DEBUG 42 43#ifdef HIFN_DEBUG 44#define dprintk(f, a...) printk(f, ##a) 45#else 46#define dprintk(f, a...) do {} while (0) 47#endif 48 49static char hifn_pll_ref[sizeof("extNNN")] = "ext"; 50module_param_string(hifn_pll_ref, hifn_pll_ref, sizeof(hifn_pll_ref), 0444); 51MODULE_PARM_DESC(hifn_pll_ref, 52 "PLL reference clock (pci[freq] or ext[freq], default ext)"); 53 54static atomic_t hifn_dev_number; 55 56#define ACRYPTO_OP_DECRYPT 0 57#define ACRYPTO_OP_ENCRYPT 1 58#define ACRYPTO_OP_HMAC 2 59#define ACRYPTO_OP_RNG 3 60 61#define ACRYPTO_MODE_ECB 0 62#define ACRYPTO_MODE_CBC 1 63#define ACRYPTO_MODE_CFB 2 64#define ACRYPTO_MODE_OFB 3 65 66#define ACRYPTO_TYPE_AES_128 0 67#define ACRYPTO_TYPE_AES_192 1 68#define ACRYPTO_TYPE_AES_256 2 69#define ACRYPTO_TYPE_3DES 3 70#define ACRYPTO_TYPE_DES 4 71 72#define PCI_VENDOR_ID_HIFN 0x13A3 73#define PCI_DEVICE_ID_HIFN_7955 0x0020 74#define PCI_DEVICE_ID_HIFN_7956 0x001d 75 76/* I/O region sizes */ 77 78#define HIFN_BAR0_SIZE 0x1000 79#define HIFN_BAR1_SIZE 0x2000 80#define HIFN_BAR2_SIZE 0x8000 81 82/* DMA registres */ 83 84#define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */ 85#define HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */ 86#define HIFN_DMA_RRA 0x2C /* DMA Result Ring Address */ 87#define HIFN_DMA_DDRA 0x3C /* DMA Destination Data Ring Address */ 88#define HIFN_DMA_STCTL 0x40 /* DMA Status and Control */ 89#define HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */ 90#define HIFN_DMA_CFG1 0x48 /* DMA Configuration #1 */ 91#define HIFN_DMA_CFG2 0x6C /* DMA Configuration #2 */ 92#define HIFN_CHIP_ID 0x98 /* Chip ID */ 93 94/* 95 * Processing Unit Registers (offset from BASEREG0) 96 */ 97#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ 98#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ 99#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ 100#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ 101#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ 102#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ 103#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ 104#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ 105#define HIFN_0_SPACESIZE 0x20 /* Register space size */ 106 107/* Processing Unit Control Register (HIFN_0_PUCTRL) */ 108#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ 109#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ 110#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ 111#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ 112#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ 113 114/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ 115#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ 116#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ 117#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 118#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 119#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ 120#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ 121#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ 122#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ 123#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ 124#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ 125 126/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ 127#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ 128#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ 129#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ 130#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ 131#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ 132#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ 133#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ 134#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ 135#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ 136#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ 137#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ 138#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ 139#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ 140#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ 141#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ 142#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ 143#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ 144#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ 145#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ 146#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ 147#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ 148#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ 149#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ 150 151/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ 152#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ 153#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ 154#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 155#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 156#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ 157#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ 158#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ 159#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ 160#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ 161#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ 162 163/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ 164#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ 165#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ 166#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 167#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 168#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ 169#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ 170#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ 171#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ 172#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ 173#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ 174#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ 175#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ 176#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ 177#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ 178#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ 179#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ 180#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ 181 182/* FIFO Status Register (HIFN_0_FIFOSTAT) */ 183#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ 184#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ 185 186/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ 187#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */ 188 189/* 190 * DMA Interface Registers (offset from BASEREG1) 191 */ 192#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ 193#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ 194#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ 195#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ 196#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ 197#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ 198#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ 199#define HIFN_1_PLL 0x4c /* 795x: PLL config */ 200#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ 201#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ 202#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ 203#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ 204#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ 205#define HIFN_1_REVID 0x98 /* Revision ID */ 206#define HIFN_1_UNLOCK_SECRET1 0xf4 207#define HIFN_1_UNLOCK_SECRET2 0xfc 208#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ 209#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ 210#define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */ 211#define HIFN_1_PUB_OP 0x308 /* Public Operand */ 212#define HIFN_1_PUB_STATUS 0x30c /* Public Status */ 213#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ 214#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ 215#define HIFN_1_RNG_DATA 0x318 /* RNG data */ 216#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ 217#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ 218 219/* DMA Status and Control Register (HIFN_1_DMA_CSR) */ 220#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ 221#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ 222#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ 223#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ 224#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ 225#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ 226#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ 227#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ 228#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ 229#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ 230#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ 231#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ 232#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ 233#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ 234#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ 235#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ 236#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ 237#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ 238#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ 239#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ 240#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ 241#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ 242#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ 243#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ 244#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ 245#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ 246#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ 247#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ 248#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ 249#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ 250#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ 251#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ 252#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ 253#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ 254#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ 255#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ 256#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ 257#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ 258 259/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ 260#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ 261#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ 262#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ 263#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ 264#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ 265#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ 266#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ 267#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ 268#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ 269#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ 270#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ 271#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ 272#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ 273#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ 274#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ 275#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ 276#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ 277#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ 278#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ 279#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ 280#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ 281#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ 282 283/* DMA Configuration Register (HIFN_1_DMA_CNFG) */ 284#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ 285#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ 286#define HIFN_DMACNFG_UNLOCK 0x00000800 287#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ 288#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ 289#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ 290#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ 291#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ 292 293/* PLL configuration register */ 294#define HIFN_PLL_REF_CLK_HBI 0x00000000 /* HBI reference clock */ 295#define HIFN_PLL_REF_CLK_PLL 0x00000001 /* PLL reference clock */ 296#define HIFN_PLL_BP 0x00000002 /* Reference clock bypass */ 297#define HIFN_PLL_PK_CLK_HBI 0x00000000 /* PK engine HBI clock */ 298#define HIFN_PLL_PK_CLK_PLL 0x00000008 /* PK engine PLL clock */ 299#define HIFN_PLL_PE_CLK_HBI 0x00000000 /* PE engine HBI clock */ 300#define HIFN_PLL_PE_CLK_PLL 0x00000010 /* PE engine PLL clock */ 301#define HIFN_PLL_RESERVED_1 0x00000400 /* Reserved bit, must be 1 */ 302#define HIFN_PLL_ND_SHIFT 11 /* Clock multiplier shift */ 303#define HIFN_PLL_ND_MULT_2 0x00000000 /* PLL clock multiplier 2 */ 304#define HIFN_PLL_ND_MULT_4 0x00000800 /* PLL clock multiplier 4 */ 305#define HIFN_PLL_ND_MULT_6 0x00001000 /* PLL clock multiplier 6 */ 306#define HIFN_PLL_ND_MULT_8 0x00001800 /* PLL clock multiplier 8 */ 307#define HIFN_PLL_ND_MULT_10 0x00002000 /* PLL clock multiplier 10 */ 308#define HIFN_PLL_ND_MULT_12 0x00002800 /* PLL clock multiplier 12 */ 309#define HIFN_PLL_IS_1_8 0x00000000 /* charge pump (mult. 1-8) */ 310#define HIFN_PLL_IS_9_12 0x00010000 /* charge pump (mult. 9-12) */ 311 312#define HIFN_PLL_FCK_MAX 266 /* Maximum PLL frequency */ 313 314/* Public key reset register (HIFN_1_PUB_RESET) */ 315#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ 316 317/* Public base address register (HIFN_1_PUB_BASE) */ 318#define HIFN_PUBBASE_ADDR 0x00003fff /* base address */ 319 320/* Public operand length register (HIFN_1_PUB_OPLEN) */ 321#define HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */ 322#define HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */ 323#define HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */ 324#define HIFN_PUBOPLEN_EXP_S 7 /* exponent length shift */ 325#define HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */ 326#define HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */ 327 328/* Public operation register (HIFN_1_PUB_OP) */ 329#define HIFN_PUBOP_AOFFSET_M 0x0000007f /* A offset mask */ 330#define HIFN_PUBOP_AOFFSET_S 0 /* A offset shift */ 331#define HIFN_PUBOP_BOFFSET_M 0x00000f80 /* B offset mask */ 332#define HIFN_PUBOP_BOFFSET_S 7 /* B offset shift */ 333#define HIFN_PUBOP_MOFFSET_M 0x0003f000 /* M offset mask */ 334#define HIFN_PUBOP_MOFFSET_S 12 /* M offset shift */ 335#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ 336#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ 337#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ 338#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ 339#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ 340#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ 341#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ 342#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ 343#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ 344#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ 345#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ 346#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ 347#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular RED */ 348#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular EXP */ 349 350/* Public status register (HIFN_1_PUB_STATUS) */ 351#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ 352#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ 353 354/* Public interrupt enable register (HIFN_1_PUB_IEN) */ 355#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ 356 357/* Random number generator config register (HIFN_1_RNG_CONFIG) */ 358#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ 359 360#define HIFN_NAMESIZE 32 361#define HIFN_MAX_RESULT_ORDER 5 362 363#define HIFN_D_CMD_RSIZE 24*1 364#define HIFN_D_SRC_RSIZE 80*1 365#define HIFN_D_DST_RSIZE 80*1 366#define HIFN_D_RES_RSIZE 24*1 367 368#define HIFN_D_DST_DALIGN 4 369 370#define HIFN_QUEUE_LENGTH (HIFN_D_CMD_RSIZE - 1) 371 372#define AES_MIN_KEY_SIZE 16 373#define AES_MAX_KEY_SIZE 32 374 375#define HIFN_DES_KEY_LENGTH 8 376#define HIFN_3DES_KEY_LENGTH 24 377#define HIFN_MAX_CRYPT_KEY_LENGTH AES_MAX_KEY_SIZE 378#define HIFN_IV_LENGTH 8 379#define HIFN_AES_IV_LENGTH 16 380#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH 381 382#define HIFN_MAC_KEY_LENGTH 64 383#define HIFN_MD5_LENGTH 16 384#define HIFN_SHA1_LENGTH 20 385#define HIFN_MAC_TRUNC_LENGTH 12 386 387#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) 388#define HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4) 389#define HIFN_USED_RESULT 12 390 391struct hifn_desc 392{ 393 volatile __le32 l; 394 volatile __le32 p; 395}; 396 397struct hifn_dma { 398 struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1]; 399 struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1]; 400 struct hifn_desc dstr[HIFN_D_DST_RSIZE+1]; 401 struct hifn_desc resr[HIFN_D_RES_RSIZE+1]; 402 403 u8 command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; 404 u8 result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; 405 406 /* 407 * Our current positions for insertion and removal from the descriptor 408 * rings. 409 */ 410 volatile int cmdi, srci, dsti, resi; 411 volatile int cmdu, srcu, dstu, resu; 412 int cmdk, srck, dstk, resk; 413}; 414 415#define HIFN_FLAG_CMD_BUSY (1<<0) 416#define HIFN_FLAG_SRC_BUSY (1<<1) 417#define HIFN_FLAG_DST_BUSY (1<<2) 418#define HIFN_FLAG_RES_BUSY (1<<3) 419#define HIFN_FLAG_OLD_KEY (1<<4) 420 421#define HIFN_DEFAULT_ACTIVE_NUM 5 422 423struct hifn_device 424{ 425 char name[HIFN_NAMESIZE]; 426 427 int irq; 428 429 struct pci_dev *pdev; 430 void __iomem *bar[3]; 431 432 void *desc_virt; 433 dma_addr_t desc_dma; 434 435 u32 dmareg; 436 437 void *sa[HIFN_D_RES_RSIZE]; 438 439 spinlock_t lock; 440 441 u32 flags; 442 int active, started; 443 struct delayed_work work; 444 unsigned long reset; 445 unsigned long success; 446 unsigned long prev_success; 447 448 u8 snum; 449 450 struct tasklet_struct tasklet; 451 452 struct crypto_queue queue; 453 struct list_head alg_list; 454 455 unsigned int pk_clk_freq; 456 457#ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG 458 unsigned int rng_wait_time; 459 ktime_t rngtime; 460 struct hwrng rng; 461#endif 462}; 463 464#define HIFN_D_LENGTH 0x0000ffff 465#define HIFN_D_NOINVALID 0x01000000 466#define HIFN_D_MASKDONEIRQ 0x02000000 467#define HIFN_D_DESTOVER 0x04000000 468#define HIFN_D_OVER 0x08000000 469#define HIFN_D_LAST 0x20000000 470#define HIFN_D_JUMP 0x40000000 471#define HIFN_D_VALID 0x80000000 472 473struct hifn_base_command 474{ 475 volatile __le16 masks; 476 volatile __le16 session_num; 477 volatile __le16 total_source_count; 478 volatile __le16 total_dest_count; 479}; 480 481#define HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */ 482#define HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */ 483#define HIFN_BASE_CMD_MAC 0x0400 /* enable MAC engine */ 484#define HIFN_BASE_CMD_CRYPT 0x0800 /* enable crypt engine */ 485#define HIFN_BASE_CMD_DECODE 0x2000 486#define HIFN_BASE_CMD_SRCLEN_M 0xc000 487#define HIFN_BASE_CMD_SRCLEN_S 14 488#define HIFN_BASE_CMD_DSTLEN_M 0x3000 489#define HIFN_BASE_CMD_DSTLEN_S 12 490#define HIFN_BASE_CMD_LENMASK_HI 0x30000 491#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff 492 493/* 494 * Structure to help build up the command data structure. 495 */ 496struct hifn_crypt_command 497{ 498 volatile __le16 masks; 499 volatile __le16 header_skip; 500 volatile __le16 source_count; 501 volatile __le16 reserved; 502}; 503 504#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ 505#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ 506#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ 507#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ 508#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ 509#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ 510#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ 511#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ 512#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ 513#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ 514#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ 515#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ 516#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ 517#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ 518#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ 519#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ 520#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ 521#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 522#define HIFN_CRYPT_CMD_SRCLEN_S 14 523 524/* 525 * Structure to help build up the command data structure. 526 */ 527struct hifn_mac_command 528{ 529 volatile __le16 masks; 530 volatile __le16 header_skip; 531 volatile __le16 source_count; 532 volatile __le16 reserved; 533}; 534 535#define HIFN_MAC_CMD_ALG_MASK 0x0001 536#define HIFN_MAC_CMD_ALG_SHA1 0x0000 537#define HIFN_MAC_CMD_ALG_MD5 0x0001 538#define HIFN_MAC_CMD_MODE_MASK 0x000c 539#define HIFN_MAC_CMD_MODE_HMAC 0x0000 540#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 541#define HIFN_MAC_CMD_MODE_HASH 0x0008 542#define HIFN_MAC_CMD_MODE_FULL 0x0004 543#define HIFN_MAC_CMD_TRUNC 0x0010 544#define HIFN_MAC_CMD_RESULT 0x0020 545#define HIFN_MAC_CMD_APPEND 0x0040 546#define HIFN_MAC_CMD_SRCLEN_M 0xc000 547#define HIFN_MAC_CMD_SRCLEN_S 14 548 549/* 550 * MAC POS IPsec initiates authentication after encryption on encodes 551 * and before decryption on decodes. 552 */ 553#define HIFN_MAC_CMD_POS_IPSEC 0x0200 554#define HIFN_MAC_CMD_NEW_KEY 0x0800 555 556struct hifn_comp_command 557{ 558 volatile __le16 masks; 559 volatile __le16 header_skip; 560 volatile __le16 source_count; 561 volatile __le16 reserved; 562}; 563 564#define HIFN_COMP_CMD_SRCLEN_M 0xc000 565#define HIFN_COMP_CMD_SRCLEN_S 14 566#define HIFN_COMP_CMD_ONE 0x0100 /* must be one */ 567#define HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */ 568#define HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */ 569#define HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */ 570#define HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */ 571#define HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */ 572#define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */ 573#define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */ 574 575struct hifn_base_result 576{ 577 volatile __le16 flags; 578 volatile __le16 session; 579 volatile __le16 src_cnt; /* 15:0 of source count */ 580 volatile __le16 dst_cnt; /* 15:0 of dest count */ 581}; 582 583#define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */ 584#define HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */ 585#define HIFN_BASE_RES_SRCLEN_S 14 586#define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */ 587#define HIFN_BASE_RES_DSTLEN_S 12 588 589struct hifn_comp_result 590{ 591 volatile __le16 flags; 592 volatile __le16 crc; 593}; 594 595#define HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */ 596#define HIFN_COMP_RES_LCB_S 8 597#define HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */ 598#define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */ 599#define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */ 600 601struct hifn_mac_result 602{ 603 volatile __le16 flags; 604 volatile __le16 reserved; 605 /* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */ 606}; 607 608#define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */ 609#define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */ 610 611struct hifn_crypt_result 612{ 613 volatile __le16 flags; 614 volatile __le16 reserved; 615}; 616 617#define HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */ 618 619#ifndef HIFN_POLL_FREQUENCY 620#define HIFN_POLL_FREQUENCY 0x1 621#endif 622 623#ifndef HIFN_POLL_SCALAR 624#define HIFN_POLL_SCALAR 0x0 625#endif 626 627#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ 628#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ 629 630struct hifn_crypto_alg 631{ 632 struct list_head entry; 633 struct crypto_alg alg; 634 struct hifn_device *dev; 635}; 636 637#define ASYNC_SCATTERLIST_CACHE 16 638 639#define ASYNC_FLAGS_MISALIGNED (1<<0) 640 641struct hifn_cipher_walk 642{ 643 struct scatterlist cache[ASYNC_SCATTERLIST_CACHE]; 644 u32 flags; 645 int num; 646}; 647 648struct hifn_context 649{ 650 u8 key[HIFN_MAX_CRYPT_KEY_LENGTH]; 651 struct hifn_device *dev; 652 unsigned int keysize; 653}; 654 655struct hifn_request_context 656{ 657 u8 *iv; 658 unsigned int ivsize; 659 u8 op, type, mode, unused; 660 struct hifn_cipher_walk walk; 661}; 662 663#define crypto_alg_to_hifn(a) container_of(a, struct hifn_crypto_alg, alg) 664 665static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg) 666{ 667 u32 ret; 668 669 ret = readl(dev->bar[0] + reg); 670 671 return ret; 672} 673 674static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg) 675{ 676 u32 ret; 677 678 ret = readl(dev->bar[1] + reg); 679 680 return ret; 681} 682 683static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val) 684{ 685 writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg); 686} 687 688static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val) 689{ 690 writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg); 691} 692 693static void hifn_wait_puc(struct hifn_device *dev) 694{ 695 int i; 696 u32 ret; 697 698 for (i=10000; i > 0; --i) { 699 ret = hifn_read_0(dev, HIFN_0_PUCTRL); 700 if (!(ret & HIFN_PUCTRL_RESET)) 701 break; 702 703 udelay(1); 704 } 705 706 if (!i) 707 dprintk("%s: Failed to reset PUC unit.\n", dev->name); 708} 709 710static void hifn_reset_puc(struct hifn_device *dev) 711{ 712 hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 713 hifn_wait_puc(dev); 714} 715 716static void hifn_stop_device(struct hifn_device *dev) 717{ 718 hifn_write_1(dev, HIFN_1_DMA_CSR, 719 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 720 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS); 721 hifn_write_0(dev, HIFN_0_PUIER, 0); 722 hifn_write_1(dev, HIFN_1_DMA_IER, 0); 723} 724 725static void hifn_reset_dma(struct hifn_device *dev, int full) 726{ 727 hifn_stop_device(dev); 728 729 /* 730 * Setting poll frequency and others to 0. 731 */ 732 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 733 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 734 mdelay(1); 735 736 /* 737 * Reset DMA. 738 */ 739 if (full) { 740 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 741 mdelay(1); 742 } else { 743 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE | 744 HIFN_DMACNFG_MSTRESET); 745 hifn_reset_puc(dev); 746 } 747 748 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 749 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 750 751 hifn_reset_puc(dev); 752} 753 754static u32 hifn_next_signature(u_int32_t a, u_int cnt) 755{ 756 int i; 757 u32 v; 758 759 for (i = 0; i < cnt; i++) { 760 761 /* get the parity */ 762 v = a & 0x80080125; 763 v ^= v >> 16; 764 v ^= v >> 8; 765 v ^= v >> 4; 766 v ^= v >> 2; 767 v ^= v >> 1; 768 769 a = (v & 1) ^ (a << 1); 770 } 771 772 return a; 773} 774 775static struct pci2id { 776 u_short pci_vendor; 777 u_short pci_prod; 778 char card_id[13]; 779} pci2id[] = { 780 { 781 PCI_VENDOR_ID_HIFN, 782 PCI_DEVICE_ID_HIFN_7955, 783 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 784 0x00, 0x00, 0x00, 0x00, 0x00 } 785 }, 786 { 787 PCI_VENDOR_ID_HIFN, 788 PCI_DEVICE_ID_HIFN_7956, 789 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 790 0x00, 0x00, 0x00, 0x00, 0x00 } 791 } 792}; 793 794#ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG 795static int hifn_rng_data_present(struct hwrng *rng, int wait) 796{ 797 struct hifn_device *dev = (struct hifn_device *)rng->priv; 798 s64 nsec; 799 800 nsec = ktime_to_ns(ktime_sub(ktime_get(), dev->rngtime)); 801 nsec -= dev->rng_wait_time; 802 if (nsec <= 0) 803 return 1; 804 if (!wait) 805 return 0; 806 ndelay(nsec); 807 return 1; 808} 809 810static int hifn_rng_data_read(struct hwrng *rng, u32 *data) 811{ 812 struct hifn_device *dev = (struct hifn_device *)rng->priv; 813 814 *data = hifn_read_1(dev, HIFN_1_RNG_DATA); 815 dev->rngtime = ktime_get(); 816 return 4; 817} 818 819static int hifn_register_rng(struct hifn_device *dev) 820{ 821 /* 822 * We must wait at least 256 Pk_clk cycles between two reads of the rng. 823 */ 824 dev->rng_wait_time = DIV_ROUND_UP(NSEC_PER_SEC, dev->pk_clk_freq) * 825 256; 826 827 dev->rng.name = dev->name; 828 dev->rng.data_present = hifn_rng_data_present, 829 dev->rng.data_read = hifn_rng_data_read, 830 dev->rng.priv = (unsigned long)dev; 831 832 return hwrng_register(&dev->rng); 833} 834 835static void hifn_unregister_rng(struct hifn_device *dev) 836{ 837 hwrng_unregister(&dev->rng); 838} 839#else 840#define hifn_register_rng(dev) 0 841#define hifn_unregister_rng(dev) 842#endif 843 844static int hifn_init_pubrng(struct hifn_device *dev) 845{ 846 int i; 847 848 hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) | 849 HIFN_PUBRST_RESET); 850 851 for (i=100; i > 0; --i) { 852 mdelay(1); 853 854 if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0) 855 break; 856 } 857 858 if (!i) 859 dprintk("Chip %s: Failed to initialise public key engine.\n", 860 dev->name); 861 else { 862 hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 863 dev->dmareg |= HIFN_DMAIER_PUBDONE; 864 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); 865 866 dprintk("Chip %s: Public key engine has been successfully " 867 "initialised.\n", dev->name); 868 } 869 870 /* 871 * Enable RNG engine. 872 */ 873 874 hifn_write_1(dev, HIFN_1_RNG_CONFIG, 875 hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA); 876 dprintk("Chip %s: RNG engine has been successfully initialised.\n", 877 dev->name); 878 879#ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG 880 /* First value must be discarded */ 881 hifn_read_1(dev, HIFN_1_RNG_DATA); 882 dev->rngtime = ktime_get(); 883#endif 884 return 0; 885} 886 887static int hifn_enable_crypto(struct hifn_device *dev) 888{ 889 u32 dmacfg, addr; 890 char *offtbl = NULL; 891 int i; 892 893 for (i = 0; i < ARRAY_SIZE(pci2id); i++) { 894 if (pci2id[i].pci_vendor == dev->pdev->vendor && 895 pci2id[i].pci_prod == dev->pdev->device) { 896 offtbl = pci2id[i].card_id; 897 break; 898 } 899 } 900 901 if (offtbl == NULL) { 902 dprintk("Chip %s: Unknown card!\n", dev->name); 903 return -ENODEV; 904 } 905 906 dmacfg = hifn_read_1(dev, HIFN_1_DMA_CNFG); 907 908 hifn_write_1(dev, HIFN_1_DMA_CNFG, 909 HIFN_DMACNFG_UNLOCK | HIFN_DMACNFG_MSTRESET | 910 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 911 mdelay(1); 912 addr = hifn_read_1(dev, HIFN_1_UNLOCK_SECRET1); 913 mdelay(1); 914 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0); 915 mdelay(1); 916 917 for (i=0; i<12; ++i) { 918 addr = hifn_next_signature(addr, offtbl[i] + 0x101); 919 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr); 920 921 mdelay(1); 922 } 923 hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg); 924 925 dprintk("Chip %s: %s.\n", dev->name, pci_name(dev->pdev)); 926 927 return 0; 928} 929 930static void hifn_init_dma(struct hifn_device *dev) 931{ 932 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; 933 u32 dptr = dev->desc_dma; 934 int i; 935 936 for (i=0; i<HIFN_D_CMD_RSIZE; ++i) 937 dma->cmdr[i].p = __cpu_to_le32(dptr + 938 offsetof(struct hifn_dma, command_bufs[i][0])); 939 for (i=0; i<HIFN_D_RES_RSIZE; ++i) 940 dma->resr[i].p = __cpu_to_le32(dptr + 941 offsetof(struct hifn_dma, result_bufs[i][0])); 942 943 /* 944 * Setup LAST descriptors. 945 */ 946 dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr + 947 offsetof(struct hifn_dma, cmdr[0])); 948 dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr + 949 offsetof(struct hifn_dma, srcr[0])); 950 dma->dstr[HIFN_D_DST_RSIZE].p = __cpu_to_le32(dptr + 951 offsetof(struct hifn_dma, dstr[0])); 952 dma->resr[HIFN_D_RES_RSIZE].p = __cpu_to_le32(dptr + 953 offsetof(struct hifn_dma, resr[0])); 954 955 dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; 956 dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; 957 dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; 958} 959 960/* 961 * Initialize the PLL. We need to know the frequency of the reference clock 962 * to calculate the optimal multiplier. For PCI we assume 66MHz, since that 963 * allows us to operate without the risk of overclocking the chip. If it 964 * actually uses 33MHz, the chip will operate at half the speed, this can be 965 * overriden by specifying the frequency as module parameter (pci33). 966 * 967 * Unfortunately the PCI clock is not very suitable since the HIFN needs a 968 * stable clock and the PCI clock frequency may vary, so the default is the 969 * external clock. There is no way to find out its frequency, we default to 970 * 66MHz since according to Mike Ham of HiFn, almost every board in existence 971 * has an external crystal populated at 66MHz. 972 */ 973static void hifn_init_pll(struct hifn_device *dev) 974{ 975 unsigned int freq, m; 976 u32 pllcfg; 977 978 pllcfg = HIFN_1_PLL | HIFN_PLL_RESERVED_1; 979 980 if (strncmp(hifn_pll_ref, "ext", 3) == 0) 981 pllcfg |= HIFN_PLL_REF_CLK_PLL; 982 else 983 pllcfg |= HIFN_PLL_REF_CLK_HBI; 984 985 if (hifn_pll_ref[3] != '\0') 986 freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10); 987 else { 988 freq = 66; 989 printk(KERN_INFO "hifn795x: assuming %uMHz clock speed, " 990 "override with hifn_pll_ref=%.3s<frequency>\n", 991 freq, hifn_pll_ref); 992 } 993 994 m = HIFN_PLL_FCK_MAX / freq; 995 996 pllcfg |= (m / 2 - 1) << HIFN_PLL_ND_SHIFT; 997 if (m <= 8) 998 pllcfg |= HIFN_PLL_IS_1_8; 999 else 1000 pllcfg |= HIFN_PLL_IS_9_12; 1001 1002 /* Select clock source and enable clock bypass */ 1003 hifn_write_1(dev, HIFN_1_PLL, pllcfg | 1004 HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI | HIFN_PLL_BP); 1005 1006 /* Let the chip lock to the input clock */ 1007 mdelay(10); 1008 1009 /* Disable clock bypass */ 1010 hifn_write_1(dev, HIFN_1_PLL, pllcfg | 1011 HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI); 1012 1013 /* Switch the engines to the PLL */ 1014 hifn_write_1(dev, HIFN_1_PLL, pllcfg | 1015 HIFN_PLL_PK_CLK_PLL | HIFN_PLL_PE_CLK_PLL); 1016 1017 /* 1018 * The Fpk_clk runs at half the total speed. Its frequency is needed to 1019 * calculate the minimum time between two reads of the rng. Since 33MHz 1020 * is actually 33.333... we overestimate the frequency here, resulting 1021 * in slightly larger intervals. 1022 */ 1023 dev->pk_clk_freq = 1000000 * (freq + 1) * m / 2; 1024} 1025 1026static void hifn_init_registers(struct hifn_device *dev) 1027{ 1028 u32 dptr = dev->desc_dma; 1029 1030 /* Initialization magic... */ 1031 hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 1032 hifn_write_0(dev, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 1033 hifn_write_0(dev, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 1034 1035 /* write all 4 ring address registers */ 1036 hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr + 1037 offsetof(struct hifn_dma, cmdr[0])); 1038 hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr + 1039 offsetof(struct hifn_dma, srcr[0])); 1040 hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr + 1041 offsetof(struct hifn_dma, dstr[0])); 1042 hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr + 1043 offsetof(struct hifn_dma, resr[0])); 1044 1045 mdelay(2); 1046 hifn_write_1(dev, HIFN_1_DMA_CSR, 1047 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1048 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA | 1049 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 1050 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 1051 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 1052 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 1053 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 1054 HIFN_DMACSR_S_WAIT | 1055 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 1056 HIFN_DMACSR_C_WAIT | 1057 HIFN_DMACSR_ENGINE | 1058 HIFN_DMACSR_PUBDONE); 1059 hifn_read_1(dev, HIFN_1_DMA_CSR); 1060 1061 dev->dmareg |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 1062 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 1063 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 1064 HIFN_DMAIER_ENGINE; 1065 dev->dmareg &= ~HIFN_DMAIER_C_WAIT; 1066 1067 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); 1068 hifn_read_1(dev, HIFN_1_DMA_IER); 1069 hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342); 1070 hifn_init_pll(dev); 1071 1072 hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1073 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 1074 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 1075 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 1076 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 1077} 1078 1079static int hifn_setup_base_command(struct hifn_device *dev, u8 *buf, 1080 unsigned dlen, unsigned slen, u16 mask, u8 snum) 1081{ 1082 struct hifn_base_command *base_cmd; 1083 u8 *buf_pos = buf; 1084 1085 base_cmd = (struct hifn_base_command *)buf_pos; 1086 base_cmd->masks = __cpu_to_le16(mask); 1087 base_cmd->total_source_count = 1088 __cpu_to_le16(slen & HIFN_BASE_CMD_LENMASK_LO); 1089 base_cmd->total_dest_count = 1090 __cpu_to_le16(dlen & HIFN_BASE_CMD_LENMASK_LO); 1091 1092 dlen >>= 16; 1093 slen >>= 16; 1094 base_cmd->session_num = __cpu_to_le16(snum | 1095 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 1096 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 1097 1098 return sizeof(struct hifn_base_command); 1099} 1100 1101static int hifn_setup_crypto_command(struct hifn_device *dev, 1102 u8 *buf, unsigned dlen, unsigned slen, 1103 u8 *key, int keylen, u8 *iv, int ivsize, u16 mode) 1104{ 1105 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; 1106 struct hifn_crypt_command *cry_cmd; 1107 u8 *buf_pos = buf; 1108 u16 cmd_len; 1109 1110 cry_cmd = (struct hifn_crypt_command *)buf_pos; 1111 1112 cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff); 1113 dlen >>= 16; 1114 cry_cmd->masks = __cpu_to_le16(mode | 1115 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & 1116 HIFN_CRYPT_CMD_SRCLEN_M)); 1117 cry_cmd->header_skip = 0; 1118 cry_cmd->reserved = 0; 1119 1120 buf_pos += sizeof(struct hifn_crypt_command); 1121 1122 dma->cmdu++; 1123 if (dma->cmdu > 1) { 1124 dev->dmareg |= HIFN_DMAIER_C_WAIT; 1125 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); 1126 } 1127 1128 if (keylen) { 1129 memcpy(buf_pos, key, keylen); 1130 buf_pos += keylen; 1131 } 1132 if (ivsize) { 1133 memcpy(buf_pos, iv, ivsize); 1134 buf_pos += ivsize; 1135 } 1136 1137 cmd_len = buf_pos - buf; 1138 1139 return cmd_len; 1140} 1141 1142static int hifn_setup_cmd_desc(struct hifn_device *dev, 1143 struct hifn_context *ctx, struct hifn_request_context *rctx, 1144 void *priv, unsigned int nbytes) 1145{ 1146 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; 1147 int cmd_len, sa_idx; 1148 u8 *buf, *buf_pos; 1149 u16 mask; 1150 1151 sa_idx = dma->cmdi; 1152 buf_pos = buf = dma->command_bufs[dma->cmdi]; 1153 1154 mask = 0; 1155 switch (rctx->op) { 1156 case ACRYPTO_OP_DECRYPT: 1157 mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE; 1158 break; 1159 case ACRYPTO_OP_ENCRYPT: 1160 mask = HIFN_BASE_CMD_CRYPT; 1161 break; 1162 case ACRYPTO_OP_HMAC: 1163 mask = HIFN_BASE_CMD_MAC; 1164 break; 1165 default: 1166 goto err_out; 1167 } 1168 1169 buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes, 1170 nbytes, mask, dev->snum); 1171 1172 if (rctx->op == ACRYPTO_OP_ENCRYPT || rctx->op == ACRYPTO_OP_DECRYPT) { 1173 u16 md = 0; 1174 1175 if (ctx->keysize) 1176 md |= HIFN_CRYPT_CMD_NEW_KEY; 1177 if (rctx->iv && rctx->mode != ACRYPTO_MODE_ECB) 1178 md |= HIFN_CRYPT_CMD_NEW_IV; 1179 1180 switch (rctx->mode) { 1181 case ACRYPTO_MODE_ECB: 1182 md |= HIFN_CRYPT_CMD_MODE_ECB; 1183 break; 1184 case ACRYPTO_MODE_CBC: 1185 md |= HIFN_CRYPT_CMD_MODE_CBC; 1186 break; 1187 case ACRYPTO_MODE_CFB: 1188 md |= HIFN_CRYPT_CMD_MODE_CFB; 1189 break; 1190 case ACRYPTO_MODE_OFB: 1191 md |= HIFN_CRYPT_CMD_MODE_OFB; 1192 break; 1193 default: 1194 goto err_out; 1195 } 1196 1197 switch (rctx->type) { 1198 case ACRYPTO_TYPE_AES_128: 1199 if (ctx->keysize != 16) 1200 goto err_out; 1201 md |= HIFN_CRYPT_CMD_KSZ_128 | 1202 HIFN_CRYPT_CMD_ALG_AES; 1203 break; 1204 case ACRYPTO_TYPE_AES_192: 1205 if (ctx->keysize != 24) 1206 goto err_out; 1207 md |= HIFN_CRYPT_CMD_KSZ_192 | 1208 HIFN_CRYPT_CMD_ALG_AES; 1209 break; 1210 case ACRYPTO_TYPE_AES_256: 1211 if (ctx->keysize != 32) 1212 goto err_out; 1213 md |= HIFN_CRYPT_CMD_KSZ_256 | 1214 HIFN_CRYPT_CMD_ALG_AES; 1215 break; 1216 case ACRYPTO_TYPE_3DES: 1217 if (ctx->keysize != 24) 1218 goto err_out; 1219 md |= HIFN_CRYPT_CMD_ALG_3DES; 1220 break; 1221 case ACRYPTO_TYPE_DES: 1222 if (ctx->keysize != 8) 1223 goto err_out; 1224 md |= HIFN_CRYPT_CMD_ALG_DES; 1225 break; 1226 default: 1227 goto err_out; 1228 } 1229 1230 buf_pos += hifn_setup_crypto_command(dev, buf_pos, 1231 nbytes, nbytes, ctx->key, ctx->keysize, 1232 rctx->iv, rctx->ivsize, md); 1233 } 1234 1235 dev->sa[sa_idx] = priv; 1236 dev->started++; 1237 1238 cmd_len = buf_pos - buf; 1239 dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID | 1240 HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 1241 1242 if (++dma->cmdi == HIFN_D_CMD_RSIZE) { 1243 dma->cmdr[dma->cmdi].l = __cpu_to_le32( 1244 HIFN_D_VALID | HIFN_D_LAST | 1245 HIFN_D_MASKDONEIRQ | HIFN_D_JUMP); 1246 dma->cmdi = 0; 1247 } else 1248 dma->cmdr[dma->cmdi-1].l |= __cpu_to_le32(HIFN_D_VALID); 1249 1250 if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) { 1251 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); 1252 dev->flags |= HIFN_FLAG_CMD_BUSY; 1253 } 1254 return 0; 1255 1256err_out: 1257 return -EINVAL; 1258} 1259 1260static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page, 1261 unsigned int offset, unsigned int size, int last) 1262{ 1263 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; 1264 int idx; 1265 dma_addr_t addr; 1266 1267 addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE); 1268 1269 idx = dma->srci; 1270 1271 dma->srcr[idx].p = __cpu_to_le32(addr); 1272 dma->srcr[idx].l = __cpu_to_le32(size | HIFN_D_VALID | 1273 HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0)); 1274 1275 if (++idx == HIFN_D_SRC_RSIZE) { 1276 dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID | 1277 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | 1278 (last ? HIFN_D_LAST : 0)); 1279 idx = 0; 1280 } 1281 1282 dma->srci = idx; 1283 dma->srcu++; 1284 1285 if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) { 1286 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); 1287 dev->flags |= HIFN_FLAG_SRC_BUSY; 1288 } 1289 1290 return size; 1291} 1292 1293static void hifn_setup_res_desc(struct hifn_device *dev) 1294{ 1295 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; 1296 1297 dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT | 1298 HIFN_D_VALID | HIFN_D_LAST); 1299 /* 1300 * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID | 1301 * HIFN_D_LAST); 1302 */ 1303 1304 if (++dma->resi == HIFN_D_RES_RSIZE) { 1305 dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID | 1306 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST); 1307 dma->resi = 0; 1308 } 1309 1310 dma->resu++; 1311 1312 if (!(dev->flags & HIFN_FLAG_RES_BUSY)) { 1313 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); 1314 dev->flags |= HIFN_FLAG_RES_BUSY; 1315 } 1316} 1317 1318static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page, 1319 unsigned offset, unsigned size, int last) 1320{ 1321 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; 1322 int idx; 1323 dma_addr_t addr; 1324 1325 addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE); 1326 1327 idx = dma->dsti; 1328 dma->dstr[idx].p = __cpu_to_le32(addr); 1329 dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID | 1330 HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0)); 1331 1332 if (++idx == HIFN_D_DST_RSIZE) { 1333 dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID | 1334 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | 1335 (last ? HIFN_D_LAST : 0)); 1336 idx = 0; 1337 } 1338 dma->dsti = idx; 1339 dma->dstu++; 1340 1341 if (!(dev->flags & HIFN_FLAG_DST_BUSY)) { 1342 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); 1343 dev->flags |= HIFN_FLAG_DST_BUSY; 1344 } 1345} 1346 1347static int hifn_setup_dma(struct hifn_device *dev, 1348 struct hifn_context *ctx, struct hifn_request_context *rctx, 1349 struct scatterlist *src, struct scatterlist *dst, 1350 unsigned int nbytes, void *priv) 1351{ 1352 struct scatterlist *t; 1353 struct page *spage, *dpage; 1354 unsigned int soff, doff; 1355 unsigned int n, len; 1356 1357 n = nbytes; 1358 while (n) { 1359 spage = sg_page(src); 1360 soff = src->offset; 1361 len = min(src->length, n); 1362 1363 hifn_setup_src_desc(dev, spage, soff, len, n - len == 0); 1364 1365 src++; 1366 n -= len; 1367 } 1368 1369 t = &rctx->walk.cache[0]; 1370 n = nbytes; 1371 while (n) { 1372 if (t->length && rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) { 1373 BUG_ON(!sg_page(t)); 1374 dpage = sg_page(t); 1375 doff = 0; 1376 len = t->length; 1377 } else { 1378 BUG_ON(!sg_page(dst)); 1379 dpage = sg_page(dst); 1380 doff = dst->offset; 1381 len = dst->length; 1382 } 1383 len = min(len, n); 1384 1385 hifn_setup_dst_desc(dev, dpage, doff, len, n - len == 0); 1386 1387 dst++; 1388 t++; 1389 n -= len; 1390 } 1391 1392 hifn_setup_cmd_desc(dev, ctx, rctx, priv, nbytes); 1393 hifn_setup_res_desc(dev); 1394 return 0; 1395} 1396 1397static int hifn_cipher_walk_init(struct hifn_cipher_walk *w, 1398 int num, gfp_t gfp_flags) 1399{ 1400 int i; 1401 1402 num = min(ASYNC_SCATTERLIST_CACHE, num); 1403 sg_init_table(w->cache, num); 1404 1405 w->num = 0; 1406 for (i=0; i<num; ++i) { 1407 struct page *page = alloc_page(gfp_flags); 1408 struct scatterlist *s; 1409 1410 if (!page) 1411 break; 1412 1413 s = &w->cache[i]; 1414 1415 sg_set_page(s, page, PAGE_SIZE, 0); 1416 w->num++; 1417 } 1418 1419 return i; 1420} 1421 1422static void hifn_cipher_walk_exit(struct hifn_cipher_walk *w) 1423{ 1424 int i; 1425 1426 for (i=0; i<w->num; ++i) { 1427 struct scatterlist *s = &w->cache[i]; 1428 1429 __free_page(sg_page(s)); 1430 1431 s->length = 0; 1432 } 1433 1434 w->num = 0; 1435} 1436 1437static int ablkcipher_add(unsigned int *drestp, struct scatterlist *dst, 1438 unsigned int size, unsigned int *nbytesp) 1439{ 1440 unsigned int copy, drest = *drestp, nbytes = *nbytesp; 1441 int idx = 0; 1442 1443 if (drest < size || size > nbytes) 1444 return -EINVAL; 1445 1446 while (size) { 1447 copy = min(drest, min(size, dst->length)); 1448 1449 size -= copy; 1450 drest -= copy; 1451 nbytes -= copy; 1452 1453 dprintk("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n", 1454 __func__, copy, size, drest, nbytes); 1455 1456 dst++; 1457 idx++; 1458 } 1459 1460 *nbytesp = nbytes; 1461 *drestp = drest; 1462 1463 return idx; 1464} 1465 1466static int hifn_cipher_walk(struct ablkcipher_request *req, 1467 struct hifn_cipher_walk *w) 1468{ 1469 struct scatterlist *dst, *t; 1470 unsigned int nbytes = req->nbytes, offset, copy, diff; 1471 int idx, tidx, err; 1472 1473 tidx = idx = 0; 1474 offset = 0; 1475 while (nbytes) { 1476 if (idx >= w->num && (w->flags & ASYNC_FLAGS_MISALIGNED)) 1477 return -EINVAL; 1478 1479 dst = &req->dst[idx]; 1480 1481 dprintk("\n%s: dlen: %u, doff: %u, offset: %u, nbytes: %u.\n", 1482 __func__, dst->length, dst->offset, offset, nbytes); 1483 1484 if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) || 1485 !IS_ALIGNED(dst->length, HIFN_D_DST_DALIGN) || 1486 offset) { 1487 unsigned slen = min(dst->length - offset, nbytes); 1488 unsigned dlen = PAGE_SIZE; 1489 1490 t = &w->cache[idx]; 1491 1492 err = ablkcipher_add(&dlen, dst, slen, &nbytes); 1493 if (err < 0) 1494 return err; 1495 1496 idx += err; 1497 1498 copy = slen & ~(HIFN_D_DST_DALIGN - 1); 1499 diff = slen & (HIFN_D_DST_DALIGN - 1); 1500 1501 if (dlen < nbytes) { 1502 /* 1503 * Destination page does not have enough space 1504 * to put there additional blocksized chunk, 1505 * so we mark that page as containing only 1506 * blocksize aligned chunks: 1507 * t->length = (slen & ~(HIFN_D_DST_DALIGN - 1)); 1508 * and increase number of bytes to be processed 1509 * in next chunk: 1510 * nbytes += diff; 1511 */ 1512 nbytes += diff; 1513 1514 /* 1515 * Temporary of course... 1516 * Kick author if you will catch this one. 1517 */ 1518 printk(KERN_ERR "%s: dlen: %u, nbytes: %u," 1519 "slen: %u, offset: %u.\n", 1520 __func__, dlen, nbytes, slen, offset); 1521 printk(KERN_ERR "%s: please contact author to fix this " 1522 "issue, generally you should not catch " 1523 "this path under any condition but who " 1524 "knows how did you use crypto code.\n" 1525 "Thank you.\n", __func__); 1526 BUG(); 1527 } else { 1528 copy += diff + nbytes; 1529 1530 dst = &req->dst[idx]; 1531 1532 err = ablkcipher_add(&dlen, dst, nbytes, &nbytes); 1533 if (err < 0) 1534 return err; 1535 1536 idx += err; 1537 } 1538 1539 t->length = copy; 1540 t->offset = offset; 1541 } else { 1542 nbytes -= min(dst->length, nbytes); 1543 idx++; 1544 } 1545 1546 tidx++; 1547 } 1548 1549 return tidx; 1550} 1551 1552static int hifn_setup_session(struct ablkcipher_request *req) 1553{ 1554 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); 1555 struct hifn_request_context *rctx = ablkcipher_request_ctx(req); 1556 struct hifn_device *dev = ctx->dev; 1557 unsigned long dlen, flags; 1558 unsigned int nbytes = req->nbytes, idx = 0; 1559 int err = -EINVAL, sg_num; 1560 struct scatterlist *dst; 1561 1562 if (rctx->iv && !rctx->ivsize && rctx->mode != ACRYPTO_MODE_ECB) 1563 goto err_out_exit; 1564 1565 rctx->walk.flags = 0; 1566 1567 while (nbytes) { 1568 dst = &req->dst[idx]; 1569 dlen = min(dst->length, nbytes); 1570 1571 if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) || 1572 !IS_ALIGNED(dlen, HIFN_D_DST_DALIGN)) 1573 rctx->walk.flags |= ASYNC_FLAGS_MISALIGNED; 1574 1575 nbytes -= dlen; 1576 idx++; 1577 } 1578 1579 if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) { 1580 err = hifn_cipher_walk_init(&rctx->walk, idx, GFP_ATOMIC); 1581 if (err < 0) 1582 return err; 1583 } 1584 1585 sg_num = hifn_cipher_walk(req, &rctx->walk); 1586 if (sg_num < 0) { 1587 err = sg_num; 1588 goto err_out_exit; 1589 } 1590 1591 spin_lock_irqsave(&dev->lock, flags); 1592 if (dev->started + sg_num > HIFN_QUEUE_LENGTH) { 1593 err = -EAGAIN; 1594 goto err_out; 1595 } 1596 1597 err = hifn_setup_dma(dev, ctx, rctx, req->src, req->dst, req->nbytes, req); 1598 if (err) 1599 goto err_out; 1600 1601 dev->snum++; 1602 1603 dev->active = HIFN_DEFAULT_ACTIVE_NUM; 1604 spin_unlock_irqrestore(&dev->lock, flags); 1605 1606 return 0; 1607 1608err_out: 1609 spin_unlock_irqrestore(&dev->lock, flags); 1610err_out_exit: 1611 if (err) { 1612 printk("%s: iv: %p [%d], key: %p [%d], mode: %u, op: %u, " 1613 "type: %u, err: %d.\n", 1614 dev->name, rctx->iv, rctx->ivsize, 1615 ctx->key, ctx->keysize, 1616 rctx->mode, rctx->op, rctx->type, err); 1617 } 1618 1619 return err; 1620} 1621 1622static int hifn_test(struct hifn_device *dev, int encdec, u8 snum) 1623{ 1624 int n, err; 1625 u8 src[16]; 1626 struct hifn_context ctx; 1627 struct hifn_request_context rctx; 1628 u8 fips_aes_ecb_from_zero[16] = { 1629 0x66, 0xE9, 0x4B, 0xD4, 1630 0xEF, 0x8A, 0x2C, 0x3B, 1631 0x88, 0x4C, 0xFA, 0x59, 1632 0xCA, 0x34, 0x2B, 0x2E}; 1633 struct scatterlist sg; 1634 1635 memset(src, 0, sizeof(src)); 1636 memset(ctx.key, 0, sizeof(ctx.key)); 1637 1638 ctx.dev = dev; 1639 ctx.keysize = 16; 1640 rctx.ivsize = 0; 1641 rctx.iv = NULL; 1642 rctx.op = (encdec)?ACRYPTO_OP_ENCRYPT:ACRYPTO_OP_DECRYPT; 1643 rctx.mode = ACRYPTO_MODE_ECB; 1644 rctx.type = ACRYPTO_TYPE_AES_128; 1645 rctx.walk.cache[0].length = 0; 1646 1647 sg_init_one(&sg, &src, sizeof(src)); 1648 1649 err = hifn_setup_dma(dev, &ctx, &rctx, &sg, &sg, sizeof(src), NULL); 1650 if (err) 1651 goto err_out; 1652 1653 dev->started = 0; 1654 msleep(200); 1655 1656 dprintk("%s: decoded: ", dev->name); 1657 for (n=0; n<sizeof(src); ++n) 1658 dprintk("%02x ", src[n]); 1659 dprintk("\n"); 1660 dprintk("%s: FIPS : ", dev->name); 1661 for (n=0; n<sizeof(fips_aes_ecb_from_zero); ++n) 1662 dprintk("%02x ", fips_aes_ecb_from_zero[n]); 1663 dprintk("\n"); 1664 1665 if (!memcmp(src, fips_aes_ecb_from_zero, sizeof(fips_aes_ecb_from_zero))) { 1666 printk(KERN_INFO "%s: AES 128 ECB test has been successfully " 1667 "passed.\n", dev->name); 1668 return 0; 1669 } 1670 1671err_out: 1672 printk(KERN_INFO "%s: AES 128 ECB test has been failed.\n", dev->name); 1673 return -1; 1674} 1675 1676static int hifn_start_device(struct hifn_device *dev) 1677{ 1678 int err; 1679 1680 dev->started = dev->active = 0; 1681 hifn_reset_dma(dev, 1); 1682 1683 err = hifn_enable_crypto(dev); 1684 if (err) 1685 return err; 1686 1687 hifn_reset_puc(dev); 1688 1689 hifn_init_dma(dev); 1690 1691 hifn_init_registers(dev); 1692 1693 hifn_init_pubrng(dev); 1694 1695 return 0; 1696} 1697 1698static int ablkcipher_get(void *saddr, unsigned int *srestp, unsigned int offset, 1699 struct scatterlist *dst, unsigned int size, unsigned int *nbytesp) 1700{ 1701 unsigned int srest = *srestp, nbytes = *nbytesp, copy; 1702 void *daddr; 1703 int idx = 0; 1704 1705 if (srest < size || size > nbytes) 1706 return -EINVAL; 1707 1708 while (size) { 1709 copy = min(srest, min(dst->length, size)); 1710 1711 daddr = kmap_atomic(sg_page(dst), KM_IRQ0); 1712 memcpy(daddr + dst->offset + offset, saddr, copy); 1713 kunmap_atomic(daddr, KM_IRQ0); 1714 1715 nbytes -= copy; 1716 size -= copy; 1717 srest -= copy; 1718 saddr += copy; 1719 offset = 0; 1720 1721 dprintk("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n", 1722 __func__, copy, size, srest, nbytes); 1723 1724 dst++; 1725 idx++; 1726 } 1727 1728 *nbytesp = nbytes; 1729 *srestp = srest; 1730 1731 return idx; 1732} 1733 1734static inline void hifn_complete_sa(struct hifn_device *dev, int i) 1735{ 1736 unsigned long flags; 1737 1738 spin_lock_irqsave(&dev->lock, flags); 1739 dev->sa[i] = NULL; 1740 dev->started--; 1741 if (dev->started < 0) 1742 printk("%s: started: %d.\n", __func__, dev->started); 1743 spin_unlock_irqrestore(&dev->lock, flags); 1744 BUG_ON(dev->started < 0); 1745} 1746 1747static void hifn_process_ready(struct ablkcipher_request *req, int error) 1748{ 1749 struct hifn_request_context *rctx = ablkcipher_request_ctx(req); 1750 1751 if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) { 1752 unsigned int nbytes = req->nbytes; 1753 int idx = 0, err; 1754 struct scatterlist *dst, *t; 1755 void *saddr; 1756 1757 while (nbytes) { 1758 t = &rctx->walk.cache[idx]; 1759 dst = &req->dst[idx]; 1760 1761 dprintk("\n%s: sg_page(t): %p, t->length: %u, " 1762 "sg_page(dst): %p, dst->length: %u, " 1763 "nbytes: %u.\n", 1764 __func__, sg_page(t), t->length, 1765 sg_page(dst), dst->length, nbytes); 1766 1767 if (!t->length) { 1768 nbytes -= min(dst->length, nbytes); 1769 idx++; 1770 continue; 1771 } 1772 1773 saddr = kmap_atomic(sg_page(t), KM_SOFTIRQ0); 1774 1775 err = ablkcipher_get(saddr, &t->length, t->offset, 1776 dst, nbytes, &nbytes); 1777 if (err < 0) { 1778 kunmap_atomic(saddr, KM_SOFTIRQ0); 1779 break; 1780 } 1781 1782 idx += err; 1783 kunmap_atomic(saddr, KM_SOFTIRQ0); 1784 } 1785 1786 hifn_cipher_walk_exit(&rctx->walk); 1787 } 1788 1789 req->base.complete(&req->base, error); 1790} 1791 1792static void hifn_clear_rings(struct hifn_device *dev, int error) 1793{ 1794 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; 1795 int i, u; 1796 1797 dprintk("%s: ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, " 1798 "k: %d.%d.%d.%d.\n", 1799 dev->name, 1800 dma->cmdi, dma->srci, dma->dsti, dma->resi, 1801 dma->cmdu, dma->srcu, dma->dstu, dma->resu, 1802 dma->cmdk, dma->srck, dma->dstk, dma->resk); 1803 1804 i = dma->resk; u = dma->resu; 1805 while (u != 0) { 1806 if (dma->resr[i].l & __cpu_to_le32(HIFN_D_VALID)) 1807 break; 1808 1809 if (dev->sa[i]) { 1810 dev->success++; 1811 dev->reset = 0; 1812 hifn_process_ready(dev->sa[i], error); 1813 hifn_complete_sa(dev, i); 1814 } 1815 1816 if (++i == HIFN_D_RES_RSIZE) 1817 i = 0; 1818 u--; 1819 } 1820 dma->resk = i; dma->resu = u; 1821 1822 i = dma->srck; u = dma->srcu; 1823 while (u != 0) { 1824 if (dma->srcr[i].l & __cpu_to_le32(HIFN_D_VALID)) 1825 break; 1826 if (++i == HIFN_D_SRC_RSIZE) 1827 i = 0; 1828 u--; 1829 } 1830 dma->srck = i; dma->srcu = u; 1831 1832 i = dma->cmdk; u = dma->cmdu; 1833 while (u != 0) { 1834 if (dma->cmdr[i].l & __cpu_to_le32(HIFN_D_VALID)) 1835 break; 1836 if (++i == HIFN_D_CMD_RSIZE) 1837 i = 0; 1838 u--; 1839 } 1840 dma->cmdk = i; dma->cmdu = u; 1841 1842 i = dma->dstk; u = dma->dstu; 1843 while (u != 0) { 1844 if (dma->dstr[i].l & __cpu_to_le32(HIFN_D_VALID)) 1845 break; 1846 if (++i == HIFN_D_DST_RSIZE) 1847 i = 0; 1848 u--; 1849 } 1850 dma->dstk = i; dma->dstu = u; 1851 1852 dprintk("%s: ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, " 1853 "k: %d.%d.%d.%d.\n", 1854 dev->name, 1855 dma->cmdi, dma->srci, dma->dsti, dma->resi, 1856 dma->cmdu, dma->srcu, dma->dstu, dma->resu, 1857 dma->cmdk, dma->srck, dma->dstk, dma->resk); 1858} 1859 1860static void hifn_work(struct work_struct *work) 1861{ 1862 struct delayed_work *dw = to_delayed_work(work); 1863 struct hifn_device *dev = container_of(dw, struct hifn_device, work); 1864 unsigned long flags; 1865 int reset = 0; 1866 u32 r = 0; 1867 1868 spin_lock_irqsave(&dev->lock, flags); 1869 if (dev->active == 0) { 1870 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; 1871 1872 if (dma->cmdu == 0 && (dev->flags & HIFN_FLAG_CMD_BUSY)) { 1873 dev->flags &= ~HIFN_FLAG_CMD_BUSY; 1874 r |= HIFN_DMACSR_C_CTRL_DIS; 1875 } 1876 if (dma->srcu == 0 && (dev->flags & HIFN_FLAG_SRC_BUSY)) { 1877 dev->flags &= ~HIFN_FLAG_SRC_BUSY; 1878 r |= HIFN_DMACSR_S_CTRL_DIS; 1879 } 1880 if (dma->dstu == 0 && (dev->flags & HIFN_FLAG_DST_BUSY)) { 1881 dev->flags &= ~HIFN_FLAG_DST_BUSY; 1882 r |= HIFN_DMACSR_D_CTRL_DIS; 1883 } 1884 if (dma->resu == 0 && (dev->flags & HIFN_FLAG_RES_BUSY)) { 1885 dev->flags &= ~HIFN_FLAG_RES_BUSY; 1886 r |= HIFN_DMACSR_R_CTRL_DIS; 1887 } 1888 if (r) 1889 hifn_write_1(dev, HIFN_1_DMA_CSR, r); 1890 } else 1891 dev->active--; 1892 1893 if ((dev->prev_success == dev->success) && dev->started) 1894 reset = 1; 1895 dev->prev_success = dev->success; 1896 spin_unlock_irqrestore(&dev->lock, flags); 1897 1898 if (reset) { 1899 if (++dev->reset >= 5) { 1900 int i; 1901 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; 1902 1903 printk("%s: r: %08x, active: %d, started: %d, " 1904 "success: %lu: qlen: %u/%u, reset: %d.\n", 1905 dev->name, r, dev->active, dev->started, 1906 dev->success, dev->queue.qlen, dev->queue.max_qlen, 1907 reset); 1908 1909 printk("%s: res: ", __func__); 1910 for (i=0; i<HIFN_D_RES_RSIZE; ++i) { 1911 printk("%x.%p ", dma->resr[i].l, dev->sa[i]); 1912 if (dev->sa[i]) { 1913 hifn_process_ready(dev->sa[i], -ENODEV); 1914 hifn_complete_sa(dev, i); 1915 } 1916 } 1917 printk("\n"); 1918 1919 hifn_reset_dma(dev, 1); 1920 hifn_stop_device(dev); 1921 hifn_start_device(dev); 1922 dev->reset = 0; 1923 } 1924 1925 tasklet_schedule(&dev->tasklet); 1926 } 1927 1928 schedule_delayed_work(&dev->work, HZ); 1929} 1930 1931static irqreturn_t hifn_interrupt(int irq, void *data) 1932{ 1933 struct hifn_device *dev = (struct hifn_device *)data; 1934 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; 1935 u32 dmacsr, restart; 1936 1937 dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR); 1938 1939 dprintk("%s: 1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], " 1940 "i: %d.%d.%d.%d, u: %d.%d.%d.%d.\n", 1941 dev->name, dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi, 1942 dma->cmdi, dma->srci, dma->dsti, dma->resi, 1943 dma->cmdu, dma->srcu, dma->dstu, dma->resu); 1944 1945 if ((dmacsr & dev->dmareg) == 0) 1946 return IRQ_NONE; 1947 1948 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg); 1949 1950 if (dmacsr & HIFN_DMACSR_ENGINE) 1951 hifn_write_0(dev, HIFN_0_PUISR, hifn_read_0(dev, HIFN_0_PUISR)); 1952 if (dmacsr & HIFN_DMACSR_PUBDONE) 1953 hifn_write_1(dev, HIFN_1_PUB_STATUS, 1954 hifn_read_1(dev, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 1955 1956 restart = dmacsr & (HIFN_DMACSR_R_OVER | HIFN_DMACSR_D_OVER); 1957 if (restart) { 1958 u32 puisr = hifn_read_0(dev, HIFN_0_PUISR); 1959 1960 printk(KERN_WARNING "%s: overflow: r: %d, d: %d, puisr: %08x, d: %u.\n", 1961 dev->name, !!(dmacsr & HIFN_DMACSR_R_OVER), 1962 !!(dmacsr & HIFN_DMACSR_D_OVER), 1963 puisr, !!(puisr & HIFN_PUISR_DSTOVER)); 1964 if (!!(puisr & HIFN_PUISR_DSTOVER)) 1965 hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1966 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER | 1967 HIFN_DMACSR_D_OVER)); 1968 } 1969 1970 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 1971 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 1972 if (restart) { 1973 printk(KERN_WARNING "%s: abort: c: %d, s: %d, d: %d, r: %d.\n", 1974 dev->name, !!(dmacsr & HIFN_DMACSR_C_ABORT), 1975 !!(dmacsr & HIFN_DMACSR_S_ABORT), 1976 !!(dmacsr & HIFN_DMACSR_D_ABORT), 1977 !!(dmacsr & HIFN_DMACSR_R_ABORT)); 1978 hifn_reset_dma(dev, 1); 1979 hifn_init_dma(dev); 1980 hifn_init_registers(dev); 1981 } 1982 1983 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { 1984 dprintk("%s: wait on command.\n", dev->name); 1985 dev->dmareg &= ~(HIFN_DMAIER_C_WAIT); 1986 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg); 1987 } 1988 1989 tasklet_schedule(&dev->tasklet); 1990 1991 return IRQ_HANDLED; 1992} 1993 1994static void hifn_flush(struct hifn_device *dev) 1995{ 1996 unsigned long flags; 1997 struct crypto_async_request *async_req; 1998 struct ablkcipher_request *req; 1999 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; 2000 int i; 2001 2002 for (i=0; i<HIFN_D_RES_RSIZE; ++i) { 2003 struct hifn_desc *d = &dma->resr[i]; 2004 2005 if (dev->sa[i]) { 2006 hifn_process_ready(dev->sa[i], 2007 (d->l & __cpu_to_le32(HIFN_D_VALID))?-ENODEV:0); 2008 hifn_complete_sa(dev, i); 2009 } 2010 } 2011 2012 spin_lock_irqsave(&dev->lock, flags); 2013 while ((async_req = crypto_dequeue_request(&dev->queue))) { 2014 req = container_of(async_req, struct ablkcipher_request, base); 2015 spin_unlock_irqrestore(&dev->lock, flags); 2016 2017 hifn_process_ready(req, -ENODEV); 2018 2019 spin_lock_irqsave(&dev->lock, flags); 2020 } 2021 spin_unlock_irqrestore(&dev->lock, flags); 2022} 2023 2024static int hifn_setkey(struct crypto_ablkcipher *cipher, const u8 *key, 2025 unsigned int len) 2026{ 2027 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); 2028 struct hifn_context *ctx = crypto_tfm_ctx(tfm); 2029 struct hifn_device *dev = ctx->dev; 2030 2031 if (len > HIFN_MAX_CRYPT_KEY_LENGTH) { 2032 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN); 2033 return -1; 2034 } 2035 2036 if (len == HIFN_DES_KEY_LENGTH) { 2037 u32 tmp[DES_EXPKEY_WORDS]; 2038 int ret = des_ekey(tmp, key); 2039 2040 if (unlikely(ret == 0) && (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) { 2041 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY; 2042 return -EINVAL; 2043 } 2044 } 2045 2046 dev->flags &= ~HIFN_FLAG_OLD_KEY; 2047 2048 memcpy(ctx->key, key, len); 2049 ctx->keysize = len; 2050 2051 return 0; 2052} 2053 2054static int hifn_handle_req(struct ablkcipher_request *req) 2055{ 2056 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); 2057 struct hifn_device *dev = ctx->dev; 2058 int err = -EAGAIN; 2059 2060 if (dev->started + DIV_ROUND_UP(req->nbytes, PAGE_SIZE) <= HIFN_QUEUE_LENGTH) 2061 err = hifn_setup_session(req); 2062 2063 if (err == -EAGAIN) { 2064 unsigned long flags; 2065 2066 spin_lock_irqsave(&dev->lock, flags); 2067 err = ablkcipher_enqueue_request(&dev->queue, req); 2068 spin_unlock_irqrestore(&dev->lock, flags); 2069 } 2070 2071 return err; 2072} 2073 2074static int hifn_setup_crypto_req(struct ablkcipher_request *req, u8 op, 2075 u8 type, u8 mode) 2076{ 2077 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); 2078 struct hifn_request_context *rctx = ablkcipher_request_ctx(req); 2079 unsigned ivsize; 2080 2081 ivsize = crypto_ablkcipher_ivsize(crypto_ablkcipher_reqtfm(req)); 2082 2083 if (req->info && mode != ACRYPTO_MODE_ECB) { 2084 if (type == ACRYPTO_TYPE_AES_128) 2085 ivsize = HIFN_AES_IV_LENGTH; 2086 else if (type == ACRYPTO_TYPE_DES) 2087 ivsize = HIFN_DES_KEY_LENGTH; 2088 else if (type == ACRYPTO_TYPE_3DES) 2089 ivsize = HIFN_3DES_KEY_LENGTH; 2090 } 2091 2092 if (ctx->keysize != 16 && type == ACRYPTO_TYPE_AES_128) { 2093 if (ctx->keysize == 24) 2094 type = ACRYPTO_TYPE_AES_192; 2095 else if (ctx->keysize == 32) 2096 type = ACRYPTO_TYPE_AES_256; 2097 } 2098 2099 rctx->op = op; 2100 rctx->mode = mode; 2101 rctx->type = type; 2102 rctx->iv = req->info; 2103 rctx->ivsize = ivsize; 2104 2105 /* 2106 * HEAVY TODO: needs to kick Herbert XU to write documentation. 2107 * HEAVY TODO: needs to kick Herbert XU to write documentation. 2108 * HEAVY TODO: needs to kick Herbert XU to write documentation. 2109 */ 2110 2111 return hifn_handle_req(req); 2112} 2113 2114static int hifn_process_queue(struct hifn_device *dev) 2115{ 2116 struct crypto_async_request *async_req, *backlog; 2117 struct ablkcipher_request *req; 2118 unsigned long flags; 2119 int err = 0; 2120 2121 while (dev->started < HIFN_QUEUE_LENGTH) { 2122 spin_lock_irqsave(&dev->lock, flags); 2123 backlog = crypto_get_backlog(&dev->queue); 2124 async_req = crypto_dequeue_request(&dev->queue); 2125 spin_unlock_irqrestore(&dev->lock, flags); 2126 2127 if (!async_req) 2128 break; 2129 2130 if (backlog) 2131 backlog->complete(backlog, -EINPROGRESS); 2132 2133 req = container_of(async_req, struct ablkcipher_request, base); 2134 2135 err = hifn_handle_req(req); 2136 if (err) 2137 break; 2138 } 2139 2140 return err; 2141} 2142 2143static int hifn_setup_crypto(struct ablkcipher_request *req, u8 op, 2144 u8 type, u8 mode) 2145{ 2146 int err; 2147 struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm); 2148 struct hifn_device *dev = ctx->dev; 2149 2150 err = hifn_setup_crypto_req(req, op, type, mode); 2151 if (err) 2152 return err; 2153 2154 if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen) 2155 hifn_process_queue(dev); 2156 2157 return -EINPROGRESS; 2158} 2159 2160/* 2161 * AES ecryption functions. 2162 */ 2163static inline int hifn_encrypt_aes_ecb(struct ablkcipher_request *req) 2164{ 2165 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, 2166 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB); 2167} 2168static inline int hifn_encrypt_aes_cbc(struct ablkcipher_request *req) 2169{ 2170 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, 2171 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC); 2172} 2173static inline int hifn_encrypt_aes_cfb(struct ablkcipher_request *req) 2174{ 2175 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, 2176 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB); 2177} 2178static inline int hifn_encrypt_aes_ofb(struct ablkcipher_request *req) 2179{ 2180 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, 2181 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB); 2182} 2183 2184/* 2185 * AES decryption functions. 2186 */ 2187static inline int hifn_decrypt_aes_ecb(struct ablkcipher_request *req) 2188{ 2189 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, 2190 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB); 2191} 2192static inline int hifn_decrypt_aes_cbc(struct ablkcipher_request *req) 2193{ 2194 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, 2195 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC); 2196} 2197static inline int hifn_decrypt_aes_cfb(struct ablkcipher_request *req) 2198{ 2199 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, 2200 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB); 2201} 2202static inline int hifn_decrypt_aes_ofb(struct ablkcipher_request *req) 2203{ 2204 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, 2205 ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB); 2206} 2207 2208/* 2209 * DES ecryption functions. 2210 */ 2211static inline int hifn_encrypt_des_ecb(struct ablkcipher_request *req) 2212{ 2213 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, 2214 ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB); 2215} 2216static inline int hifn_encrypt_des_cbc(struct ablkcipher_request *req) 2217{ 2218 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, 2219 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC); 2220} 2221static inline int hifn_encrypt_des_cfb(struct ablkcipher_request *req) 2222{ 2223 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, 2224 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB); 2225} 2226static inline int hifn_encrypt_des_ofb(struct ablkcipher_request *req) 2227{ 2228 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, 2229 ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB); 2230} 2231 2232/* 2233 * DES decryption functions. 2234 */ 2235static inline int hifn_decrypt_des_ecb(struct ablkcipher_request *req) 2236{ 2237 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, 2238 ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB); 2239} 2240static inline int hifn_decrypt_des_cbc(struct ablkcipher_request *req) 2241{ 2242 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, 2243 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC); 2244} 2245static inline int hifn_decrypt_des_cfb(struct ablkcipher_request *req) 2246{ 2247 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, 2248 ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB); 2249} 2250static inline int hifn_decrypt_des_ofb(struct ablkcipher_request *req) 2251{ 2252 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, 2253 ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB); 2254} 2255 2256/* 2257 * 3DES ecryption functions. 2258 */ 2259static inline int hifn_encrypt_3des_ecb(struct ablkcipher_request *req) 2260{ 2261 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, 2262 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB); 2263} 2264static inline int hifn_encrypt_3des_cbc(struct ablkcipher_request *req) 2265{ 2266 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, 2267 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC); 2268} 2269static inline int hifn_encrypt_3des_cfb(struct ablkcipher_request *req) 2270{ 2271 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, 2272 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB); 2273} 2274static inline int hifn_encrypt_3des_ofb(struct ablkcipher_request *req) 2275{ 2276 return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT, 2277 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB); 2278} 2279 2280/* 2281 * 3DES decryption functions. 2282 */ 2283static inline int hifn_decrypt_3des_ecb(struct ablkcipher_request *req) 2284{ 2285 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, 2286 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB); 2287} 2288static inline int hifn_decrypt_3des_cbc(struct ablkcipher_request *req) 2289{ 2290 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, 2291 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC); 2292} 2293static inline int hifn_decrypt_3des_cfb(struct ablkcipher_request *req) 2294{ 2295 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, 2296 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB); 2297} 2298static inline int hifn_decrypt_3des_ofb(struct ablkcipher_request *req) 2299{ 2300 return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT, 2301 ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB); 2302} 2303 2304struct hifn_alg_template 2305{ 2306 char name[CRYPTO_MAX_ALG_NAME]; 2307 char drv_name[CRYPTO_MAX_ALG_NAME]; 2308 unsigned int bsize; 2309 struct ablkcipher_alg ablkcipher; 2310}; 2311 2312static struct hifn_alg_template hifn_alg_templates[] = { 2313 /* 2314 * 3DES ECB, CBC, CFB and OFB modes. 2315 */ 2316 { 2317 .name = "cfb(des3_ede)", .drv_name = "cfb-3des", .bsize = 8, 2318 .ablkcipher = { 2319 .min_keysize = HIFN_3DES_KEY_LENGTH, 2320 .max_keysize = HIFN_3DES_KEY_LENGTH, 2321 .setkey = hifn_setkey, 2322 .encrypt = hifn_encrypt_3des_cfb, 2323 .decrypt = hifn_decrypt_3des_cfb, 2324 }, 2325 }, 2326 { 2327 .name = "ofb(des3_ede)", .drv_name = "ofb-3des", .bsize = 8, 2328 .ablkcipher = { 2329 .min_keysize = HIFN_3DES_KEY_LENGTH, 2330 .max_keysize = HIFN_3DES_KEY_LENGTH, 2331 .setkey = hifn_setkey, 2332 .encrypt = hifn_encrypt_3des_ofb, 2333 .decrypt = hifn_decrypt_3des_ofb, 2334 }, 2335 }, 2336 { 2337 .name = "cbc(des3_ede)", .drv_name = "cbc-3des", .bsize = 8, 2338 .ablkcipher = { 2339 .ivsize = HIFN_IV_LENGTH, 2340 .min_keysize = HIFN_3DES_KEY_LENGTH, 2341 .max_keysize = HIFN_3DES_KEY_LENGTH, 2342 .setkey = hifn_setkey, 2343 .encrypt = hifn_encrypt_3des_cbc, 2344 .decrypt = hifn_decrypt_3des_cbc, 2345 }, 2346 }, 2347 { 2348 .name = "ecb(des3_ede)", .drv_name = "ecb-3des", .bsize = 8, 2349 .ablkcipher = { 2350 .min_keysize = HIFN_3DES_KEY_LENGTH, 2351 .max_keysize = HIFN_3DES_KEY_LENGTH, 2352 .setkey = hifn_setkey, 2353 .encrypt = hifn_encrypt_3des_ecb, 2354 .decrypt = hifn_decrypt_3des_ecb, 2355 }, 2356 }, 2357 2358 /* 2359 * DES ECB, CBC, CFB and OFB modes. 2360 */ 2361 { 2362 .name = "cfb(des)", .drv_name = "cfb-des", .bsize = 8, 2363 .ablkcipher = { 2364 .min_keysize = HIFN_DES_KEY_LENGTH, 2365 .max_keysize = HIFN_DES_KEY_LENGTH, 2366 .setkey = hifn_setkey, 2367 .encrypt = hifn_encrypt_des_cfb, 2368 .decrypt = hifn_decrypt_des_cfb, 2369 }, 2370 }, 2371 { 2372 .name = "ofb(des)", .drv_name = "ofb-des", .bsize = 8, 2373 .ablkcipher = { 2374 .min_keysize = HIFN_DES_KEY_LENGTH, 2375 .max_keysize = HIFN_DES_KEY_LENGTH, 2376 .setkey = hifn_setkey, 2377 .encrypt = hifn_encrypt_des_ofb, 2378 .decrypt = hifn_decrypt_des_ofb, 2379 }, 2380 }, 2381 { 2382 .name = "cbc(des)", .drv_name = "cbc-des", .bsize = 8, 2383 .ablkcipher = { 2384 .ivsize = HIFN_IV_LENGTH, 2385 .min_keysize = HIFN_DES_KEY_LENGTH, 2386 .max_keysize = HIFN_DES_KEY_LENGTH, 2387 .setkey = hifn_setkey, 2388 .encrypt = hifn_encrypt_des_cbc, 2389 .decrypt = hifn_decrypt_des_cbc, 2390 }, 2391 }, 2392 { 2393 .name = "ecb(des)", .drv_name = "ecb-des", .bsize = 8, 2394 .ablkcipher = { 2395 .min_keysize = HIFN_DES_KEY_LENGTH, 2396 .max_keysize = HIFN_DES_KEY_LENGTH, 2397 .setkey = hifn_setkey, 2398 .encrypt = hifn_encrypt_des_ecb, 2399 .decrypt = hifn_decrypt_des_ecb, 2400 }, 2401 }, 2402 2403 /* 2404 * AES ECB, CBC, CFB and OFB modes. 2405 */ 2406 { 2407 .name = "ecb(aes)", .drv_name = "ecb-aes", .bsize = 16, 2408 .ablkcipher = { 2409 .min_keysize = AES_MIN_KEY_SIZE, 2410 .max_keysize = AES_MAX_KEY_SIZE, 2411 .setkey = hifn_setkey, 2412 .encrypt = hifn_encrypt_aes_ecb, 2413 .decrypt = hifn_decrypt_aes_ecb, 2414 }, 2415 }, 2416 { 2417 .name = "cbc(aes)", .drv_name = "cbc-aes", .bsize = 16, 2418 .ablkcipher = { 2419 .ivsize = HIFN_AES_IV_LENGTH, 2420 .min_keysize = AES_MIN_KEY_SIZE, 2421 .max_keysize = AES_MAX_KEY_SIZE, 2422 .setkey = hifn_setkey, 2423 .encrypt = hifn_encrypt_aes_cbc, 2424 .decrypt = hifn_decrypt_aes_cbc, 2425 }, 2426 }, 2427 { 2428 .name = "cfb(aes)", .drv_name = "cfb-aes", .bsize = 16, 2429 .ablkcipher = { 2430 .min_keysize = AES_MIN_KEY_SIZE, 2431 .max_keysize = AES_MAX_KEY_SIZE, 2432 .setkey = hifn_setkey, 2433 .encrypt = hifn_encrypt_aes_cfb, 2434 .decrypt = hifn_decrypt_aes_cfb, 2435 }, 2436 }, 2437 { 2438 .name = "ofb(aes)", .drv_name = "ofb-aes", .bsize = 16, 2439 .ablkcipher = { 2440 .min_keysize = AES_MIN_KEY_SIZE, 2441 .max_keysize = AES_MAX_KEY_SIZE, 2442 .setkey = hifn_setkey, 2443 .encrypt = hifn_encrypt_aes_ofb, 2444 .decrypt = hifn_decrypt_aes_ofb, 2445 }, 2446 }, 2447}; 2448 2449static int hifn_cra_init(struct crypto_tfm *tfm) 2450{ 2451 struct crypto_alg *alg = tfm->__crt_alg; 2452 struct hifn_crypto_alg *ha = crypto_alg_to_hifn(alg); 2453 struct hifn_context *ctx = crypto_tfm_ctx(tfm); 2454 2455 ctx->dev = ha->dev; 2456 tfm->crt_ablkcipher.reqsize = sizeof(struct hifn_request_context); 2457 return 0; 2458} 2459 2460static int hifn_alg_alloc(struct hifn_device *dev, struct hifn_alg_template *t) 2461{ 2462 struct hifn_crypto_alg *alg; 2463 int err; 2464 2465 alg = kzalloc(sizeof(struct hifn_crypto_alg), GFP_KERNEL); 2466 if (!alg) 2467 return -ENOMEM; 2468 2469 snprintf(alg->alg.cra_name, CRYPTO_MAX_ALG_NAME, "%s", t->name); 2470 snprintf(alg->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-%s", 2471 t->drv_name, dev->name); 2472 2473 alg->alg.cra_priority = 300; 2474 alg->alg.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC; 2475 alg->alg.cra_blocksize = t->bsize; 2476 alg->alg.cra_ctxsize = sizeof(struct hifn_context); 2477 alg->alg.cra_alignmask = 0; 2478 alg->alg.cra_type = &crypto_ablkcipher_type; 2479 alg->alg.cra_module = THIS_MODULE; 2480 alg->alg.cra_u.ablkcipher = t->ablkcipher; 2481 alg->alg.cra_init = hifn_cra_init; 2482 2483 alg->dev = dev; 2484 2485 list_add_tail(&alg->entry, &dev->alg_list); 2486 2487 err = crypto_register_alg(&alg->alg); 2488 if (err) { 2489 list_del(&alg->entry); 2490 kfree(alg); 2491 } 2492 2493 return err; 2494} 2495 2496static void hifn_unregister_alg(struct hifn_device *dev) 2497{ 2498 struct hifn_crypto_alg *a, *n; 2499 2500 list_for_each_entry_safe(a, n, &dev->alg_list, entry) { 2501 list_del(&a->entry); 2502 crypto_unregister_alg(&a->alg); 2503 kfree(a); 2504 } 2505} 2506 2507static int hifn_register_alg(struct hifn_device *dev) 2508{ 2509 int i, err; 2510 2511 for (i=0; i<ARRAY_SIZE(hifn_alg_templates); ++i) { 2512 err = hifn_alg_alloc(dev, &hifn_alg_templates[i]); 2513 if (err) 2514 goto err_out_exit; 2515 } 2516 2517 return 0; 2518 2519err_out_exit: 2520 hifn_unregister_alg(dev); 2521 return err; 2522} 2523 2524static void hifn_tasklet_callback(unsigned long data) 2525{ 2526 struct hifn_device *dev = (struct hifn_device *)data; 2527 2528 /* 2529 * This is ok to call this without lock being held, 2530 * althogh it modifies some parameters used in parallel, 2531 * (like dev->success), but they are used in process 2532 * context or update is atomic (like setting dev->sa[i] to NULL). 2533 */ 2534 hifn_clear_rings(dev, 0); 2535 2536 if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen) 2537 hifn_process_queue(dev); 2538} 2539 2540static int __devinit hifn_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2541{ 2542 int err, i; 2543 struct hifn_device *dev; 2544 char name[8]; 2545 2546 err = pci_enable_device(pdev); 2547 if (err) 2548 return err; 2549 pci_set_master(pdev); 2550 2551 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2552 if (err) 2553 goto err_out_disable_pci_device; 2554 2555 snprintf(name, sizeof(name), "hifn%d", 2556 atomic_inc_return(&hifn_dev_number)-1); 2557 2558 err = pci_request_regions(pdev, name); 2559 if (err) 2560 goto err_out_disable_pci_device; 2561 2562 if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE || 2563 pci_resource_len(pdev, 1) < HIFN_BAR1_SIZE || 2564 pci_resource_len(pdev, 2) < HIFN_BAR2_SIZE) { 2565 dprintk("%s: Broken hardware - I/O regions are too small.\n", 2566 pci_name(pdev)); 2567 err = -ENODEV; 2568 goto err_out_free_regions; 2569 } 2570 2571 dev = kzalloc(sizeof(struct hifn_device) + sizeof(struct crypto_alg), 2572 GFP_KERNEL); 2573 if (!dev) { 2574 err = -ENOMEM; 2575 goto err_out_free_regions; 2576 } 2577 2578 INIT_LIST_HEAD(&dev->alg_list); 2579 2580 snprintf(dev->name, sizeof(dev->name), "%s", name); 2581 spin_lock_init(&dev->lock); 2582 2583 for (i=0; i<3; ++i) { 2584 unsigned long addr, size; 2585 2586 addr = pci_resource_start(pdev, i); 2587 size = pci_resource_len(pdev, i); 2588 2589 dev->bar[i] = ioremap_nocache(addr, size); 2590 if (!dev->bar[i]) 2591 goto err_out_unmap_bars; 2592 } 2593 2594 dev->desc_virt = pci_alloc_consistent(pdev, sizeof(struct hifn_dma), 2595 &dev->desc_dma); 2596 if (!dev->desc_virt) { 2597 dprintk("Failed to allocate descriptor rings.\n"); 2598 goto err_out_unmap_bars; 2599 } 2600 memset(dev->desc_virt, 0, sizeof(struct hifn_dma)); 2601 2602 dev->pdev = pdev; 2603 dev->irq = pdev->irq; 2604 2605 for (i=0; i<HIFN_D_RES_RSIZE; ++i) 2606 dev->sa[i] = NULL; 2607 2608 pci_set_drvdata(pdev, dev); 2609 2610 tasklet_init(&dev->tasklet, hifn_tasklet_callback, (unsigned long)dev); 2611 2612 crypto_init_queue(&dev->queue, 1); 2613 2614 err = request_irq(dev->irq, hifn_interrupt, IRQF_SHARED, dev->name, dev); 2615 if (err) { 2616 dprintk("Failed to request IRQ%d: err: %d.\n", dev->irq, err); 2617 dev->irq = 0; 2618 goto err_out_free_desc; 2619 } 2620 2621 err = hifn_start_device(dev); 2622 if (err) 2623 goto err_out_free_irq; 2624 2625 err = hifn_test(dev, 1, 0); 2626 if (err) 2627 goto err_out_stop_device; 2628 2629 err = hifn_register_rng(dev); 2630 if (err) 2631 goto err_out_stop_device; 2632 2633 err = hifn_register_alg(dev); 2634 if (err) 2635 goto err_out_unregister_rng; 2636 2637 INIT_DELAYED_WORK(&dev->work, hifn_work); 2638 schedule_delayed_work(&dev->work, HZ); 2639 2640 dprintk("HIFN crypto accelerator card at %s has been " 2641 "successfully registered as %s.\n", 2642 pci_name(pdev), dev->name); 2643 2644 return 0; 2645 2646err_out_unregister_rng: 2647 hifn_unregister_rng(dev); 2648err_out_stop_device: 2649 hifn_reset_dma(dev, 1); 2650 hifn_stop_device(dev); 2651err_out_free_irq: 2652 free_irq(dev->irq, dev->name); 2653 tasklet_kill(&dev->tasklet); 2654err_out_free_desc: 2655 pci_free_consistent(pdev, sizeof(struct hifn_dma), 2656 dev->desc_virt, dev->desc_dma); 2657 2658err_out_unmap_bars: 2659 for (i=0; i<3; ++i) 2660 if (dev->bar[i]) 2661 iounmap(dev->bar[i]); 2662 2663err_out_free_regions: 2664 pci_release_regions(pdev); 2665 2666err_out_disable_pci_device: 2667 pci_disable_device(pdev); 2668 2669 return err; 2670} 2671 2672static void __devexit hifn_remove(struct pci_dev *pdev) 2673{ 2674 int i; 2675 struct hifn_device *dev; 2676 2677 dev = pci_get_drvdata(pdev); 2678 2679 if (dev) { 2680 cancel_delayed_work(&dev->work); 2681 flush_scheduled_work(); 2682 2683 hifn_unregister_rng(dev); 2684 hifn_unregister_alg(dev); 2685 hifn_reset_dma(dev, 1); 2686 hifn_stop_device(dev); 2687 2688 free_irq(dev->irq, dev->name); 2689 tasklet_kill(&dev->tasklet); 2690 2691 hifn_flush(dev); 2692 2693 pci_free_consistent(pdev, sizeof(struct hifn_dma), 2694 dev->desc_virt, dev->desc_dma); 2695 for (i=0; i<3; ++i) 2696 if (dev->bar[i]) 2697 iounmap(dev->bar[i]); 2698 2699 kfree(dev); 2700 } 2701 2702 pci_release_regions(pdev); 2703 pci_disable_device(pdev); 2704} 2705 2706static struct pci_device_id hifn_pci_tbl[] = { 2707 { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7955) }, 2708 { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7956) }, 2709 { 0 } 2710}; 2711MODULE_DEVICE_TABLE(pci, hifn_pci_tbl); 2712 2713static struct pci_driver hifn_pci_driver = { 2714 .name = "hifn795x", 2715 .id_table = hifn_pci_tbl, 2716 .probe = hifn_probe, 2717 .remove = __devexit_p(hifn_remove), 2718}; 2719 2720static int __init hifn_init(void) 2721{ 2722 unsigned int freq; 2723 int err; 2724 2725 if (sizeof(dma_addr_t) > 4) { 2726 printk(KERN_INFO "HIFN supports only 32-bit addresses.\n"); 2727 return -EINVAL; 2728 } 2729 2730 if (strncmp(hifn_pll_ref, "ext", 3) && 2731 strncmp(hifn_pll_ref, "pci", 3)) { 2732 printk(KERN_ERR "hifn795x: invalid hifn_pll_ref clock, " 2733 "must be pci or ext"); 2734 return -EINVAL; 2735 } 2736 2737 /* 2738 * For the 7955/7956 the reference clock frequency must be in the 2739 * range of 20MHz-100MHz. For the 7954 the upper bound is 66.67MHz, 2740 * but this chip is currently not supported. 2741 */ 2742 if (hifn_pll_ref[3] != '\0') { 2743 freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10); 2744 if (freq < 20 || freq > 100) { 2745 printk(KERN_ERR "hifn795x: invalid hifn_pll_ref " 2746 "frequency, must be in the range " 2747 "of 20-100"); 2748 return -EINVAL; 2749 } 2750 } 2751 2752 err = pci_register_driver(&hifn_pci_driver); 2753 if (err < 0) { 2754 dprintk("Failed to register PCI driver for %s device.\n", 2755 hifn_pci_driver.name); 2756 return -ENODEV; 2757 } 2758 2759 printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip " 2760 "has been successfully registered.\n"); 2761 2762 return 0; 2763} 2764 2765static void __exit hifn_fini(void) 2766{ 2767 pci_unregister_driver(&hifn_pci_driver); 2768 2769 printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip " 2770 "has been successfully unregistered.\n"); 2771} 2772 2773module_init(hifn_init); 2774module_exit(hifn_fini); 2775 2776MODULE_LICENSE("GPL"); 2777MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>"); 2778MODULE_DESCRIPTION("Driver for HIFN 795x crypto accelerator chip."); 2779