1/******************************************************************************* 2* 3* (c) 1998 by Computone Corporation 4* 5******************************************************************************** 6* 7* 8* PACKAGE: Linux tty Device Driver for IntelliPort family of multiport 9* serial I/O controllers. 10* 11* DESCRIPTION: Low-level interface code for the device driver 12* (This is included source code, not a separate compilation 13* module.) 14* 15*******************************************************************************/ 16//--------------------------------------------- 17// Function declarations private to this module 18//--------------------------------------------- 19// Functions called only indirectly through i2eBordStr entries. 20 21static int iiWriteBuf16(i2eBordStrPtr, unsigned char *, int); 22static int iiWriteBuf8(i2eBordStrPtr, unsigned char *, int); 23static int iiReadBuf16(i2eBordStrPtr, unsigned char *, int); 24static int iiReadBuf8(i2eBordStrPtr, unsigned char *, int); 25 26static unsigned short iiReadWord16(i2eBordStrPtr); 27static unsigned short iiReadWord8(i2eBordStrPtr); 28static void iiWriteWord16(i2eBordStrPtr, unsigned short); 29static void iiWriteWord8(i2eBordStrPtr, unsigned short); 30 31static int iiWaitForTxEmptyII(i2eBordStrPtr, int); 32static int iiWaitForTxEmptyIIEX(i2eBordStrPtr, int); 33static int iiTxMailEmptyII(i2eBordStrPtr); 34static int iiTxMailEmptyIIEX(i2eBordStrPtr); 35static int iiTrySendMailII(i2eBordStrPtr, unsigned char); 36static int iiTrySendMailIIEX(i2eBordStrPtr, unsigned char); 37 38static unsigned short iiGetMailII(i2eBordStrPtr); 39static unsigned short iiGetMailIIEX(i2eBordStrPtr); 40 41static void iiEnableMailIrqII(i2eBordStrPtr); 42static void iiEnableMailIrqIIEX(i2eBordStrPtr); 43static void iiWriteMaskII(i2eBordStrPtr, unsigned char); 44static void iiWriteMaskIIEX(i2eBordStrPtr, unsigned char); 45 46static void ii2Nop(void); 47 48//*************** 49//* Static Data * 50//*************** 51 52static int ii2Safe; // Safe I/O address for delay routine 53 54static int iiDelayed; // Set when the iiResetDelay function is 55 // called. Cleared when ANY board is reset. 56static DEFINE_RWLOCK(Dl_spinlock); 57 58//******** 59//* Code * 60//******** 61 62//======================================================= 63// Initialization Routines 64// 65// iiSetAddress 66// iiReset 67// iiResetDelay 68// iiInitialize 69//======================================================= 70 71//****************************************************************************** 72// Function: iiSetAddress(pB, address, delay) 73// Parameters: pB - pointer to the board structure 74// address - the purported I/O address of the board 75// delay - pointer to the 1-ms delay function to use 76// in this and any future operations to this board 77// 78// Returns: True if everything appears copacetic. 79// False if there is any error: the pB->i2eError field has the error 80// 81// Description: 82// 83// This routine (roughly) checks for address validity, sets the i2eValid OK and 84// sets the state to II_STATE_COLD which means that we haven't even sent a reset 85// yet. 86// 87//****************************************************************************** 88static int 89iiSetAddress( i2eBordStrPtr pB, int address, delayFunc_t delay ) 90{ 91 // Should any failure occur before init is finished... 92 pB->i2eValid = I2E_INCOMPLETE; 93 94 // Cannot check upper limit except extremely: Might be microchannel 95 // Address must be on an 8-byte boundary 96 97 if ((unsigned int)address <= 0x100 98 || (unsigned int)address >= 0xfff8 99 || (address & 0x7) 100 ) 101 { 102 I2_COMPLETE(pB, I2EE_BADADDR); 103 } 104 105 // Initialize accelerators 106 pB->i2eBase = address; 107 pB->i2eData = address + FIFO_DATA; 108 pB->i2eStatus = address + FIFO_STATUS; 109 pB->i2ePointer = address + FIFO_PTR; 110 pB->i2eXMail = address + FIFO_MAIL; 111 pB->i2eXMask = address + FIFO_MASK; 112 113 // Initialize i/o address for ii2DelayIO 114 ii2Safe = address + FIFO_NOP; 115 116 // Initialize the delay routine 117 pB->i2eDelay = ((delay != (delayFunc_t)NULL) ? delay : (delayFunc_t)ii2Nop); 118 119 pB->i2eValid = I2E_MAGIC; 120 pB->i2eState = II_STATE_COLD; 121 122 I2_COMPLETE(pB, I2EE_GOOD); 123} 124 125//****************************************************************************** 126// Function: iiReset(pB) 127// Parameters: pB - pointer to the board structure 128// 129// Returns: True if everything appears copacetic. 130// False if there is any error: the pB->i2eError field has the error 131// 132// Description: 133// 134// Attempts to reset the board (see also i2hw.h). Normally, we would use this to 135// reset a board immediately after iiSetAddress(), but it is valid to reset a 136// board from any state, say, in order to change or re-load loadware. (Under 137// such circumstances, no reason to re-run iiSetAddress(), which is why it is a 138// separate routine and not included in this routine. 139// 140//****************************************************************************** 141static int 142iiReset(i2eBordStrPtr pB) 143{ 144 // Magic number should be set, else even the address is suspect 145 if (pB->i2eValid != I2E_MAGIC) 146 { 147 I2_COMPLETE(pB, I2EE_BADMAGIC); 148 } 149 150 outb(0, pB->i2eBase + FIFO_RESET); /* Any data will do */ 151 iiDelay(pB, 50); // Pause between resets 152 outb(0, pB->i2eBase + FIFO_RESET); /* Second reset */ 153 154 // We must wait before even attempting to read anything from the FIFO: the 155 // board's P.O.S.T may actually attempt to read and write its end of the 156 // FIFO in order to check flags, loop back (where supported), etc. On 157 // completion of this testing it would reset the FIFO, and on completion 158 // of all // P.O.S.T., write the message. We must not mistake data which 159 // might have been sent for testing as part of the reset message. To 160 // better utilize time, say, when resetting several boards, we allow the 161 // delay to be performed externally; in this way the caller can reset 162 // several boards, delay a single time, then call the initialization 163 // routine for all. 164 165 pB->i2eState = II_STATE_RESET; 166 167 iiDelayed = 0; // i.e., the delay routine hasn't been called since the most 168 // recent reset. 169 170 // Ensure anything which would have been of use to standard loadware is 171 // blanked out, since board has now forgotten everything!. 172 173 pB->i2eUsingIrq = I2_IRQ_UNDEFINED; /* to not use an interrupt so far */ 174 pB->i2eWaitingForEmptyFifo = 0; 175 pB->i2eOutMailWaiting = 0; 176 pB->i2eChannelPtr = NULL; 177 pB->i2eChannelCnt = 0; 178 179 pB->i2eLeadoffWord[0] = 0; 180 pB->i2eFifoInInts = 0; 181 pB->i2eFifoOutInts = 0; 182 pB->i2eFatalTrap = NULL; 183 pB->i2eFatal = 0; 184 185 I2_COMPLETE(pB, I2EE_GOOD); 186} 187 188//****************************************************************************** 189// Function: iiResetDelay(pB) 190// Parameters: pB - pointer to the board structure 191// 192// Returns: True if everything appears copacetic. 193// False if there is any error: the pB->i2eError field has the error 194// 195// Description: 196// 197// Using the delay defined in board structure, waits two seconds (for board to 198// reset). 199// 200//****************************************************************************** 201static int 202iiResetDelay(i2eBordStrPtr pB) 203{ 204 if (pB->i2eValid != I2E_MAGIC) { 205 I2_COMPLETE(pB, I2EE_BADMAGIC); 206 } 207 if (pB->i2eState != II_STATE_RESET) { 208 I2_COMPLETE(pB, I2EE_BADSTATE); 209 } 210 iiDelay(pB,2000); /* Now we wait for two seconds. */ 211 iiDelayed = 1; /* Delay has been called: ok to initialize */ 212 I2_COMPLETE(pB, I2EE_GOOD); 213} 214 215//****************************************************************************** 216// Function: iiInitialize(pB) 217// Parameters: pB - pointer to the board structure 218// 219// Returns: True if everything appears copacetic. 220// False if there is any error: the pB->i2eError field has the error 221// 222// Description: 223// 224// Attempts to read the Power-on reset message. Initializes any remaining fields 225// in the pB structure. 226// 227// This should be called as the third step of a process beginning with 228// iiReset(), then iiResetDelay(). This routine checks to see that the structure 229// is "valid" and in the reset state, also confirms that the delay routine has 230// been called since the latest reset (to any board! overly strong!). 231// 232//****************************************************************************** 233static int 234iiInitialize(i2eBordStrPtr pB) 235{ 236 int itemp; 237 unsigned char c; 238 unsigned short utemp; 239 unsigned int ilimit; 240 241 if (pB->i2eValid != I2E_MAGIC) 242 { 243 I2_COMPLETE(pB, I2EE_BADMAGIC); 244 } 245 246 if (pB->i2eState != II_STATE_RESET || !iiDelayed) 247 { 248 I2_COMPLETE(pB, I2EE_BADSTATE); 249 } 250 251 // In case there is a failure short of our completely reading the power-up 252 // message. 253 pB->i2eValid = I2E_INCOMPLETE; 254 255 256 // Now attempt to read the message. 257 258 for (itemp = 0; itemp < sizeof(porStr); itemp++) 259 { 260 // We expect the entire message is ready. 261 if (!I2_HAS_INPUT(pB)) { 262 pB->i2ePomSize = itemp; 263 I2_COMPLETE(pB, I2EE_PORM_SHORT); 264 } 265 266 pB->i2ePom.c[itemp] = c = inb(pB->i2eData); 267 268 // We check the magic numbers as soon as they are supposed to be read 269 // (rather than after) to minimize effect of reading something we 270 // already suspect can't be "us". 271 if ( (itemp == POR_1_INDEX && c != POR_MAGIC_1) || 272 (itemp == POR_2_INDEX && c != POR_MAGIC_2)) 273 { 274 pB->i2ePomSize = itemp+1; 275 I2_COMPLETE(pB, I2EE_BADMAGIC); 276 } 277 } 278 279 pB->i2ePomSize = itemp; 280 281 // Ensure that this was all the data... 282 if (I2_HAS_INPUT(pB)) 283 I2_COMPLETE(pB, I2EE_PORM_LONG); 284 285 // For now, we'll fail to initialize if P.O.S.T reports bad chip mapper: 286 // Implying we will not be able to download any code either: That's ok: the 287 // condition is pretty explicit. 288 if (pB->i2ePom.e.porDiag1 & POR_BAD_MAPPER) 289 { 290 I2_COMPLETE(pB, I2EE_POSTERR); 291 } 292 293 // Determine anything which must be done differently depending on the family 294 // of boards! 295 switch (pB->i2ePom.e.porID & POR_ID_FAMILY) 296 { 297 case POR_ID_FII: // IntelliPort-II 298 299 pB->i2eFifoStyle = FIFO_II; 300 pB->i2eFifoSize = 512; // 512 bytes, always 301 pB->i2eDataWidth16 = false; 302 303 pB->i2eMaxIrq = 15; // Because board cannot tell us it is in an 8-bit 304 // slot, we do allow it to be done (documentation!) 305 306 pB->i2eGoodMap[1] = 307 pB->i2eGoodMap[2] = 308 pB->i2eGoodMap[3] = 309 pB->i2eChannelMap[1] = 310 pB->i2eChannelMap[2] = 311 pB->i2eChannelMap[3] = 0; 312 313 switch (pB->i2ePom.e.porID & POR_ID_SIZE) 314 { 315 case POR_ID_II_4: 316 pB->i2eGoodMap[0] = 317 pB->i2eChannelMap[0] = 0x0f; // four-port 318 319 // Since porPorts1 is based on the Hardware ID register, the numbers 320 // should always be consistent for IntelliPort-II. Ditto below... 321 if (pB->i2ePom.e.porPorts1 != 4) 322 { 323 I2_COMPLETE(pB, I2EE_INCONSIST); 324 } 325 break; 326 327 case POR_ID_II_8: 328 case POR_ID_II_8R: 329 pB->i2eGoodMap[0] = 330 pB->i2eChannelMap[0] = 0xff; // Eight port 331 if (pB->i2ePom.e.porPorts1 != 8) 332 { 333 I2_COMPLETE(pB, I2EE_INCONSIST); 334 } 335 break; 336 337 case POR_ID_II_6: 338 pB->i2eGoodMap[0] = 339 pB->i2eChannelMap[0] = 0x3f; // Six Port 340 if (pB->i2ePom.e.porPorts1 != 6) 341 { 342 I2_COMPLETE(pB, I2EE_INCONSIST); 343 } 344 break; 345 } 346 347 // Fix up the "good channel list based on any errors reported. 348 if (pB->i2ePom.e.porDiag1 & POR_BAD_UART1) 349 { 350 pB->i2eGoodMap[0] &= ~0x0f; 351 } 352 353 if (pB->i2ePom.e.porDiag1 & POR_BAD_UART2) 354 { 355 pB->i2eGoodMap[0] &= ~0xf0; 356 } 357 358 break; // POR_ID_FII case 359 360 case POR_ID_FIIEX: // IntelliPort-IIEX 361 362 pB->i2eFifoStyle = FIFO_IIEX; 363 364 itemp = pB->i2ePom.e.porFifoSize; 365 366 // Implicit assumption that fifo would not grow beyond 32k, 367 // nor would ever be less than 256. 368 369 if (itemp < 8 || itemp > 15) 370 { 371 I2_COMPLETE(pB, I2EE_INCONSIST); 372 } 373 pB->i2eFifoSize = (1 << itemp); 374 375 // These are based on what P.O.S.T thinks should be there, based on 376 // box ID registers 377 ilimit = pB->i2ePom.e.porNumBoxes; 378 if (ilimit > ABS_MAX_BOXES) 379 { 380 ilimit = ABS_MAX_BOXES; 381 } 382 383 // For as many boxes as EXIST, gives the type of box. 384 // Added 8/6/93: check for the ISA-4 (asic) which looks like an 385 // expandable but for whom "8 or 16?" is not the right question. 386 387 utemp = pB->i2ePom.e.porFlags; 388 if (utemp & POR_CEX4) 389 { 390 pB->i2eChannelMap[0] = 0x000f; 391 } else { 392 utemp &= POR_BOXES; 393 for (itemp = 0; itemp < ilimit; itemp++) 394 { 395 pB->i2eChannelMap[itemp] = 396 ((utemp & POR_BOX_16) ? 0xffff : 0x00ff); 397 utemp >>= 1; 398 } 399 } 400 401 // These are based on what P.O.S.T actually found. 402 403 utemp = (pB->i2ePom.e.porPorts2 << 8) + pB->i2ePom.e.porPorts1; 404 405 for (itemp = 0; itemp < ilimit; itemp++) 406 { 407 pB->i2eGoodMap[itemp] = 0; 408 if (utemp & 1) pB->i2eGoodMap[itemp] |= 0x000f; 409 if (utemp & 2) pB->i2eGoodMap[itemp] |= 0x00f0; 410 if (utemp & 4) pB->i2eGoodMap[itemp] |= 0x0f00; 411 if (utemp & 8) pB->i2eGoodMap[itemp] |= 0xf000; 412 utemp >>= 4; 413 } 414 415 // Now determine whether we should transfer in 8 or 16-bit mode. 416 switch (pB->i2ePom.e.porBus & (POR_BUS_SLOT16 | POR_BUS_DIP16) ) 417 { 418 case POR_BUS_SLOT16 | POR_BUS_DIP16: 419 pB->i2eDataWidth16 = true; 420 pB->i2eMaxIrq = 15; 421 break; 422 423 case POR_BUS_SLOT16: 424 pB->i2eDataWidth16 = false; 425 pB->i2eMaxIrq = 15; 426 break; 427 428 case 0: 429 case POR_BUS_DIP16: // In an 8-bit slot, DIP switch don't care. 430 default: 431 pB->i2eDataWidth16 = false; 432 pB->i2eMaxIrq = 7; 433 break; 434 } 435 break; // POR_ID_FIIEX case 436 437 default: // Unknown type of board 438 I2_COMPLETE(pB, I2EE_BAD_FAMILY); 439 break; 440 } // End the switch based on family 441 442 // Temporarily, claim there is no room in the outbound fifo. 443 // We will maintain this whenever we check for an empty outbound FIFO. 444 pB->i2eFifoRemains = 0; 445 446 // Now, based on the bus type, should we expect to be able to re-configure 447 // interrupts (say, for testing purposes). 448 switch (pB->i2ePom.e.porBus & POR_BUS_TYPE) 449 { 450 case POR_BUS_T_ISA: 451 case POR_BUS_T_UNK: // If the type of bus is undeclared, assume ok. 452 case POR_BUS_T_MCA: 453 case POR_BUS_T_EISA: 454 break; 455 default: 456 I2_COMPLETE(pB, I2EE_BADBUS); 457 } 458 459 if (pB->i2eDataWidth16) 460 { 461 pB->i2eWriteBuf = iiWriteBuf16; 462 pB->i2eReadBuf = iiReadBuf16; 463 pB->i2eWriteWord = iiWriteWord16; 464 pB->i2eReadWord = iiReadWord16; 465 } else { 466 pB->i2eWriteBuf = iiWriteBuf8; 467 pB->i2eReadBuf = iiReadBuf8; 468 pB->i2eWriteWord = iiWriteWord8; 469 pB->i2eReadWord = iiReadWord8; 470 } 471 472 switch(pB->i2eFifoStyle) 473 { 474 case FIFO_II: 475 pB->i2eWaitForTxEmpty = iiWaitForTxEmptyII; 476 pB->i2eTxMailEmpty = iiTxMailEmptyII; 477 pB->i2eTrySendMail = iiTrySendMailII; 478 pB->i2eGetMail = iiGetMailII; 479 pB->i2eEnableMailIrq = iiEnableMailIrqII; 480 pB->i2eWriteMask = iiWriteMaskII; 481 482 break; 483 484 case FIFO_IIEX: 485 pB->i2eWaitForTxEmpty = iiWaitForTxEmptyIIEX; 486 pB->i2eTxMailEmpty = iiTxMailEmptyIIEX; 487 pB->i2eTrySendMail = iiTrySendMailIIEX; 488 pB->i2eGetMail = iiGetMailIIEX; 489 pB->i2eEnableMailIrq = iiEnableMailIrqIIEX; 490 pB->i2eWriteMask = iiWriteMaskIIEX; 491 492 break; 493 494 default: 495 I2_COMPLETE(pB, I2EE_INCONSIST); 496 } 497 498 // Initialize state information. 499 pB->i2eState = II_STATE_READY; // Ready to load loadware. 500 501 // Some Final cleanup: 502 // For some boards, the bootstrap firmware may perform some sort of test 503 // resulting in a stray character pending in the incoming mailbox. If one is 504 // there, it should be read and discarded, especially since for the standard 505 // firmware, it's the mailbox that interrupts the host. 506 507 pB->i2eStartMail = iiGetMail(pB); 508 509 // Throw it away and clear the mailbox structure element 510 pB->i2eStartMail = NO_MAIL_HERE; 511 512 // Everything is ok now, return with good status/ 513 514 pB->i2eValid = I2E_MAGIC; 515 I2_COMPLETE(pB, I2EE_GOOD); 516} 517 518//****************************************************************************** 519// Function: ii2DelayTimer(mseconds) 520// Parameters: mseconds - number of milliseconds to delay 521// 522// Returns: Nothing 523// 524// Description: 525// 526// This routine delays for approximately mseconds milliseconds and is intended 527// to be called indirectly through i2Delay field in i2eBordStr. It uses the 528// Linux timer_list mechanism. 529// 530// The Linux timers use a unit called "jiffies" which are 10mS in the Intel 531// architecture. This function rounds the delay period up to the next "jiffy". 532// In the Alpha architecture the "jiffy" is 1mS, but this driver is not intended 533// for Alpha platforms at this time. 534// 535//****************************************************************************** 536static void 537ii2DelayTimer(unsigned int mseconds) 538{ 539 msleep_interruptible(mseconds); 540} 541 542 543//****************************************************************************** 544// Function: ii2Nop() 545// Parameters: None 546// 547// Returns: Nothing 548// 549// Description: 550// 551// iiInitialize will set i2eDelay to this if the delay parameter is NULL. This 552// saves checking for a NULL pointer at every call. 553//****************************************************************************** 554static void 555ii2Nop(void) 556{ 557 return; // no mystery here 558} 559 560//======================================================= 561// Routines which are available in 8/16-bit versions, or 562// in different fifo styles. These are ALL called 563// indirectly through the board structure. 564//======================================================= 565 566//****************************************************************************** 567// Function: iiWriteBuf16(pB, address, count) 568// Parameters: pB - pointer to board structure 569// address - address of data to write 570// count - number of data bytes to write 571// 572// Returns: True if everything appears copacetic. 573// False if there is any error: the pB->i2eError field has the error 574// 575// Description: 576// 577// Writes 'count' bytes from 'address' to the data fifo specified by the board 578// structure pointer pB. Should count happen to be odd, an extra pad byte is 579// sent (identity unknown...). Uses 16-bit (word) operations. Is called 580// indirectly through pB->i2eWriteBuf. 581// 582//****************************************************************************** 583static int 584iiWriteBuf16(i2eBordStrPtr pB, unsigned char *address, int count) 585{ 586 // Rudimentary sanity checking here. 587 if (pB->i2eValid != I2E_MAGIC) 588 I2_COMPLETE(pB, I2EE_INVALID); 589 590 I2_OUTSW(pB->i2eData, address, count); 591 592 I2_COMPLETE(pB, I2EE_GOOD); 593} 594 595//****************************************************************************** 596// Function: iiWriteBuf8(pB, address, count) 597// Parameters: pB - pointer to board structure 598// address - address of data to write 599// count - number of data bytes to write 600// 601// Returns: True if everything appears copacetic. 602// False if there is any error: the pB->i2eError field has the error 603// 604// Description: 605// 606// Writes 'count' bytes from 'address' to the data fifo specified by the board 607// structure pointer pB. Should count happen to be odd, an extra pad byte is 608// sent (identity unknown...). This is to be consistent with the 16-bit version. 609// Uses 8-bit (byte) operations. Is called indirectly through pB->i2eWriteBuf. 610// 611//****************************************************************************** 612static int 613iiWriteBuf8(i2eBordStrPtr pB, unsigned char *address, int count) 614{ 615 /* Rudimentary sanity checking here */ 616 if (pB->i2eValid != I2E_MAGIC) 617 I2_COMPLETE(pB, I2EE_INVALID); 618 619 I2_OUTSB(pB->i2eData, address, count); 620 621 I2_COMPLETE(pB, I2EE_GOOD); 622} 623 624//****************************************************************************** 625// Function: iiReadBuf16(pB, address, count) 626// Parameters: pB - pointer to board structure 627// address - address to put data read 628// count - number of data bytes to read 629// 630// Returns: True if everything appears copacetic. 631// False if there is any error: the pB->i2eError field has the error 632// 633// Description: 634// 635// Reads 'count' bytes into 'address' from the data fifo specified by the board 636// structure pointer pB. Should count happen to be odd, an extra pad byte is 637// received (identity unknown...). Uses 16-bit (word) operations. Is called 638// indirectly through pB->i2eReadBuf. 639// 640//****************************************************************************** 641static int 642iiReadBuf16(i2eBordStrPtr pB, unsigned char *address, int count) 643{ 644 // Rudimentary sanity checking here. 645 if (pB->i2eValid != I2E_MAGIC) 646 I2_COMPLETE(pB, I2EE_INVALID); 647 648 I2_INSW(pB->i2eData, address, count); 649 650 I2_COMPLETE(pB, I2EE_GOOD); 651} 652 653//****************************************************************************** 654// Function: iiReadBuf8(pB, address, count) 655// Parameters: pB - pointer to board structure 656// address - address to put data read 657// count - number of data bytes to read 658// 659// Returns: True if everything appears copacetic. 660// False if there is any error: the pB->i2eError field has the error 661// 662// Description: 663// 664// Reads 'count' bytes into 'address' from the data fifo specified by the board 665// structure pointer pB. Should count happen to be odd, an extra pad byte is 666// received (identity unknown...). This to match the 16-bit behaviour. Uses 667// 8-bit (byte) operations. Is called indirectly through pB->i2eReadBuf. 668// 669//****************************************************************************** 670static int 671iiReadBuf8(i2eBordStrPtr pB, unsigned char *address, int count) 672{ 673 // Rudimentary sanity checking here. 674 if (pB->i2eValid != I2E_MAGIC) 675 I2_COMPLETE(pB, I2EE_INVALID); 676 677 I2_INSB(pB->i2eData, address, count); 678 679 I2_COMPLETE(pB, I2EE_GOOD); 680} 681 682//****************************************************************************** 683// Function: iiReadWord16(pB) 684// Parameters: pB - pointer to board structure 685// 686// Returns: True if everything appears copacetic. 687// False if there is any error: the pB->i2eError field has the error 688// 689// Description: 690// 691// Returns the word read from the data fifo specified by the board-structure 692// pointer pB. Uses a 16-bit operation. Is called indirectly through 693// pB->i2eReadWord. 694// 695//****************************************************************************** 696static unsigned short 697iiReadWord16(i2eBordStrPtr pB) 698{ 699 return inw(pB->i2eData); 700} 701 702//****************************************************************************** 703// Function: iiReadWord8(pB) 704// Parameters: pB - pointer to board structure 705// 706// Returns: True if everything appears copacetic. 707// False if there is any error: the pB->i2eError field has the error 708// 709// Description: 710// 711// Returns the word read from the data fifo specified by the board-structure 712// pointer pB. Uses two 8-bit operations. Bytes are assumed to be LSB first. Is 713// called indirectly through pB->i2eReadWord. 714// 715//****************************************************************************** 716static unsigned short 717iiReadWord8(i2eBordStrPtr pB) 718{ 719 unsigned short urs; 720 721 urs = inb(pB->i2eData); 722 723 return (inb(pB->i2eData) << 8) | urs; 724} 725 726//****************************************************************************** 727// Function: iiWriteWord16(pB, value) 728// Parameters: pB - pointer to board structure 729// value - data to write 730// 731// Returns: True if everything appears copacetic. 732// False if there is any error: the pB->i2eError field has the error 733// 734// Description: 735// 736// Writes the word 'value' to the data fifo specified by the board-structure 737// pointer pB. Uses 16-bit operation. Is called indirectly through 738// pB->i2eWriteWord. 739// 740//****************************************************************************** 741static void 742iiWriteWord16(i2eBordStrPtr pB, unsigned short value) 743{ 744 outw((int)value, pB->i2eData); 745} 746 747//****************************************************************************** 748// Function: iiWriteWord8(pB, value) 749// Parameters: pB - pointer to board structure 750// value - data to write 751// 752// Returns: True if everything appears copacetic. 753// False if there is any error: the pB->i2eError field has the error 754// 755// Description: 756// 757// Writes the word 'value' to the data fifo specified by the board-structure 758// pointer pB. Uses two 8-bit operations (writes LSB first). Is called 759// indirectly through pB->i2eWriteWord. 760// 761//****************************************************************************** 762static void 763iiWriteWord8(i2eBordStrPtr pB, unsigned short value) 764{ 765 outb((char)value, pB->i2eData); 766 outb((char)(value >> 8), pB->i2eData); 767} 768 769//****************************************************************************** 770// Function: iiWaitForTxEmptyII(pB, mSdelay) 771// Parameters: pB - pointer to board structure 772// mSdelay - period to wait before returning 773// 774// Returns: True if the FIFO is empty. 775// False if it not empty in the required time: the pB->i2eError 776// field has the error. 777// 778// Description: 779// 780// Waits up to "mSdelay" milliseconds for the outgoing FIFO to become empty; if 781// not empty by the required time, returns false and error in pB->i2eError, 782// otherwise returns true. 783// 784// mSdelay == 0 is taken to mean must be empty on the first test. 785// 786// This version operates on IntelliPort-II - style FIFO's 787// 788// Note this routine is organized so that if status is ok there is no delay at 789// all called either before or after the test. Is called indirectly through 790// pB->i2eWaitForTxEmpty. 791// 792//****************************************************************************** 793static int 794iiWaitForTxEmptyII(i2eBordStrPtr pB, int mSdelay) 795{ 796 unsigned long flags; 797 int itemp; 798 799 for (;;) 800 { 801 // This routine hinges on being able to see the "other" status register 802 // (as seen by the local processor). His incoming fifo is our outgoing 803 // FIFO. 804 // 805 // By the nature of this routine, you would be using this as part of a 806 // larger atomic context: i.e., you would use this routine to ensure the 807 // fifo empty, then act on this information. Between these two halves, 808 // you will generally not want to service interrupts or in any way 809 // disrupt the assumptions implicit in the larger context. 810 // 811 // Even worse, however, this routine "shifts" the status register to 812 // point to the local status register which is not the usual situation. 813 // Therefore for extra safety, we force the critical section to be 814 // completely atomic, and pick up after ourselves before allowing any 815 // interrupts of any kind. 816 817 818 write_lock_irqsave(&Dl_spinlock, flags); 819 outb(SEL_COMMAND, pB->i2ePointer); 820 outb(SEL_CMD_SH, pB->i2ePointer); 821 822 itemp = inb(pB->i2eStatus); 823 824 outb(SEL_COMMAND, pB->i2ePointer); 825 outb(SEL_CMD_UNSH, pB->i2ePointer); 826 827 if (itemp & ST_IN_EMPTY) 828 { 829 I2_UPDATE_FIFO_ROOM(pB); 830 write_unlock_irqrestore(&Dl_spinlock, flags); 831 I2_COMPLETE(pB, I2EE_GOOD); 832 } 833 834 write_unlock_irqrestore(&Dl_spinlock, flags); 835 836 if (mSdelay-- == 0) 837 break; 838 839 iiDelay(pB, 1); /* 1 mS granularity on checking condition */ 840 } 841 I2_COMPLETE(pB, I2EE_TXE_TIME); 842} 843 844//****************************************************************************** 845// Function: iiWaitForTxEmptyIIEX(pB, mSdelay) 846// Parameters: pB - pointer to board structure 847// mSdelay - period to wait before returning 848// 849// Returns: True if the FIFO is empty. 850// False if it not empty in the required time: the pB->i2eError 851// field has the error. 852// 853// Description: 854// 855// Waits up to "mSdelay" milliseconds for the outgoing FIFO to become empty; if 856// not empty by the required time, returns false and error in pB->i2eError, 857// otherwise returns true. 858// 859// mSdelay == 0 is taken to mean must be empty on the first test. 860// 861// This version operates on IntelliPort-IIEX - style FIFO's 862// 863// Note this routine is organized so that if status is ok there is no delay at 864// all called either before or after the test. Is called indirectly through 865// pB->i2eWaitForTxEmpty. 866// 867//****************************************************************************** 868static int 869iiWaitForTxEmptyIIEX(i2eBordStrPtr pB, int mSdelay) 870{ 871 unsigned long flags; 872 873 for (;;) 874 { 875 // By the nature of this routine, you would be using this as part of a 876 // larger atomic context: i.e., you would use this routine to ensure the 877 // fifo empty, then act on this information. Between these two halves, 878 // you will generally not want to service interrupts or in any way 879 // disrupt the assumptions implicit in the larger context. 880 881 write_lock_irqsave(&Dl_spinlock, flags); 882 883 if (inb(pB->i2eStatus) & STE_OUT_MT) { 884 I2_UPDATE_FIFO_ROOM(pB); 885 write_unlock_irqrestore(&Dl_spinlock, flags); 886 I2_COMPLETE(pB, I2EE_GOOD); 887 } 888 write_unlock_irqrestore(&Dl_spinlock, flags); 889 890 if (mSdelay-- == 0) 891 break; 892 893 iiDelay(pB, 1); // 1 mS granularity on checking condition 894 } 895 I2_COMPLETE(pB, I2EE_TXE_TIME); 896} 897 898//****************************************************************************** 899// Function: iiTxMailEmptyII(pB) 900// Parameters: pB - pointer to board structure 901// 902// Returns: True if the transmit mailbox is empty. 903// False if it not empty. 904// 905// Description: 906// 907// Returns true or false according to whether the transmit mailbox is empty (and 908// therefore able to accept more mail) 909// 910// This version operates on IntelliPort-II - style FIFO's 911// 912//****************************************************************************** 913static int 914iiTxMailEmptyII(i2eBordStrPtr pB) 915{ 916 int port = pB->i2ePointer; 917 outb(SEL_OUTMAIL, port); 918 return inb(port) == 0; 919} 920 921//****************************************************************************** 922// Function: iiTxMailEmptyIIEX(pB) 923// Parameters: pB - pointer to board structure 924// 925// Returns: True if the transmit mailbox is empty. 926// False if it not empty. 927// 928// Description: 929// 930// Returns true or false according to whether the transmit mailbox is empty (and 931// therefore able to accept more mail) 932// 933// This version operates on IntelliPort-IIEX - style FIFO's 934// 935//****************************************************************************** 936static int 937iiTxMailEmptyIIEX(i2eBordStrPtr pB) 938{ 939 return !(inb(pB->i2eStatus) & STE_OUT_MAIL); 940} 941 942//****************************************************************************** 943// Function: iiTrySendMailII(pB,mail) 944// Parameters: pB - pointer to board structure 945// mail - value to write to mailbox 946// 947// Returns: True if the transmit mailbox is empty, and mail is sent. 948// False if it not empty. 949// 950// Description: 951// 952// If outgoing mailbox is empty, sends mail and returns true. If outgoing 953// mailbox is not empty, returns false. 954// 955// This version operates on IntelliPort-II - style FIFO's 956// 957//****************************************************************************** 958static int 959iiTrySendMailII(i2eBordStrPtr pB, unsigned char mail) 960{ 961 int port = pB->i2ePointer; 962 963 outb(SEL_OUTMAIL, port); 964 if (inb(port) == 0) { 965 outb(SEL_OUTMAIL, port); 966 outb(mail, port); 967 return 1; 968 } 969 return 0; 970} 971 972//****************************************************************************** 973// Function: iiTrySendMailIIEX(pB,mail) 974// Parameters: pB - pointer to board structure 975// mail - value to write to mailbox 976// 977// Returns: True if the transmit mailbox is empty, and mail is sent. 978// False if it not empty. 979// 980// Description: 981// 982// If outgoing mailbox is empty, sends mail and returns true. If outgoing 983// mailbox is not empty, returns false. 984// 985// This version operates on IntelliPort-IIEX - style FIFO's 986// 987//****************************************************************************** 988static int 989iiTrySendMailIIEX(i2eBordStrPtr pB, unsigned char mail) 990{ 991 if (inb(pB->i2eStatus) & STE_OUT_MAIL) 992 return 0; 993 outb(mail, pB->i2eXMail); 994 return 1; 995} 996 997//****************************************************************************** 998// Function: iiGetMailII(pB,mail) 999// Parameters: pB - pointer to board structure 1000// 1001// Returns: Mailbox data or NO_MAIL_HERE. 1002// 1003// Description: 1004// 1005// If no mail available, returns NO_MAIL_HERE otherwise returns the data from 1006// the mailbox, which is guaranteed != NO_MAIL_HERE. 1007// 1008// This version operates on IntelliPort-II - style FIFO's 1009// 1010//****************************************************************************** 1011static unsigned short 1012iiGetMailII(i2eBordStrPtr pB) 1013{ 1014 if (I2_HAS_MAIL(pB)) { 1015 outb(SEL_INMAIL, pB->i2ePointer); 1016 return inb(pB->i2ePointer); 1017 } else { 1018 return NO_MAIL_HERE; 1019 } 1020} 1021 1022//****************************************************************************** 1023// Function: iiGetMailIIEX(pB,mail) 1024// Parameters: pB - pointer to board structure 1025// 1026// Returns: Mailbox data or NO_MAIL_HERE. 1027// 1028// Description: 1029// 1030// If no mail available, returns NO_MAIL_HERE otherwise returns the data from 1031// the mailbox, which is guaranteed != NO_MAIL_HERE. 1032// 1033// This version operates on IntelliPort-IIEX - style FIFO's 1034// 1035//****************************************************************************** 1036static unsigned short 1037iiGetMailIIEX(i2eBordStrPtr pB) 1038{ 1039 if (I2_HAS_MAIL(pB)) 1040 return inb(pB->i2eXMail); 1041 else 1042 return NO_MAIL_HERE; 1043} 1044 1045//****************************************************************************** 1046// Function: iiEnableMailIrqII(pB) 1047// Parameters: pB - pointer to board structure 1048// 1049// Returns: Nothing 1050// 1051// Description: 1052// 1053// Enables board to interrupt host (only) by writing to host's in-bound mailbox. 1054// 1055// This version operates on IntelliPort-II - style FIFO's 1056// 1057//****************************************************************************** 1058static void 1059iiEnableMailIrqII(i2eBordStrPtr pB) 1060{ 1061 outb(SEL_MASK, pB->i2ePointer); 1062 outb(ST_IN_MAIL, pB->i2ePointer); 1063} 1064 1065//****************************************************************************** 1066// Function: iiEnableMailIrqIIEX(pB) 1067// Parameters: pB - pointer to board structure 1068// 1069// Returns: Nothing 1070// 1071// Description: 1072// 1073// Enables board to interrupt host (only) by writing to host's in-bound mailbox. 1074// 1075// This version operates on IntelliPort-IIEX - style FIFO's 1076// 1077//****************************************************************************** 1078static void 1079iiEnableMailIrqIIEX(i2eBordStrPtr pB) 1080{ 1081 outb(MX_IN_MAIL, pB->i2eXMask); 1082} 1083 1084//****************************************************************************** 1085// Function: iiWriteMaskII(pB) 1086// Parameters: pB - pointer to board structure 1087// 1088// Returns: Nothing 1089// 1090// Description: 1091// 1092// Writes arbitrary value to the mask register. 1093// 1094// This version operates on IntelliPort-II - style FIFO's 1095// 1096//****************************************************************************** 1097static void 1098iiWriteMaskII(i2eBordStrPtr pB, unsigned char value) 1099{ 1100 outb(SEL_MASK, pB->i2ePointer); 1101 outb(value, pB->i2ePointer); 1102} 1103 1104//****************************************************************************** 1105// Function: iiWriteMaskIIEX(pB) 1106// Parameters: pB - pointer to board structure 1107// 1108// Returns: Nothing 1109// 1110// Description: 1111// 1112// Writes arbitrary value to the mask register. 1113// 1114// This version operates on IntelliPort-IIEX - style FIFO's 1115// 1116//****************************************************************************** 1117static void 1118iiWriteMaskIIEX(i2eBordStrPtr pB, unsigned char value) 1119{ 1120 outb(value, pB->i2eXMask); 1121} 1122 1123//****************************************************************************** 1124// Function: iiDownloadBlock(pB, pSource, isStandard) 1125// Parameters: pB - pointer to board structure 1126// pSource - loadware block to download 1127// isStandard - True if "standard" loadware, else false. 1128// 1129// Returns: Success or Failure 1130// 1131// Description: 1132// 1133// Downloads a single block (at pSource)to the board referenced by pB. Caller 1134// sets isStandard to true/false according to whether the "standard" loadware is 1135// what's being loaded. The normal process, then, is to perform an iiInitialize 1136// to the board, then perform some number of iiDownloadBlocks using the returned 1137// state to determine when download is complete. 1138// 1139// Possible return values: (see I2ELLIS.H) 1140// II_DOWN_BADVALID 1141// II_DOWN_BADFILE 1142// II_DOWN_CONTINUING 1143// II_DOWN_GOOD 1144// II_DOWN_BAD 1145// II_DOWN_BADSTATE 1146// II_DOWN_TIMEOUT 1147// 1148// Uses the i2eState and i2eToLoad fields (initialized at iiInitialize) to 1149// determine whether this is the first block, whether to check for magic 1150// numbers, how many blocks there are to go... 1151// 1152//****************************************************************************** 1153static int 1154iiDownloadBlock ( i2eBordStrPtr pB, loadHdrStrPtr pSource, int isStandard) 1155{ 1156 int itemp; 1157 int loadedFirst; 1158 1159 if (pB->i2eValid != I2E_MAGIC) return II_DOWN_BADVALID; 1160 1161 switch(pB->i2eState) 1162 { 1163 case II_STATE_READY: 1164 1165 // Loading the first block after reset. Must check the magic number of the 1166 // loadfile, store the number of blocks we expect to load. 1167 if (pSource->e.loadMagic != MAGIC_LOADFILE) 1168 { 1169 return II_DOWN_BADFILE; 1170 } 1171 1172 // Next we store the total number of blocks to load, including this one. 1173 pB->i2eToLoad = 1 + pSource->e.loadBlocksMore; 1174 1175 // Set the state, store the version numbers. ('Cause this may have come 1176 // from a file - we might want to report these versions and revisions in 1177 // case of an error! 1178 pB->i2eState = II_STATE_LOADING; 1179 pB->i2eLVersion = pSource->e.loadVersion; 1180 pB->i2eLRevision = pSource->e.loadRevision; 1181 pB->i2eLSub = pSource->e.loadSubRevision; 1182 1183 // The time and date of compilation is also available but don't bother 1184 // storing it for normal purposes. 1185 loadedFirst = 1; 1186 break; 1187 1188 case II_STATE_LOADING: 1189 loadedFirst = 0; 1190 break; 1191 1192 default: 1193 return II_DOWN_BADSTATE; 1194 } 1195 1196 // Now we must be in the II_STATE_LOADING state, and we assume i2eToLoad 1197 // must be positive still, because otherwise we would have cleaned up last 1198 // time and set the state to II_STATE_LOADED. 1199 if (!iiWaitForTxEmpty(pB, MAX_DLOAD_READ_TIME)) { 1200 return II_DOWN_TIMEOUT; 1201 } 1202 1203 if (!iiWriteBuf(pB, pSource->c, LOADWARE_BLOCK_SIZE)) { 1204 return II_DOWN_BADVALID; 1205 } 1206 1207 // If we just loaded the first block, wait for the fifo to empty an extra 1208 // long time to allow for any special startup code in the firmware, like 1209 // sending status messages to the LCD's. 1210 1211 if (loadedFirst) { 1212 if (!iiWaitForTxEmpty(pB, MAX_DLOAD_START_TIME)) { 1213 return II_DOWN_TIMEOUT; 1214 } 1215 } 1216 1217 // Determine whether this was our last block! 1218 if (--(pB->i2eToLoad)) { 1219 return II_DOWN_CONTINUING; // more to come... 1220 } 1221 1222 // It WAS our last block: Clean up operations... 1223 // ...Wait for last buffer to drain from the board... 1224 if (!iiWaitForTxEmpty(pB, MAX_DLOAD_READ_TIME)) { 1225 return II_DOWN_TIMEOUT; 1226 } 1227 // If there were only a single block written, this would come back 1228 // immediately and be harmless, though not strictly necessary. 1229 itemp = MAX_DLOAD_ACK_TIME/10; 1230 while (--itemp) { 1231 if (I2_HAS_INPUT(pB)) { 1232 switch (inb(pB->i2eData)) { 1233 case LOADWARE_OK: 1234 pB->i2eState = 1235 isStandard ? II_STATE_STDLOADED :II_STATE_LOADED; 1236 1237 // Some revisions of the bootstrap firmware (e.g. ISA-8 1.0.2) 1238 // will, // if there is a debug port attached, require some 1239 // time to send information to the debug port now. It will do 1240 // this before // executing any of the code we just downloaded. 1241 // It may take up to 700 milliseconds. 1242 if (pB->i2ePom.e.porDiag2 & POR_DEBUG_PORT) { 1243 iiDelay(pB, 700); 1244 } 1245 1246 return II_DOWN_GOOD; 1247 1248 case LOADWARE_BAD: 1249 default: 1250 return II_DOWN_BAD; 1251 } 1252 } 1253 1254 iiDelay(pB, 10); // 10 mS granularity on checking condition 1255 } 1256 1257 // Drop-through --> timed out waiting for firmware confirmation 1258 1259 pB->i2eState = II_STATE_BADLOAD; 1260 return II_DOWN_TIMEOUT; 1261} 1262 1263//****************************************************************************** 1264// Function: iiDownloadAll(pB, pSource, isStandard, size) 1265// Parameters: pB - pointer to board structure 1266// pSource - loadware block to download 1267// isStandard - True if "standard" loadware, else false. 1268// size - size of data to download (in bytes) 1269// 1270// Returns: Success or Failure 1271// 1272// Description: 1273// 1274// Given a pointer to a board structure, a pointer to the beginning of some 1275// loadware, whether it is considered the "standard loadware", and the size of 1276// the array in bytes loads the entire array to the board as loadware. 1277// 1278// Assumes the board has been freshly reset and the power-up reset message read. 1279// (i.e., in II_STATE_READY). Complains if state is bad, or if there seems to be 1280// too much or too little data to load, or if iiDownloadBlock complains. 1281//****************************************************************************** 1282static int 1283iiDownloadAll(i2eBordStrPtr pB, loadHdrStrPtr pSource, int isStandard, int size) 1284{ 1285 int status; 1286 1287 // We know (from context) board should be ready for the first block of 1288 // download. Complain if not. 1289 if (pB->i2eState != II_STATE_READY) return II_DOWN_BADSTATE; 1290 1291 while (size > 0) { 1292 size -= LOADWARE_BLOCK_SIZE; // How much data should there be left to 1293 // load after the following operation ? 1294 1295 // Note we just bump pSource by "one", because its size is actually that 1296 // of an entire block, same as LOADWARE_BLOCK_SIZE. 1297 status = iiDownloadBlock(pB, pSource++, isStandard); 1298 1299 switch(status) 1300 { 1301 case II_DOWN_GOOD: 1302 return ( (size > 0) ? II_DOWN_OVER : II_DOWN_GOOD); 1303 1304 case II_DOWN_CONTINUING: 1305 break; 1306 1307 default: 1308 return status; 1309 } 1310 } 1311 1312 // We shouldn't drop out: it means "while" caught us with nothing left to 1313 // download, yet the previous DownloadBlock did not return complete. Ergo, 1314 // not enough data to match the size byte in the header. 1315 return II_DOWN_UNDER; 1316} 1317