1/* 2 * pata_sis.c - SiS ATA driver 3 * 4 * (C) 2005 Red Hat 5 * (C) 2007,2009 Bartlomiej Zolnierkiewicz 6 * 7 * Based upon linux/drivers/ide/pci/sis5513.c 8 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> 9 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer 10 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> 11 * SiS Taiwan : for direct support and hardware. 12 * Daniela Engert : for initial ATA100 advices and numerous others. 13 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : 14 * for checking code correctness, providing patches. 15 * Original tests and design on the SiS620 chipset. 16 * ATA100 tests and design on the SiS735 chipset. 17 * ATA16/33 support from specs 18 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> 19 * 20 * 21 * TODO 22 * Check MWDMA on drives that don't support MWDMA speed pio cycles ? 23 * More Testing 24 */ 25 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/pci.h> 29#include <linux/init.h> 30#include <linux/blkdev.h> 31#include <linux/delay.h> 32#include <linux/device.h> 33#include <scsi/scsi_host.h> 34#include <linux/libata.h> 35#include <linux/ata.h> 36#include "sis.h" 37 38#define DRV_NAME "pata_sis" 39#define DRV_VERSION "0.5.2" 40 41struct sis_chipset { 42 u16 device; /* PCI host ID */ 43 const struct ata_port_info *info; /* Info block */ 44 /* Probably add family, cable detect type etc here to clean 45 up code later */ 46}; 47 48struct sis_laptop { 49 u16 device; 50 u16 subvendor; 51 u16 subdevice; 52}; 53 54static const struct sis_laptop sis_laptop[] = { 55 /* devid, subvendor, subdev */ 56 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ 57 { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ 58 { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ 59 /* end marker */ 60 { 0, } 61}; 62 63static int sis_short_ata40(struct pci_dev *dev) 64{ 65 const struct sis_laptop *lap = &sis_laptop[0]; 66 67 while (lap->device) { 68 if (lap->device == dev->device && 69 lap->subvendor == dev->subsystem_vendor && 70 lap->subdevice == dev->subsystem_device) 71 return 1; 72 lap++; 73 } 74 75 return 0; 76} 77 78/** 79 * sis_old_port_base - return PCI configuration base for dev 80 * @adev: device 81 * 82 * Returns the base of the PCI configuration registers for this port 83 * number. 84 */ 85 86static int sis_old_port_base(struct ata_device *adev) 87{ 88 return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); 89} 90 91/** 92 * sis_133_cable_detect - check for 40/80 pin 93 * @ap: Port 94 * @deadline: deadline jiffies for the operation 95 * 96 * Perform cable detection for the later UDMA133 capable 97 * SiS chipset. 98 */ 99 100static int sis_133_cable_detect(struct ata_port *ap) 101{ 102 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 103 u16 tmp; 104 105 /* The top bit of this register is the cable detect bit */ 106 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); 107 if ((tmp & 0x8000) && !sis_short_ata40(pdev)) 108 return ATA_CBL_PATA40; 109 return ATA_CBL_PATA80; 110} 111 112/** 113 * sis_66_cable_detect - check for 40/80 pin 114 * @ap: Port 115 * 116 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 117 * SiS IDE controllers. 118 */ 119 120static int sis_66_cable_detect(struct ata_port *ap) 121{ 122 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 123 u8 tmp; 124 125 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ 126 pci_read_config_byte(pdev, 0x48, &tmp); 127 tmp >>= ap->port_no; 128 if ((tmp & 0x10) && !sis_short_ata40(pdev)) 129 return ATA_CBL_PATA40; 130 return ATA_CBL_PATA80; 131} 132 133 134/** 135 * sis_pre_reset - probe begin 136 * @link: ATA link 137 * @deadline: deadline jiffies for the operation 138 * 139 * Set up cable type and use generic probe init 140 */ 141 142static int sis_pre_reset(struct ata_link *link, unsigned long deadline) 143{ 144 static const struct pci_bits sis_enable_bits[] = { 145 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ 146 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ 147 }; 148 149 struct ata_port *ap = link->ap; 150 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 151 152 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) 153 return -ENOENT; 154 155 /* Clear the FIFO settings. We can't enable the FIFO until 156 we know we are poking at a disk */ 157 pci_write_config_byte(pdev, 0x4B, 0); 158 return ata_sff_prereset(link, deadline); 159} 160 161 162/** 163 * sis_set_fifo - Set RWP fifo bits for this device 164 * @ap: Port 165 * @adev: Device 166 * 167 * SIS chipsets implement prefetch/postwrite bits for each device 168 * on both channels. This functionality is not ATAPI compatible and 169 * must be configured according to the class of device present 170 */ 171 172static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) 173{ 174 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 175 u8 fifoctrl; 176 u8 mask = 0x11; 177 178 mask <<= (2 * ap->port_no); 179 mask <<= adev->devno; 180 181 /* This holds various bits including the FIFO control */ 182 pci_read_config_byte(pdev, 0x4B, &fifoctrl); 183 fifoctrl &= ~mask; 184 185 /* Enable for ATA (disk) only */ 186 if (adev->class == ATA_DEV_ATA) 187 fifoctrl |= mask; 188 pci_write_config_byte(pdev, 0x4B, fifoctrl); 189} 190 191/** 192 * sis_old_set_piomode - Initialize host controller PATA PIO timings 193 * @ap: Port whose timings we are configuring 194 * @adev: Device we are configuring for. 195 * 196 * Set PIO mode for device, in host controller PCI config space. This 197 * function handles PIO set up for all chips that are pre ATA100 and 198 * also early ATA100 devices. 199 * 200 * LOCKING: 201 * None (inherited from caller). 202 */ 203 204static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) 205{ 206 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 207 int port = sis_old_port_base(adev); 208 u8 t1, t2; 209 int speed = adev->pio_mode - XFER_PIO_0; 210 211 const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; 212 const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; 213 214 sis_set_fifo(ap, adev); 215 216 pci_read_config_byte(pdev, port, &t1); 217 pci_read_config_byte(pdev, port + 1, &t2); 218 219 t1 &= ~0x0F; /* Clear active/recovery timings */ 220 t2 &= ~0x07; 221 222 t1 |= active[speed]; 223 t2 |= recovery[speed]; 224 225 pci_write_config_byte(pdev, port, t1); 226 pci_write_config_byte(pdev, port + 1, t2); 227} 228 229/** 230 * sis_100_set_piomode - Initialize host controller PATA PIO timings 231 * @ap: Port whose timings we are configuring 232 * @adev: Device we are configuring for. 233 * 234 * Set PIO mode for device, in host controller PCI config space. This 235 * function handles PIO set up for ATA100 devices and early ATA133. 236 * 237 * LOCKING: 238 * None (inherited from caller). 239 */ 240 241static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) 242{ 243 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 244 int port = sis_old_port_base(adev); 245 int speed = adev->pio_mode - XFER_PIO_0; 246 247 const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; 248 249 sis_set_fifo(ap, adev); 250 251 pci_write_config_byte(pdev, port, actrec[speed]); 252} 253 254/** 255 * sis_133_set_piomode - Initialize host controller PATA PIO timings 256 * @ap: Port whose timings we are configuring 257 * @adev: Device we are configuring for. 258 * 259 * Set PIO mode for device, in host controller PCI config space. This 260 * function handles PIO set up for the later ATA133 devices. 261 * 262 * LOCKING: 263 * None (inherited from caller). 264 */ 265 266static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) 267{ 268 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 269 int port = 0x40; 270 u32 t1; 271 u32 reg54; 272 int speed = adev->pio_mode - XFER_PIO_0; 273 274 const u32 timing133[] = { 275 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 276 0x0C266000, 277 0x04263000, 278 0x0C0A3000, 279 0x05093000 280 }; 281 const u32 timing100[] = { 282 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 283 0x091C4000, 284 0x031C2000, 285 0x09072000, 286 0x04062000 287 }; 288 289 sis_set_fifo(ap, adev); 290 291 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ 292 pci_read_config_dword(pdev, 0x54, ®54); 293 if (reg54 & 0x40000000) 294 port = 0x70; 295 port += 8 * ap->port_no + 4 * adev->devno; 296 297 pci_read_config_dword(pdev, port, &t1); 298 t1 &= 0xC0C00FFF; /* Mask out timing */ 299 300 if (t1 & 0x08) /* 100 or 133 ? */ 301 t1 |= timing133[speed]; 302 else 303 t1 |= timing100[speed]; 304 pci_write_config_byte(pdev, port, t1); 305} 306 307/** 308 * sis_old_set_dmamode - Initialize host controller PATA DMA timings 309 * @ap: Port whose timings we are configuring 310 * @adev: Device to program 311 * 312 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 313 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike 314 * the old ide/pci driver. 315 * 316 * LOCKING: 317 * None (inherited from caller). 318 */ 319 320static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) 321{ 322 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 323 int speed = adev->dma_mode - XFER_MW_DMA_0; 324 int drive_pci = sis_old_port_base(adev); 325 u16 timing; 326 327 const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; 328 const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; 329 330 pci_read_config_word(pdev, drive_pci, &timing); 331 332 if (adev->dma_mode < XFER_UDMA_0) { 333 /* bits 3-0 hold recovery timing bits 8-10 active timing and 334 the higher bits are dependant on the device */ 335 timing &= ~0x870F; 336 timing |= mwdma_bits[speed]; 337 } else { 338 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ 339 speed = adev->dma_mode - XFER_UDMA_0; 340 timing &= ~0x6000; 341 timing |= udma_bits[speed]; 342 } 343 pci_write_config_word(pdev, drive_pci, timing); 344} 345 346/** 347 * sis_66_set_dmamode - Initialize host controller PATA DMA timings 348 * @ap: Port whose timings we are configuring 349 * @adev: Device to program 350 * 351 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 352 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike 353 * the old ide/pci driver. 354 * 355 * LOCKING: 356 * None (inherited from caller). 357 */ 358 359static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) 360{ 361 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 362 int speed = adev->dma_mode - XFER_MW_DMA_0; 363 int drive_pci = sis_old_port_base(adev); 364 u16 timing; 365 366 /* MWDMA 0-2 and UDMA 0-5 */ 367 const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; 368 const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 }; 369 370 pci_read_config_word(pdev, drive_pci, &timing); 371 372 if (adev->dma_mode < XFER_UDMA_0) { 373 /* bits 3-0 hold recovery timing bits 8-10 active timing and 374 the higher bits are dependant on the device, bit 15 udma */ 375 timing &= ~0x870F; 376 timing |= mwdma_bits[speed]; 377 } else { 378 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ 379 speed = adev->dma_mode - XFER_UDMA_0; 380 timing &= ~0xF000; 381 timing |= udma_bits[speed]; 382 } 383 pci_write_config_word(pdev, drive_pci, timing); 384} 385 386/** 387 * sis_100_set_dmamode - Initialize host controller PATA DMA timings 388 * @ap: Port whose timings we are configuring 389 * @adev: Device to program 390 * 391 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 392 * Handles UDMA66 and early UDMA100 devices. 393 * 394 * LOCKING: 395 * None (inherited from caller). 396 */ 397 398static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) 399{ 400 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 401 int speed = adev->dma_mode - XFER_MW_DMA_0; 402 int drive_pci = sis_old_port_base(adev); 403 u8 timing; 404 405 const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81}; 406 407 pci_read_config_byte(pdev, drive_pci + 1, &timing); 408 409 if (adev->dma_mode < XFER_UDMA_0) { 410 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 411 } else { 412 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 413 speed = adev->dma_mode - XFER_UDMA_0; 414 timing &= ~0x8F; 415 timing |= udma_bits[speed]; 416 } 417 pci_write_config_byte(pdev, drive_pci + 1, timing); 418} 419 420/** 421 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings 422 * @ap: Port whose timings we are configuring 423 * @adev: Device to program 424 * 425 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 426 * Handles early SiS 961 bridges. 427 * 428 * LOCKING: 429 * None (inherited from caller). 430 */ 431 432static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) 433{ 434 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 435 int speed = adev->dma_mode - XFER_MW_DMA_0; 436 int drive_pci = sis_old_port_base(adev); 437 u8 timing; 438 /* Low 4 bits are timing */ 439 static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81}; 440 441 pci_read_config_byte(pdev, drive_pci + 1, &timing); 442 443 if (adev->dma_mode < XFER_UDMA_0) { 444 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 445 } else { 446 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 447 speed = adev->dma_mode - XFER_UDMA_0; 448 timing &= ~0x8F; 449 timing |= udma_bits[speed]; 450 } 451 pci_write_config_byte(pdev, drive_pci + 1, timing); 452} 453 454/** 455 * sis_133_set_dmamode - Initialize host controller PATA DMA timings 456 * @ap: Port whose timings we are configuring 457 * @adev: Device to program 458 * 459 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 460 * 461 * LOCKING: 462 * None (inherited from caller). 463 */ 464 465static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) 466{ 467 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 468 int speed = adev->dma_mode - XFER_MW_DMA_0; 469 int port = 0x40; 470 u32 t1; 471 u32 reg54; 472 473 /* bits 4- cycle time 8 - cvs time */ 474 static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; 475 static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; 476 477 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ 478 pci_read_config_dword(pdev, 0x54, ®54); 479 if (reg54 & 0x40000000) 480 port = 0x70; 481 port += (8 * ap->port_no) + (4 * adev->devno); 482 483 pci_read_config_dword(pdev, port, &t1); 484 485 if (adev->dma_mode < XFER_UDMA_0) { 486 t1 &= ~0x00000004; 487 } else { 488 speed = adev->dma_mode - XFER_UDMA_0; 489 /* if & 8 no UDMA133 - need info for ... */ 490 t1 &= ~0x00000FF0; 491 t1 |= 0x00000004; 492 if (t1 & 0x08) 493 t1 |= timing_u133[speed]; 494 else 495 t1 |= timing_u100[speed]; 496 } 497 pci_write_config_dword(pdev, port, t1); 498} 499 500static struct scsi_host_template sis_sht = { 501 ATA_BMDMA_SHT(DRV_NAME), 502}; 503 504static struct ata_port_operations sis_133_for_sata_ops = { 505 .inherits = &ata_bmdma_port_ops, 506 .set_piomode = sis_133_set_piomode, 507 .set_dmamode = sis_133_set_dmamode, 508 .cable_detect = sis_133_cable_detect, 509}; 510 511static struct ata_port_operations sis_base_ops = { 512 .inherits = &ata_bmdma_port_ops, 513 .prereset = sis_pre_reset, 514}; 515 516static struct ata_port_operations sis_133_ops = { 517 .inherits = &sis_base_ops, 518 .set_piomode = sis_133_set_piomode, 519 .set_dmamode = sis_133_set_dmamode, 520 .cable_detect = sis_133_cable_detect, 521}; 522 523static struct ata_port_operations sis_133_early_ops = { 524 .inherits = &sis_base_ops, 525 .set_piomode = sis_100_set_piomode, 526 .set_dmamode = sis_133_early_set_dmamode, 527 .cable_detect = sis_66_cable_detect, 528}; 529 530static struct ata_port_operations sis_100_ops = { 531 .inherits = &sis_base_ops, 532 .set_piomode = sis_100_set_piomode, 533 .set_dmamode = sis_100_set_dmamode, 534 .cable_detect = sis_66_cable_detect, 535}; 536 537static struct ata_port_operations sis_66_ops = { 538 .inherits = &sis_base_ops, 539 .set_piomode = sis_old_set_piomode, 540 .set_dmamode = sis_66_set_dmamode, 541 .cable_detect = sis_66_cable_detect, 542}; 543 544static struct ata_port_operations sis_old_ops = { 545 .inherits = &sis_base_ops, 546 .set_piomode = sis_old_set_piomode, 547 .set_dmamode = sis_old_set_dmamode, 548 .cable_detect = ata_cable_40wire, 549}; 550 551static const struct ata_port_info sis_info = { 552 .flags = ATA_FLAG_SLAVE_POSS, 553 .pio_mask = ATA_PIO4, 554 .mwdma_mask = ATA_MWDMA2, 555 /* No UDMA */ 556 .port_ops = &sis_old_ops, 557}; 558static const struct ata_port_info sis_info33 = { 559 .flags = ATA_FLAG_SLAVE_POSS, 560 .pio_mask = ATA_PIO4, 561 .mwdma_mask = ATA_MWDMA2, 562 .udma_mask = ATA_UDMA2, 563 .port_ops = &sis_old_ops, 564}; 565static const struct ata_port_info sis_info66 = { 566 .flags = ATA_FLAG_SLAVE_POSS, 567 .pio_mask = ATA_PIO4, 568 /* No MWDMA */ 569 .udma_mask = ATA_UDMA4, 570 .port_ops = &sis_66_ops, 571}; 572static const struct ata_port_info sis_info100 = { 573 .flags = ATA_FLAG_SLAVE_POSS, 574 .pio_mask = ATA_PIO4, 575 /* No MWDMA */ 576 .udma_mask = ATA_UDMA5, 577 .port_ops = &sis_100_ops, 578}; 579static const struct ata_port_info sis_info100_early = { 580 .flags = ATA_FLAG_SLAVE_POSS, 581 .pio_mask = ATA_PIO4, 582 /* No MWDMA */ 583 .udma_mask = ATA_UDMA5, 584 .port_ops = &sis_66_ops, 585}; 586static const struct ata_port_info sis_info133 = { 587 .flags = ATA_FLAG_SLAVE_POSS, 588 .pio_mask = ATA_PIO4, 589 /* No MWDMA */ 590 .udma_mask = ATA_UDMA6, 591 .port_ops = &sis_133_ops, 592}; 593const struct ata_port_info sis_info133_for_sata = { 594 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 595 .pio_mask = ATA_PIO4, 596 /* No MWDMA */ 597 .udma_mask = ATA_UDMA6, 598 .port_ops = &sis_133_for_sata_ops, 599}; 600static const struct ata_port_info sis_info133_early = { 601 .flags = ATA_FLAG_SLAVE_POSS, 602 .pio_mask = ATA_PIO4, 603 /* No MWDMA */ 604 .udma_mask = ATA_UDMA6, 605 .port_ops = &sis_133_early_ops, 606}; 607 608/* Privately shared with the SiS180 SATA driver, not for use elsewhere */ 609EXPORT_SYMBOL_GPL(sis_info133_for_sata); 610 611static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) 612{ 613 u16 regw; 614 u8 reg; 615 616 if (sis->info == &sis_info133) { 617 pci_read_config_word(pdev, 0x50, ®w); 618 if (regw & 0x08) 619 pci_write_config_word(pdev, 0x50, regw & ~0x08); 620 pci_read_config_word(pdev, 0x52, ®w); 621 if (regw & 0x08) 622 pci_write_config_word(pdev, 0x52, regw & ~0x08); 623 return; 624 } 625 626 if (sis->info == &sis_info133_early || sis->info == &sis_info100) { 627 /* Fix up latency */ 628 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 629 /* Set compatibility bit */ 630 pci_read_config_byte(pdev, 0x49, ®); 631 if (!(reg & 0x01)) 632 pci_write_config_byte(pdev, 0x49, reg | 0x01); 633 return; 634 } 635 636 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { 637 /* Fix up latency */ 638 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 639 /* Set compatibility bit */ 640 pci_read_config_byte(pdev, 0x52, ®); 641 if (!(reg & 0x04)) 642 pci_write_config_byte(pdev, 0x52, reg | 0x04); 643 return; 644 } 645 646 if (sis->info == &sis_info33) { 647 pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); 648 if (( reg & 0x0F ) != 0x00) 649 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); 650 /* Fall through to ATA16 fixup below */ 651 } 652 653 if (sis->info == &sis_info || sis->info == &sis_info33) { 654 /* force per drive recovery and active timings 655 needed on ATA_33 and below chips */ 656 pci_read_config_byte(pdev, 0x52, ®); 657 if (!(reg & 0x08)) 658 pci_write_config_byte(pdev, 0x52, reg|0x08); 659 return; 660 } 661 662 BUG(); 663} 664 665/** 666 * sis_init_one - Register SiS ATA PCI device with kernel services 667 * @pdev: PCI device to register 668 * @ent: Entry in sis_pci_tbl matching with @pdev 669 * 670 * Called from kernel PCI layer. We probe for combined mode (sigh), 671 * and then hand over control to libata, for it to do the rest. 672 * 673 * LOCKING: 674 * Inherited from PCI layer (may sleep). 675 * 676 * RETURNS: 677 * Zero on success, or -ERRNO value. 678 */ 679 680static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 681{ 682 static int printed_version; 683 const struct ata_port_info *ppi[] = { NULL, NULL }; 684 struct pci_dev *host = NULL; 685 struct sis_chipset *chipset = NULL; 686 struct sis_chipset *sets; 687 int rc; 688 689 static struct sis_chipset sis_chipsets[] = { 690 691 { 0x0968, &sis_info133 }, 692 { 0x0966, &sis_info133 }, 693 { 0x0965, &sis_info133 }, 694 { 0x0745, &sis_info100 }, 695 { 0x0735, &sis_info100 }, 696 { 0x0733, &sis_info100 }, 697 { 0x0635, &sis_info100 }, 698 { 0x0633, &sis_info100 }, 699 700 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ 701 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ 702 703 { 0x0640, &sis_info66 }, 704 { 0x0630, &sis_info66 }, 705 { 0x0620, &sis_info66 }, 706 { 0x0540, &sis_info66 }, 707 { 0x0530, &sis_info66 }, 708 709 { 0x5600, &sis_info33 }, 710 { 0x5598, &sis_info33 }, 711 { 0x5597, &sis_info33 }, 712 { 0x5591, &sis_info33 }, 713 { 0x5582, &sis_info33 }, 714 { 0x5581, &sis_info33 }, 715 716 { 0x5596, &sis_info }, 717 { 0x5571, &sis_info }, 718 { 0x5517, &sis_info }, 719 { 0x5511, &sis_info }, 720 721 {0} 722 }; 723 static struct sis_chipset sis133_early = { 724 0x0, &sis_info133_early 725 }; 726 static struct sis_chipset sis133 = { 727 0x0, &sis_info133 728 }; 729 static struct sis_chipset sis100_early = { 730 0x0, &sis_info100_early 731 }; 732 static struct sis_chipset sis100 = { 733 0x0, &sis_info100 734 }; 735 736 if (!printed_version++) 737 dev_printk(KERN_DEBUG, &pdev->dev, 738 "version " DRV_VERSION "\n"); 739 740 rc = pcim_enable_device(pdev); 741 if (rc) 742 return rc; 743 744 /* We have to find the bridge first */ 745 for (sets = &sis_chipsets[0]; sets->device; sets++) { 746 host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL); 747 if (host != NULL) { 748 chipset = sets; /* Match found */ 749 if (sets->device == 0x630) { /* SIS630 */ 750 if (host->revision >= 0x30) /* 630 ET */ 751 chipset = &sis100_early; 752 } 753 break; 754 } 755 } 756 757 /* Look for concealed bridges */ 758 if (chipset == NULL) { 759 /* Second check */ 760 u32 idemisc; 761 u16 trueid; 762 763 /* Disable ID masking and register remapping then 764 see what the real ID is */ 765 766 pci_read_config_dword(pdev, 0x54, &idemisc); 767 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); 768 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 769 pci_write_config_dword(pdev, 0x54, idemisc); 770 771 switch(trueid) { 772 case 0x5518: /* SIS 962/963 */ 773 chipset = &sis133; 774 if ((idemisc & 0x40000000) == 0) { 775 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); 776 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); 777 } 778 break; 779 case 0x0180: /* SIS 965/965L */ 780 chipset = &sis133; 781 break; 782 case 0x1180: /* SIS 966/966L */ 783 chipset = &sis133; 784 break; 785 } 786 } 787 788 /* Further check */ 789 if (chipset == NULL) { 790 struct pci_dev *lpc_bridge; 791 u16 trueid; 792 u8 prefctl; 793 u8 idecfg; 794 795 /* Try the second unmasking technique */ 796 pci_read_config_byte(pdev, 0x4a, &idecfg); 797 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); 798 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 799 pci_write_config_byte(pdev, 0x4a, idecfg); 800 801 switch(trueid) { 802 case 0x5517: 803 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ 804 if (lpc_bridge == NULL) 805 break; 806 pci_read_config_byte(pdev, 0x49, &prefctl); 807 pci_dev_put(lpc_bridge); 808 809 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { 810 chipset = &sis133_early; 811 break; 812 } 813 chipset = &sis100; 814 break; 815 } 816 } 817 pci_dev_put(host); 818 819 /* No chipset info, no support */ 820 if (chipset == NULL) 821 return -ENODEV; 822 823 ppi[0] = chipset->info; 824 825 sis_fixup(pdev, chipset); 826 827 return ata_pci_bmdma_init_one(pdev, ppi, &sis_sht, chipset, 0); 828} 829 830#ifdef CONFIG_PM 831static int sis_reinit_one(struct pci_dev *pdev) 832{ 833 struct ata_host *host = dev_get_drvdata(&pdev->dev); 834 int rc; 835 836 rc = ata_pci_device_do_resume(pdev); 837 if (rc) 838 return rc; 839 840 sis_fixup(pdev, host->private_data); 841 842 ata_host_resume(host); 843 return 0; 844} 845#endif 846 847static const struct pci_device_id sis_pci_tbl[] = { 848 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */ 849 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */ 850 { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */ 851 852 { } 853}; 854 855static struct pci_driver sis_pci_driver = { 856 .name = DRV_NAME, 857 .id_table = sis_pci_tbl, 858 .probe = sis_init_one, 859 .remove = ata_pci_remove_one, 860#ifdef CONFIG_PM 861 .suspend = ata_pci_device_suspend, 862 .resume = sis_reinit_one, 863#endif 864}; 865 866static int __init sis_init(void) 867{ 868 return pci_register_driver(&sis_pci_driver); 869} 870 871static void __exit sis_exit(void) 872{ 873 pci_unregister_driver(&sis_pci_driver); 874} 875 876module_init(sis_init); 877module_exit(sis_exit); 878 879MODULE_AUTHOR("Alan Cox"); 880MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA"); 881MODULE_LICENSE("GPL"); 882MODULE_DEVICE_TABLE(pci, sis_pci_tbl); 883MODULE_VERSION(DRV_VERSION); 884