1/* 2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers. 3 * 4 * This driver is heavily based upon: 5 * 6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 7 * 8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 9 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 10 * Portions Copyright (C) 2003 Red Hat Inc 11 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc. 12 * 13 * TODO 14 * Look into engine reset on timeout errors. Should not be required. 15 */ 16 17#include <linux/kernel.h> 18#include <linux/module.h> 19#include <linux/pci.h> 20#include <linux/init.h> 21#include <linux/blkdev.h> 22#include <linux/delay.h> 23#include <scsi/scsi_host.h> 24#include <linux/libata.h> 25 26#define DRV_NAME "pata_hpt37x" 27#define DRV_VERSION "0.6.15" 28 29struct hpt_clock { 30 u8 xfer_speed; 31 u32 timing; 32}; 33 34struct hpt_chip { 35 const char *name; 36 unsigned int base; 37 struct hpt_clock const *clocks[4]; 38}; 39 40/* key for bus clock timings 41 * bit 42 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. 43 * cycles = value + 1 44 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. 45 * cycles = value + 1 46 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file 47 * register access. 48 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file 49 * register access. 50 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. 51 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. 52 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. 53 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file 54 * register access. 55 * 28 UDMA enable. 56 * 29 DMA enable. 57 * 30 PIO_MST enable. If set, the chip is in bus master mode during 58 * PIO xfer. 59 * 31 FIFO enable. Only for PIO. 60 */ 61 62static struct hpt_clock hpt37x_timings_33[] = { 63 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */ 64 { XFER_UDMA_5, 0x12446231 }, 65 { XFER_UDMA_4, 0x12446231 }, 66 { XFER_UDMA_3, 0x126c6231 }, 67 { XFER_UDMA_2, 0x12486231 }, 68 { XFER_UDMA_1, 0x124c6233 }, 69 { XFER_UDMA_0, 0x12506297 }, 70 71 { XFER_MW_DMA_2, 0x22406c31 }, 72 { XFER_MW_DMA_1, 0x22406c33 }, 73 { XFER_MW_DMA_0, 0x22406c97 }, 74 75 { XFER_PIO_4, 0x06414e31 }, 76 { XFER_PIO_3, 0x06414e42 }, 77 { XFER_PIO_2, 0x06414e53 }, 78 { XFER_PIO_1, 0x06814e93 }, 79 { XFER_PIO_0, 0x06814ea7 } 80}; 81 82static struct hpt_clock hpt37x_timings_50[] = { 83 { XFER_UDMA_6, 0x12848242 }, 84 { XFER_UDMA_5, 0x12848242 }, 85 { XFER_UDMA_4, 0x12ac8242 }, 86 { XFER_UDMA_3, 0x128c8242 }, 87 { XFER_UDMA_2, 0x120c8242 }, 88 { XFER_UDMA_1, 0x12148254 }, 89 { XFER_UDMA_0, 0x121882ea }, 90 91 { XFER_MW_DMA_2, 0x22808242 }, 92 { XFER_MW_DMA_1, 0x22808254 }, 93 { XFER_MW_DMA_0, 0x228082ea }, 94 95 { XFER_PIO_4, 0x0a81f442 }, 96 { XFER_PIO_3, 0x0a81f443 }, 97 { XFER_PIO_2, 0x0a81f454 }, 98 { XFER_PIO_1, 0x0ac1f465 }, 99 { XFER_PIO_0, 0x0ac1f48a } 100}; 101 102static struct hpt_clock hpt37x_timings_66[] = { 103 { XFER_UDMA_6, 0x1c869c62 }, 104 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */ 105 { XFER_UDMA_4, 0x1c8a9c62 }, 106 { XFER_UDMA_3, 0x1c8e9c62 }, 107 { XFER_UDMA_2, 0x1c929c62 }, 108 { XFER_UDMA_1, 0x1c9a9c62 }, 109 { XFER_UDMA_0, 0x1c829c62 }, 110 111 { XFER_MW_DMA_2, 0x2c829c62 }, 112 { XFER_MW_DMA_1, 0x2c829c66 }, 113 { XFER_MW_DMA_0, 0x2c829d2e }, 114 115 { XFER_PIO_4, 0x0c829c62 }, 116 { XFER_PIO_3, 0x0c829c84 }, 117 { XFER_PIO_2, 0x0c829ca6 }, 118 { XFER_PIO_1, 0x0d029d26 }, 119 { XFER_PIO_0, 0x0d029d5e } 120}; 121 122 123static const struct hpt_chip hpt370 = { 124 "HPT370", 125 48, 126 { 127 hpt37x_timings_33, 128 NULL, 129 NULL, 130 NULL 131 } 132}; 133 134static const struct hpt_chip hpt370a = { 135 "HPT370A", 136 48, 137 { 138 hpt37x_timings_33, 139 NULL, 140 hpt37x_timings_50, 141 NULL 142 } 143}; 144 145static const struct hpt_chip hpt372 = { 146 "HPT372", 147 55, 148 { 149 hpt37x_timings_33, 150 NULL, 151 hpt37x_timings_50, 152 hpt37x_timings_66 153 } 154}; 155 156static const struct hpt_chip hpt302 = { 157 "HPT302", 158 66, 159 { 160 hpt37x_timings_33, 161 NULL, 162 hpt37x_timings_50, 163 hpt37x_timings_66 164 } 165}; 166 167static const struct hpt_chip hpt371 = { 168 "HPT371", 169 66, 170 { 171 hpt37x_timings_33, 172 NULL, 173 hpt37x_timings_50, 174 hpt37x_timings_66 175 } 176}; 177 178static const struct hpt_chip hpt372a = { 179 "HPT372A", 180 66, 181 { 182 hpt37x_timings_33, 183 NULL, 184 hpt37x_timings_50, 185 hpt37x_timings_66 186 } 187}; 188 189static const struct hpt_chip hpt374 = { 190 "HPT374", 191 48, 192 { 193 hpt37x_timings_33, 194 NULL, 195 NULL, 196 NULL 197 } 198}; 199 200/** 201 * hpt37x_find_mode - reset the hpt37x bus 202 * @ap: ATA port 203 * @speed: transfer mode 204 * 205 * Return the 32bit register programming information for this channel 206 * that matches the speed provided. 207 */ 208 209static u32 hpt37x_find_mode(struct ata_port *ap, int speed) 210{ 211 struct hpt_clock *clocks = ap->host->private_data; 212 213 while(clocks->xfer_speed) { 214 if (clocks->xfer_speed == speed) 215 return clocks->timing; 216 clocks++; 217 } 218 BUG(); 219 return 0xffffffffU; /* silence compiler warning */ 220} 221 222static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[]) 223{ 224 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 225 int i = 0; 226 227 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 228 229 while (list[i] != NULL) { 230 if (!strcmp(list[i], model_num)) { 231 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n", 232 modestr, list[i]); 233 return 1; 234 } 235 i++; 236 } 237 return 0; 238} 239 240static const char *bad_ata33[] = { 241 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", 242 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", 243 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", 244 "Maxtor 90510D4", 245 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", 246 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", 247 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", 248 NULL 249}; 250 251static const char *bad_ata100_5[] = { 252 "IBM-DTLA-307075", 253 "IBM-DTLA-307060", 254 "IBM-DTLA-307045", 255 "IBM-DTLA-307030", 256 "IBM-DTLA-307020", 257 "IBM-DTLA-307015", 258 "IBM-DTLA-305040", 259 "IBM-DTLA-305030", 260 "IBM-DTLA-305020", 261 "IC35L010AVER07-0", 262 "IC35L020AVER07-0", 263 "IC35L030AVER07-0", 264 "IC35L040AVER07-0", 265 "IC35L060AVER07-0", 266 "WDC AC310200R", 267 NULL 268}; 269 270/** 271 * hpt370_filter - mode selection filter 272 * @adev: ATA device 273 * 274 * Block UDMA on devices that cause trouble with this controller. 275 */ 276 277static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask) 278{ 279 if (adev->class == ATA_DEV_ATA) { 280 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) 281 mask &= ~ATA_MASK_UDMA; 282 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) 283 mask &= ~(0xE0 << ATA_SHIFT_UDMA); 284 } 285 return mask; 286} 287 288/** 289 * hpt370a_filter - mode selection filter 290 * @adev: ATA device 291 * 292 * Block UDMA on devices that cause trouble with this controller. 293 */ 294 295static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask) 296{ 297 if (adev->class == ATA_DEV_ATA) { 298 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) 299 mask &= ~(0xE0 << ATA_SHIFT_UDMA); 300 } 301 return mask; 302} 303 304/** 305 * hpt37x_cable_detect - Detect the cable type 306 * @ap: ATA port to detect on 307 * 308 * Return the cable type attached to this port 309 */ 310 311static int hpt37x_cable_detect(struct ata_port *ap) 312{ 313 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 314 u8 scr2, ata66; 315 316 pci_read_config_byte(pdev, 0x5B, &scr2); 317 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); 318 319 udelay(10); /* debounce */ 320 321 /* Cable register now active */ 322 pci_read_config_byte(pdev, 0x5A, &ata66); 323 /* Restore state */ 324 pci_write_config_byte(pdev, 0x5B, scr2); 325 326 if (ata66 & (2 >> ap->port_no)) 327 return ATA_CBL_PATA40; 328 else 329 return ATA_CBL_PATA80; 330} 331 332/** 333 * hpt374_fn1_cable_detect - Detect the cable type 334 * @ap: ATA port to detect on 335 * 336 * Return the cable type attached to this port 337 */ 338 339static int hpt374_fn1_cable_detect(struct ata_port *ap) 340{ 341 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 342 unsigned int mcrbase = 0x50 + 4 * ap->port_no; 343 u16 mcr3; 344 u8 ata66; 345 346 /* Do the extra channel work */ 347 pci_read_config_word(pdev, mcrbase + 2, &mcr3); 348 /* Set bit 15 of 0x52 to enable TCBLID as input */ 349 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000); 350 pci_read_config_byte(pdev, 0x5A, &ata66); 351 /* Reset TCBLID/FCBLID to output */ 352 pci_write_config_word(pdev, mcrbase + 2, mcr3); 353 354 if (ata66 & (2 >> ap->port_no)) 355 return ATA_CBL_PATA40; 356 else 357 return ATA_CBL_PATA80; 358} 359 360/** 361 * hpt37x_pre_reset - reset the hpt37x bus 362 * @link: ATA link to reset 363 * @deadline: deadline jiffies for the operation 364 * 365 * Perform the initial reset handling for the HPT37x. 366 */ 367 368static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline) 369{ 370 struct ata_port *ap = link->ap; 371 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 372 static const struct pci_bits hpt37x_enable_bits[] = { 373 { 0x50, 1, 0x04, 0x04 }, 374 { 0x54, 1, 0x04, 0x04 } 375 }; 376 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) 377 return -ENOENT; 378 379 /* Reset the state machine */ 380 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 381 udelay(100); 382 383 return ata_sff_prereset(link, deadline); 384} 385 386static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev, 387 u8 mode) 388{ 389 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 390 u32 addr1, addr2; 391 u32 reg, timing, mask; 392 u8 fast; 393 394 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 395 addr2 = 0x51 + 4 * ap->port_no; 396 397 /* Fast interrupt prediction disable, hold off interrupt disable */ 398 pci_read_config_byte(pdev, addr2, &fast); 399 fast &= ~0x02; 400 fast |= 0x01; 401 pci_write_config_byte(pdev, addr2, fast); 402 403 /* Determine timing mask and find matching mode entry */ 404 if (mode < XFER_MW_DMA_0) 405 mask = 0xcfc3ffff; 406 else if (mode < XFER_UDMA_0) 407 mask = 0x31c001ff; 408 else 409 mask = 0x303c0000; 410 411 timing = hpt37x_find_mode(ap, mode); 412 413 pci_read_config_dword(pdev, addr1, ®); 414 reg = (reg & ~mask) | (timing & mask); 415 pci_write_config_dword(pdev, addr1, reg); 416} 417/** 418 * hpt370_set_piomode - PIO setup 419 * @ap: ATA interface 420 * @adev: device on the interface 421 * 422 * Perform PIO mode setup. 423 */ 424 425static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev) 426{ 427 hpt370_set_mode(ap, adev, adev->pio_mode); 428} 429 430/** 431 * hpt370_set_dmamode - DMA timing setup 432 * @ap: ATA interface 433 * @adev: Device being configured 434 * 435 * Set up the channel for MWDMA or UDMA modes. 436 */ 437 438static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev) 439{ 440 hpt370_set_mode(ap, adev, adev->dma_mode); 441} 442 443 444static void hpt370_bmdma_stop(struct ata_queued_cmd *qc) 445{ 446 struct ata_port *ap = qc->ap; 447 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 448 void __iomem *bmdma = ap->ioaddr.bmdma_addr; 449 u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); 450 u8 dma_cmd; 451 452 if (dma_stat & ATA_DMA_ACTIVE) { 453 udelay(20); 454 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); 455 } 456 if (dma_stat & ATA_DMA_ACTIVE) { 457 /* Clear the engine */ 458 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 459 udelay(10); 460 /* Stop DMA */ 461 dma_cmd = ioread8(bmdma + ATA_DMA_CMD); 462 iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD); 463 /* Clear Error */ 464 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); 465 iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, 466 bmdma + ATA_DMA_STATUS); 467 /* Clear the engine */ 468 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); 469 udelay(10); 470 } 471 ata_bmdma_stop(qc); 472} 473 474static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev, 475 u8 mode) 476{ 477 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 478 u32 addr1, addr2; 479 u32 reg, timing, mask; 480 u8 fast; 481 482 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 483 addr2 = 0x51 + 4 * ap->port_no; 484 485 /* Fast interrupt prediction disable, hold off interrupt disable */ 486 pci_read_config_byte(pdev, addr2, &fast); 487 fast &= ~0x07; 488 pci_write_config_byte(pdev, addr2, fast); 489 490 /* Determine timing mask and find matching mode entry */ 491 if (mode < XFER_MW_DMA_0) 492 mask = 0xcfc3ffff; 493 else if (mode < XFER_UDMA_0) 494 mask = 0x31c001ff; 495 else 496 mask = 0x303c0000; 497 498 timing = hpt37x_find_mode(ap, mode); 499 500 pci_read_config_dword(pdev, addr1, ®); 501 reg = (reg & ~mask) | (timing & mask); 502 pci_write_config_dword(pdev, addr1, reg); 503} 504 505/** 506 * hpt372_set_piomode - PIO setup 507 * @ap: ATA interface 508 * @adev: device on the interface 509 * 510 * Perform PIO mode setup. 511 */ 512 513static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev) 514{ 515 hpt372_set_mode(ap, adev, adev->pio_mode); 516} 517 518/** 519 * hpt372_set_dmamode - DMA timing setup 520 * @ap: ATA interface 521 * @adev: Device being configured 522 * 523 * Set up the channel for MWDMA or UDMA modes. 524 */ 525 526static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev) 527{ 528 hpt372_set_mode(ap, adev, adev->dma_mode); 529} 530 531/** 532 * hpt37x_bmdma_end - DMA engine stop 533 * @qc: ATA command 534 * 535 * Clean up after the HPT372 and later DMA engine 536 */ 537 538static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc) 539{ 540 struct ata_port *ap = qc->ap; 541 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 542 int mscreg = 0x50 + 4 * ap->port_no; 543 u8 bwsr_stat, msc_stat; 544 545 pci_read_config_byte(pdev, 0x6A, &bwsr_stat); 546 pci_read_config_byte(pdev, mscreg, &msc_stat); 547 if (bwsr_stat & (1 << ap->port_no)) 548 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); 549 ata_bmdma_stop(qc); 550} 551 552 553static struct scsi_host_template hpt37x_sht = { 554 ATA_BMDMA_SHT(DRV_NAME), 555}; 556 557/* 558 * Configuration for HPT370 559 */ 560 561static struct ata_port_operations hpt370_port_ops = { 562 .inherits = &ata_bmdma_port_ops, 563 564 .bmdma_stop = hpt370_bmdma_stop, 565 566 .mode_filter = hpt370_filter, 567 .cable_detect = hpt37x_cable_detect, 568 .set_piomode = hpt370_set_piomode, 569 .set_dmamode = hpt370_set_dmamode, 570 .prereset = hpt37x_pre_reset, 571}; 572 573/* 574 * Configuration for HPT370A. Close to 370 but less filters 575 */ 576 577static struct ata_port_operations hpt370a_port_ops = { 578 .inherits = &hpt370_port_ops, 579 .mode_filter = hpt370a_filter, 580}; 581 582/* 583 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO 584 * and DMA mode setting functionality. 585 */ 586 587static struct ata_port_operations hpt372_port_ops = { 588 .inherits = &ata_bmdma_port_ops, 589 590 .bmdma_stop = hpt37x_bmdma_stop, 591 592 .cable_detect = hpt37x_cable_detect, 593 .set_piomode = hpt372_set_piomode, 594 .set_dmamode = hpt372_set_dmamode, 595 .prereset = hpt37x_pre_reset, 596}; 597 598/* 599 * Configuration for HPT374. Mode setting works like 372 and friends 600 * but we have a different cable detection procedure for function 1. 601 */ 602 603static struct ata_port_operations hpt374_fn1_port_ops = { 604 .inherits = &hpt372_port_ops, 605 .cable_detect = hpt374_fn1_cable_detect, 606 .prereset = hpt37x_pre_reset, 607}; 608 609/** 610 * hpt37x_clock_slot - Turn timing to PC clock entry 611 * @freq: Reported frequency timing 612 * @base: Base timing 613 * 614 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50 615 * and 3 for 66Mhz) 616 */ 617 618static int hpt37x_clock_slot(unsigned int freq, unsigned int base) 619{ 620 unsigned int f = (base * freq) / 192; /* Mhz */ 621 if (f < 40) 622 return 0; /* 33Mhz slot */ 623 if (f < 45) 624 return 1; /* 40Mhz slot */ 625 if (f < 55) 626 return 2; /* 50Mhz slot */ 627 return 3; /* 60Mhz slot */ 628} 629 630/** 631 * hpt37x_calibrate_dpll - Calibrate the DPLL loop 632 * @dev: PCI device 633 * 634 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this 635 * succeeds 636 */ 637 638static int hpt37x_calibrate_dpll(struct pci_dev *dev) 639{ 640 u8 reg5b; 641 u32 reg5c; 642 int tries; 643 644 for(tries = 0; tries < 0x5000; tries++) { 645 udelay(50); 646 pci_read_config_byte(dev, 0x5b, ®5b); 647 if (reg5b & 0x80) { 648 /* See if it stays set */ 649 for(tries = 0; tries < 0x1000; tries ++) { 650 pci_read_config_byte(dev, 0x5b, ®5b); 651 /* Failed ? */ 652 if ((reg5b & 0x80) == 0) 653 return 0; 654 } 655 /* Turn off tuning, we have the DPLL set */ 656 pci_read_config_dword(dev, 0x5c, ®5c); 657 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100); 658 return 1; 659 } 660 } 661 /* Never went stable */ 662 return 0; 663} 664 665static u32 hpt374_read_freq(struct pci_dev *pdev) 666{ 667 u32 freq; 668 unsigned long io_base = pci_resource_start(pdev, 4); 669 if (PCI_FUNC(pdev->devfn) & 1) { 670 struct pci_dev *pdev_0; 671 672 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1); 673 /* Someone hot plugged the controller on us ? */ 674 if (pdev_0 == NULL) 675 return 0; 676 io_base = pci_resource_start(pdev_0, 4); 677 freq = inl(io_base + 0x90); 678 pci_dev_put(pdev_0); 679 } else 680 freq = inl(io_base + 0x90); 681 return freq; 682} 683 684/** 685 * hpt37x_init_one - Initialise an HPT37X/302 686 * @dev: PCI device 687 * @id: Entry in match table 688 * 689 * Initialise an HPT37x device. There are some interesting complications 690 * here. Firstly the chip may report 366 and be one of several variants. 691 * Secondly all the timings depend on the clock for the chip which we must 692 * detect and look up 693 * 694 * This is the known chip mappings. It may be missing a couple of later 695 * releases. 696 * 697 * Chip version PCI Rev Notes 698 * HPT366 4 (HPT366) 0 Other driver 699 * HPT366 4 (HPT366) 1 Other driver 700 * HPT368 4 (HPT366) 2 Other driver 701 * HPT370 4 (HPT366) 3 UDMA100 702 * HPT370A 4 (HPT366) 4 UDMA100 703 * HPT372 4 (HPT366) 5 UDMA133 (1) 704 * HPT372N 4 (HPT366) 6 Other driver 705 * HPT372A 5 (HPT372) 1 UDMA133 (1) 706 * HPT372N 5 (HPT372) 2 Other driver 707 * HPT302 6 (HPT302) 1 UDMA133 708 * HPT302N 6 (HPT302) 2 Other driver 709 * HPT371 7 (HPT371) * UDMA133 710 * HPT374 8 (HPT374) * UDMA133 4 channel 711 * HPT372N 9 (HPT372N) * Other driver 712 * 713 * (1) UDMA133 support depends on the bus clock 714 */ 715 716static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id) 717{ 718 /* HPT370 - UDMA100 */ 719 static const struct ata_port_info info_hpt370 = { 720 .flags = ATA_FLAG_SLAVE_POSS, 721 .pio_mask = ATA_PIO4, 722 .mwdma_mask = ATA_MWDMA2, 723 .udma_mask = ATA_UDMA5, 724 .port_ops = &hpt370_port_ops 725 }; 726 /* HPT370A - UDMA100 */ 727 static const struct ata_port_info info_hpt370a = { 728 .flags = ATA_FLAG_SLAVE_POSS, 729 .pio_mask = ATA_PIO4, 730 .mwdma_mask = ATA_MWDMA2, 731 .udma_mask = ATA_UDMA5, 732 .port_ops = &hpt370a_port_ops 733 }; 734 /* HPT370 - UDMA100 */ 735 static const struct ata_port_info info_hpt370_33 = { 736 .flags = ATA_FLAG_SLAVE_POSS, 737 .pio_mask = ATA_PIO4, 738 .mwdma_mask = ATA_MWDMA2, 739 .udma_mask = ATA_UDMA5, 740 .port_ops = &hpt370_port_ops 741 }; 742 /* HPT370A - UDMA100 */ 743 static const struct ata_port_info info_hpt370a_33 = { 744 .flags = ATA_FLAG_SLAVE_POSS, 745 .pio_mask = ATA_PIO4, 746 .mwdma_mask = ATA_MWDMA2, 747 .udma_mask = ATA_UDMA5, 748 .port_ops = &hpt370a_port_ops 749 }; 750 /* HPT371, 372 and friends - UDMA133 */ 751 static const struct ata_port_info info_hpt372 = { 752 .flags = ATA_FLAG_SLAVE_POSS, 753 .pio_mask = ATA_PIO4, 754 .mwdma_mask = ATA_MWDMA2, 755 .udma_mask = ATA_UDMA6, 756 .port_ops = &hpt372_port_ops 757 }; 758 /* HPT374 - UDMA100, function 1 uses different prereset method */ 759 static const struct ata_port_info info_hpt374_fn0 = { 760 .flags = ATA_FLAG_SLAVE_POSS, 761 .pio_mask = ATA_PIO4, 762 .mwdma_mask = ATA_MWDMA2, 763 .udma_mask = ATA_UDMA5, 764 .port_ops = &hpt372_port_ops 765 }; 766 static const struct ata_port_info info_hpt374_fn1 = { 767 .flags = ATA_FLAG_SLAVE_POSS, 768 .pio_mask = ATA_PIO4, 769 .mwdma_mask = ATA_MWDMA2, 770 .udma_mask = ATA_UDMA5, 771 .port_ops = &hpt374_fn1_port_ops 772 }; 773 774 static const int MHz[4] = { 33, 40, 50, 66 }; 775 void *private_data = NULL; 776 const struct ata_port_info *ppi[] = { NULL, NULL }; 777 u8 rev = dev->revision; 778 u8 irqmask; 779 u8 mcr1; 780 u32 freq; 781 int prefer_dpll = 1; 782 783 unsigned long iobase = pci_resource_start(dev, 4); 784 785 const struct hpt_chip *chip_table; 786 int clock_slot; 787 int rc; 788 789 rc = pcim_enable_device(dev); 790 if (rc) 791 return rc; 792 793 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) { 794 /* May be a later chip in disguise. Check */ 795 /* Older chips are in the HPT366 driver. Ignore them */ 796 if (rev < 3) 797 return -ENODEV; 798 /* N series chips have their own driver. Ignore */ 799 if (rev == 6) 800 return -ENODEV; 801 802 switch(rev) { 803 case 3: 804 ppi[0] = &info_hpt370; 805 chip_table = &hpt370; 806 prefer_dpll = 0; 807 break; 808 case 4: 809 ppi[0] = &info_hpt370a; 810 chip_table = &hpt370a; 811 prefer_dpll = 0; 812 break; 813 case 5: 814 ppi[0] = &info_hpt372; 815 chip_table = &hpt372; 816 break; 817 default: 818 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 " 819 "subtype, please report (%d).\n", rev); 820 return -ENODEV; 821 } 822 } else { 823 switch(dev->device) { 824 case PCI_DEVICE_ID_TTI_HPT372: 825 /* 372N if rev >= 2*/ 826 if (rev >= 2) 827 return -ENODEV; 828 ppi[0] = &info_hpt372; 829 chip_table = &hpt372a; 830 break; 831 case PCI_DEVICE_ID_TTI_HPT302: 832 /* 302N if rev > 1 */ 833 if (rev > 1) 834 return -ENODEV; 835 ppi[0] = &info_hpt372; 836 /* Check this */ 837 chip_table = &hpt302; 838 break; 839 case PCI_DEVICE_ID_TTI_HPT371: 840 if (rev > 1) 841 return -ENODEV; 842 ppi[0] = &info_hpt372; 843 chip_table = &hpt371; 844 /* Single channel device, master is not present 845 but the BIOS (or us for non x86) must mark it 846 absent */ 847 pci_read_config_byte(dev, 0x50, &mcr1); 848 mcr1 &= ~0x04; 849 pci_write_config_byte(dev, 0x50, mcr1); 850 break; 851 case PCI_DEVICE_ID_TTI_HPT374: 852 chip_table = &hpt374; 853 if (!(PCI_FUNC(dev->devfn) & 1)) 854 *ppi = &info_hpt374_fn0; 855 else 856 *ppi = &info_hpt374_fn1; 857 break; 858 default: 859 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device); 860 return -ENODEV; 861 } 862 } 863 /* Ok so this is a chip we support */ 864 865 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 866 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 867 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 868 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 869 870 pci_read_config_byte(dev, 0x5A, &irqmask); 871 irqmask &= ~0x10; 872 pci_write_config_byte(dev, 0x5a, irqmask); 873 874 /* 875 * default to pci clock. make sure MA15/16 are set to output 876 * to prevent drives having problems with 40-pin cables. Needed 877 * for some drives such as IBM-DTLA which will not enter ready 878 * state on reset when PDIAG is a input. 879 */ 880 881 pci_write_config_byte(dev, 0x5b, 0x23); 882 883 /* 884 * HighPoint does this for HPT372A. 885 * NOTE: This register is only writeable via I/O space. 886 */ 887 if (chip_table == &hpt372a) 888 outb(0x0e, iobase + 0x9c); 889 890 /* Some devices do not let this value be accessed via PCI space 891 according to the old driver. In addition we must use the value 892 from FN 0 on the HPT374 */ 893 894 if (chip_table == &hpt374) { 895 freq = hpt374_read_freq(dev); 896 if (freq == 0) 897 return -ENODEV; 898 } else 899 freq = inl(iobase + 0x90); 900 901 if ((freq >> 12) != 0xABCDE) { 902 int i; 903 u8 sr; 904 u32 total = 0; 905 906 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n"); 907 908 /* This is the process the HPT371 BIOS is reported to use */ 909 for(i = 0; i < 128; i++) { 910 pci_read_config_byte(dev, 0x78, &sr); 911 total += sr & 0x1FF; 912 udelay(15); 913 } 914 freq = total / 128; 915 } 916 freq &= 0x1FF; 917 918 /* 919 * Turn the frequency check into a band and then find a timing 920 * table to match it. 921 */ 922 923 clock_slot = hpt37x_clock_slot(freq, chip_table->base); 924 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { 925 /* 926 * We need to try PLL mode instead 927 * 928 * For non UDMA133 capable devices we should 929 * use a 50MHz DPLL by choice 930 */ 931 unsigned int f_low, f_high; 932 int dpll, adjust; 933 934 /* Compute DPLL */ 935 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; 936 937 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; 938 f_high = f_low + 2; 939 if (clock_slot > 1) 940 f_high += 2; 941 942 /* Select the DPLL clock. */ 943 pci_write_config_byte(dev, 0x5b, 0x21); 944 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); 945 946 for(adjust = 0; adjust < 8; adjust++) { 947 if (hpt37x_calibrate_dpll(dev)) 948 break; 949 /* See if it'll settle at a fractionally different clock */ 950 if (adjust & 1) 951 f_low -= adjust >> 1; 952 else 953 f_high += adjust >> 1; 954 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); 955 } 956 if (adjust == 8) { 957 printk(KERN_ERR "pata_hpt37x: DPLL did not stabilize!\n"); 958 return -ENODEV; 959 } 960 if (dpll == 3) 961 private_data = (void *)hpt37x_timings_66; 962 else 963 private_data = (void *)hpt37x_timings_50; 964 965 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n", 966 MHz[clock_slot], MHz[dpll]); 967 } else { 968 private_data = (void *)chip_table->clocks[clock_slot]; 969 /* 970 * Perform a final fixup. Note that we will have used the 971 * DPLL on the HPT372 which means we don't have to worry 972 * about lack of UDMA133 support on lower clocks 973 */ 974 975 if (clock_slot < 2 && ppi[0] == &info_hpt370) 976 ppi[0] = &info_hpt370_33; 977 if (clock_slot < 2 && ppi[0] == &info_hpt370a) 978 ppi[0] = &info_hpt370a_33; 979 printk(KERN_INFO "pata_hpt37x: %s using %dMHz bus clock.\n", 980 chip_table->name, MHz[clock_slot]); 981 } 982 983 /* Now kick off ATA set up */ 984 return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0); 985} 986 987static const struct pci_device_id hpt37x[] = { 988 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, 989 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, 990 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, 991 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), }, 992 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, 993 994 { }, 995}; 996 997static struct pci_driver hpt37x_pci_driver = { 998 .name = DRV_NAME, 999 .id_table = hpt37x, 1000 .probe = hpt37x_init_one, 1001 .remove = ata_pci_remove_one 1002}; 1003 1004static int __init hpt37x_init(void) 1005{ 1006 return pci_register_driver(&hpt37x_pci_driver); 1007} 1008 1009static void __exit hpt37x_exit(void) 1010{ 1011 pci_unregister_driver(&hpt37x_pci_driver); 1012} 1013 1014MODULE_AUTHOR("Alan Cox"); 1015MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x"); 1016MODULE_LICENSE("GPL"); 1017MODULE_DEVICE_TABLE(pci, hpt37x); 1018MODULE_VERSION(DRV_VERSION); 1019 1020module_init(hpt37x_init); 1021module_exit(hpt37x_exit); 1022