1/* 2 * Low-level PCI config space access for OLPC systems who lack the VSA 3 * PCI virtualization software. 4 * 5 * Copyright �� 2006 Advanced Micro Devices, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * The AMD Geode chipset (ie: GX2 processor, cs5536 I/O companion device) 13 * has some I/O functions (display, southbridge, sound, USB HCIs, etc) 14 * that more or less behave like PCI devices, but the hardware doesn't 15 * directly implement the PCI configuration space headers. AMD provides 16 * "VSA" (Virtual System Architecture) software that emulates PCI config 17 * space for these devices, by trapping I/O accesses to PCI config register 18 * (CF8/CFC) and running some code in System Management Mode interrupt state. 19 * On the OLPC platform, we don't want to use that VSA code because 20 * (a) it slows down suspend/resume, and (b) recompiling it requires special 21 * compilers that are hard to get. So instead of letting the complex VSA 22 * code simulate the PCI config registers for the on-chip devices, we 23 * just simulate them the easy way, by inserting the code into the 24 * pci_write_config and pci_read_config path. Most of the config registers 25 * are read-only anyway, so the bulk of the simulation is just table lookup. 26 */ 27 28#include <linux/pci.h> 29#include <linux/init.h> 30#include <asm/olpc.h> 31#include <asm/geode.h> 32#include <asm/pci_x86.h> 33 34/* 35 * In the tables below, the first two line (8 longwords) are the 36 * size masks that are used when the higher level PCI code determines 37 * the size of the region by writing ~0 to a base address register 38 * and reading back the result. 39 * 40 * The following lines are the values that are read during normal 41 * PCI config access cycles, i.e. not after just having written 42 * ~0 to a base address register. 43 */ 44 45static const uint32_t lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */ 46 0x0, 0x0, 0x0, 0x0, 47 0x0, 0x0, 0x0, 0x0, 48 49 0x281022, 0x2200005, 0x6000021, 0x80f808, /* AMD Vendor ID */ 50 0x0, 0x0, 0x0, 0x0, /* No virtual registers, hence no BAR */ 51 0x0, 0x0, 0x0, 0x28100b, 52 0x0, 0x0, 0x0, 0x0, 53 0x0, 0x0, 0x0, 0x0, 54 0x0, 0x0, 0x0, 0x0, 55 0x0, 0x0, 0x0, 0x0, 56}; 57 58static const uint32_t gxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */ 59 0xfffffffd, 0x0, 0x0, 0x0, 60 0x0, 0x0, 0x0, 0x0, 61 62 0x28100b, 0x2200005, 0x6000021, 0x80f808, /* NSC Vendor ID */ 63 0xac1d, 0x0, 0x0, 0x0, /* I/O BAR - base of virtual registers */ 64 0x0, 0x0, 0x0, 0x28100b, 65 0x0, 0x0, 0x0, 0x0, 66 0x0, 0x0, 0x0, 0x0, 67 0x0, 0x0, 0x0, 0x0, 68 0x0, 0x0, 0x0, 0x0, 69}; 70 71static const uint32_t lxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */ 72 0xff000008, 0xffffc000, 0xffffc000, 0xffffc000, 73 0xffffc000, 0x0, 0x0, 0x0, 74 75 0x20811022, 0x2200003, 0x3000000, 0x0, /* AMD Vendor ID */ 76 0xfd000000, 0xfe000000, 0xfe004000, 0xfe008000, /* FB, GP, VG, DF */ 77 0xfe00c000, 0x0, 0x0, 0x30100b, /* VIP */ 78 0x0, 0x0, 0x0, 0x10e, /* INTA, IRQ14 for graphics accel */ 79 0x0, 0x0, 0x0, 0x0, 80 0x3d0, 0x3c0, 0xa0000, 0x0, /* VG IO, VG IO, EGA FB, MONO FB */ 81 0x0, 0x0, 0x0, 0x0, 82}; 83 84static const uint32_t gxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */ 85 0xff800008, 0xffffc000, 0xffffc000, 0xffffc000, 86 0x0, 0x0, 0x0, 0x0, 87 88 0x30100b, 0x2200003, 0x3000000, 0x0, /* NSC Vendor ID */ 89 0xfd000000, 0xfe000000, 0xfe004000, 0xfe008000, /* FB, GP, VG, DF */ 90 0x0, 0x0, 0x0, 0x30100b, 91 0x0, 0x0, 0x0, 0x0, 92 0x0, 0x0, 0x0, 0x0, 93 0x3d0, 0x3c0, 0xa0000, 0x0, /* VG IO, VG IO, EGA FB, MONO FB */ 94 0x0, 0x0, 0x0, 0x0, 95}; 96 97static const uint32_t aes_hdr[] = { /* dev 1 function 2 - devfn = 0xa */ 98 0xffffc000, 0x0, 0x0, 0x0, 99 0x0, 0x0, 0x0, 0x0, 100 101 0x20821022, 0x2a00006, 0x10100000, 0x8, /* NSC Vendor ID */ 102 0xfe010000, 0x0, 0x0, 0x0, /* AES registers */ 103 0x0, 0x0, 0x0, 0x20821022, 104 0x0, 0x0, 0x0, 0x0, 105 0x0, 0x0, 0x0, 0x0, 106 0x0, 0x0, 0x0, 0x0, 107 0x0, 0x0, 0x0, 0x0, 108}; 109 110 111static const uint32_t isa_hdr[] = { /* dev f function 0 - devfn = 78 */ 112 0xfffffff9, 0xffffff01, 0xffffffc1, 0xffffffe1, 113 0xffffff81, 0xffffffc1, 0x0, 0x0, 114 115 0x20901022, 0x2a00049, 0x6010003, 0x802000, 116 0x18b1, 0x1001, 0x1801, 0x1881, /* SMB-8 GPIO-256 MFGPT-64 IRQ-32 */ 117 0x1401, 0x1841, 0x0, 0x20901022, /* PMS-128 ACPI-64 */ 118 0x0, 0x0, 0x0, 0x0, 119 0x0, 0x0, 0x0, 0x0, 120 0x0, 0x0, 0x0, 0xaa5b, /* IRQ steering */ 121 0x0, 0x0, 0x0, 0x0, 122}; 123 124static const uint32_t ac97_hdr[] = { /* dev f function 3 - devfn = 7b */ 125 0xffffff81, 0x0, 0x0, 0x0, 126 0x0, 0x0, 0x0, 0x0, 127 128 0x20931022, 0x2a00041, 0x4010001, 0x0, 129 0x1481, 0x0, 0x0, 0x0, /* I/O BAR-128 */ 130 0x0, 0x0, 0x0, 0x20931022, 131 0x0, 0x0, 0x0, 0x205, /* IntB, IRQ5 */ 132 0x0, 0x0, 0x0, 0x0, 133 0x0, 0x0, 0x0, 0x0, 134 0x0, 0x0, 0x0, 0x0, 135}; 136 137static const uint32_t ohci_hdr[] = { /* dev f function 4 - devfn = 7c */ 138 0xfffff000, 0x0, 0x0, 0x0, 139 0x0, 0x0, 0x0, 0x0, 140 141 0x20941022, 0x2300006, 0xc031002, 0x0, 142 0xfe01a000, 0x0, 0x0, 0x0, /* MEMBAR-1000 */ 143 0x0, 0x0, 0x0, 0x20941022, 144 0x0, 0x40, 0x0, 0x40a, /* CapPtr INT-D, IRQA */ 145 0xc8020001, 0x0, 0x0, 0x0, /* Capabilities - 40 is R/O, 146 44 is mask 8103 (power control) */ 147 0x0, 0x0, 0x0, 0x0, 148 0x0, 0x0, 0x0, 0x0, 149}; 150 151static const uint32_t ehci_hdr[] = { /* dev f function 4 - devfn = 7d */ 152 0xfffff000, 0x0, 0x0, 0x0, 153 0x0, 0x0, 0x0, 0x0, 154 155 0x20951022, 0x2300006, 0xc032002, 0x0, 156 0xfe01b000, 0x0, 0x0, 0x0, /* MEMBAR-1000 */ 157 0x0, 0x0, 0x0, 0x20951022, 158 0x0, 0x40, 0x0, 0x40a, /* CapPtr INT-D, IRQA */ 159 0xc8020001, 0x0, 0x0, 0x0, /* Capabilities - 40 is R/O, 44 is 160 mask 8103 (power control) */ 161 0x01000001, 0x0, 0x0, 0x0, /* EECP - see EHCI spec section 2.1.7 */ 162 0x2020, 0x0, 0x0, 0x0, /* (EHCI page 8) 60 SBRN (R/O), 163 61 FLADJ (R/W), PORTWAKECAP */ 164}; 165 166static uint32_t ff_loc = ~0; 167static uint32_t zero_loc; 168static int bar_probing; /* Set after a write of ~0 to a BAR */ 169static int is_lx; 170 171#define NB_SLOT 0x1 /* Northbridge - GX chip - Device 1 */ 172#define SB_SLOT 0xf /* Southbridge - CS5536 chip - Device F */ 173 174static int is_simulated(unsigned int bus, unsigned int devfn) 175{ 176 return (!bus && ((PCI_SLOT(devfn) == NB_SLOT) || 177 (PCI_SLOT(devfn) == SB_SLOT))); 178} 179 180static uint32_t *hdr_addr(const uint32_t *hdr, int reg) 181{ 182 uint32_t addr; 183 184 /* 185 * This is a little bit tricky. The header maps consist of 186 * 0x20 bytes of size masks, followed by 0x70 bytes of header data. 187 * In the normal case, when not probing a BAR's size, we want 188 * to access the header data, so we add 0x20 to the reg offset, 189 * thus skipping the size mask area. 190 * In the BAR probing case, we want to access the size mask for 191 * the BAR, so we subtract 0x10 (the config header offset for 192 * BAR0), and don't skip the size mask area. 193 */ 194 195 addr = (uint32_t)hdr + reg + (bar_probing ? -0x10 : 0x20); 196 197 bar_probing = 0; 198 return (uint32_t *)addr; 199} 200 201static int pci_olpc_read(unsigned int seg, unsigned int bus, 202 unsigned int devfn, int reg, int len, uint32_t *value) 203{ 204 uint32_t *addr; 205 206 /* Use the hardware mechanism for non-simulated devices */ 207 if (!is_simulated(bus, devfn)) 208 return pci_direct_conf1.read(seg, bus, devfn, reg, len, value); 209 210 /* 211 * No device has config registers past 0x70, so we save table space 212 * by not storing entries for the nonexistent registers 213 */ 214 if (reg >= 0x70) 215 addr = &zero_loc; 216 else { 217 switch (devfn) { 218 case 0x8: 219 addr = hdr_addr(is_lx ? lxnb_hdr : gxnb_hdr, reg); 220 break; 221 case 0x9: 222 addr = hdr_addr(is_lx ? lxfb_hdr : gxfb_hdr, reg); 223 break; 224 case 0xa: 225 addr = is_lx ? hdr_addr(aes_hdr, reg) : &ff_loc; 226 break; 227 case 0x78: 228 addr = hdr_addr(isa_hdr, reg); 229 break; 230 case 0x7b: 231 addr = hdr_addr(ac97_hdr, reg); 232 break; 233 case 0x7c: 234 addr = hdr_addr(ohci_hdr, reg); 235 break; 236 case 0x7d: 237 addr = hdr_addr(ehci_hdr, reg); 238 break; 239 default: 240 addr = &ff_loc; 241 break; 242 } 243 } 244 switch (len) { 245 case 1: 246 *value = *(uint8_t *)addr; 247 break; 248 case 2: 249 *value = *(uint16_t *)addr; 250 break; 251 case 4: 252 *value = *addr; 253 break; 254 default: 255 BUG(); 256 } 257 258 return 0; 259} 260 261static int pci_olpc_write(unsigned int seg, unsigned int bus, 262 unsigned int devfn, int reg, int len, uint32_t value) 263{ 264 /* Use the hardware mechanism for non-simulated devices */ 265 if (!is_simulated(bus, devfn)) 266 return pci_direct_conf1.write(seg, bus, devfn, reg, len, value); 267 268 269 /* 270 * Mostly we just discard writes, but if the write is a size probe 271 * (i.e. writing ~0 to a BAR), we remember it and arrange to return 272 * the appropriate size mask on the next read. This is cheating 273 * to some extent, because it depends on the fact that the next 274 * access after such a write will always be a read to the same BAR. 275 */ 276 277 if ((reg >= 0x10) && (reg < 0x2c)) { 278 /* write is to a BAR */ 279 if (value == ~0) 280 bar_probing = 1; 281 } else { 282 /* 283 * No warning on writes to ROM BAR, CMD, LATENCY_TIMER, 284 * CACHE_LINE_SIZE, or PM registers. 285 */ 286 if ((reg != PCI_ROM_ADDRESS) && (reg != PCI_COMMAND_MASTER) && 287 (reg != PCI_LATENCY_TIMER) && 288 (reg != PCI_CACHE_LINE_SIZE) && (reg != 0x44)) 289 printk(KERN_WARNING "OLPC PCI: Config write to devfn" 290 " %x reg %x value %x\n", devfn, reg, value); 291 } 292 293 return 0; 294} 295 296static struct pci_raw_ops pci_olpc_conf = { 297 .read = pci_olpc_read, 298 .write = pci_olpc_write, 299}; 300 301int __init pci_olpc_init(void) 302{ 303 printk(KERN_INFO "PCI: Using configuration type OLPC\n"); 304 raw_pci_ops = &pci_olpc_conf; 305 is_lx = is_geode_lx(); 306 return 0; 307} 308