1/* 2 * SGI RTC clock/timer routines. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 * 18 * Copyright (c) 2009 Silicon Graphics, Inc. All Rights Reserved. 19 * Copyright (c) Dimitri Sivanich 20 */ 21#include <linux/clockchips.h> 22#include <linux/slab.h> 23 24#include <asm/uv/uv_mmrs.h> 25#include <asm/uv/uv_hub.h> 26#include <asm/uv/bios.h> 27#include <asm/uv/uv.h> 28#include <asm/apic.h> 29#include <asm/cpu.h> 30 31#define RTC_NAME "sgi_rtc" 32 33static cycle_t uv_read_rtc(struct clocksource *cs); 34static int uv_rtc_next_event(unsigned long, struct clock_event_device *); 35static void uv_rtc_timer_setup(enum clock_event_mode, 36 struct clock_event_device *); 37 38static struct clocksource clocksource_uv = { 39 .name = RTC_NAME, 40 .rating = 400, 41 .read = uv_read_rtc, 42 .mask = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK, 43 .shift = 10, 44 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 45}; 46 47static struct clock_event_device clock_event_device_uv = { 48 .name = RTC_NAME, 49 .features = CLOCK_EVT_FEAT_ONESHOT, 50 .shift = 20, 51 .rating = 400, 52 .irq = -1, 53 .set_next_event = uv_rtc_next_event, 54 .set_mode = uv_rtc_timer_setup, 55 .event_handler = NULL, 56}; 57 58static DEFINE_PER_CPU(struct clock_event_device, cpu_ced); 59 60/* There is one of these allocated per node */ 61struct uv_rtc_timer_head { 62 spinlock_t lock; 63 /* next cpu waiting for timer, local node relative: */ 64 int next_cpu; 65 /* number of cpus on this node: */ 66 int ncpus; 67 struct { 68 int lcpu; /* systemwide logical cpu number */ 69 u64 expires; /* next timer expiration for this cpu */ 70 } cpu[1]; 71}; 72 73/* 74 * Access to uv_rtc_timer_head via blade id. 75 */ 76static struct uv_rtc_timer_head **blade_info __read_mostly; 77 78static int uv_rtc_evt_enable; 79 80/* 81 * Hardware interface routines 82 */ 83 84/* Send IPIs to another node */ 85static void uv_rtc_send_IPI(int cpu) 86{ 87 unsigned long apicid, val; 88 int pnode; 89 90 apicid = cpu_physical_id(cpu); 91 pnode = uv_apicid_to_pnode(apicid); 92 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 93 (apicid << UVH_IPI_INT_APIC_ID_SHFT) | 94 (X86_PLATFORM_IPI_VECTOR << UVH_IPI_INT_VECTOR_SHFT); 95 96 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 97} 98 99/* Check for an RTC interrupt pending */ 100static int uv_intr_pending(int pnode) 101{ 102 return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) & 103 UVH_EVENT_OCCURRED0_RTC1_MASK; 104} 105 106/* Setup interrupt and return non-zero if early expiration occurred. */ 107static int uv_setup_intr(int cpu, u64 expires) 108{ 109 u64 val; 110 int pnode = uv_cpu_to_pnode(cpu); 111 112 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, 113 UVH_RTC1_INT_CONFIG_M_MASK); 114 uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L); 115 116 uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS, 117 UVH_EVENT_OCCURRED0_RTC1_MASK); 118 119 val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) | 120 ((u64)cpu_physical_id(cpu) << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT); 121 122 /* Set configuration */ 123 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val); 124 /* Initialize comparator value */ 125 uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires); 126 127 if (uv_read_rtc(NULL) <= expires) 128 return 0; 129 130 return !uv_intr_pending(pnode); 131} 132 133/* 134 * Per-cpu timer tracking routines 135 */ 136 137static __init void uv_rtc_deallocate_timers(void) 138{ 139 int bid; 140 141 for_each_possible_blade(bid) { 142 kfree(blade_info[bid]); 143 } 144 kfree(blade_info); 145} 146 147/* Allocate per-node list of cpu timer expiration times. */ 148static __init int uv_rtc_allocate_timers(void) 149{ 150 int cpu; 151 152 blade_info = kmalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL); 153 if (!blade_info) 154 return -ENOMEM; 155 memset(blade_info, 0, uv_possible_blades * sizeof(void *)); 156 157 for_each_present_cpu(cpu) { 158 int nid = cpu_to_node(cpu); 159 int bid = uv_cpu_to_blade_id(cpu); 160 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; 161 struct uv_rtc_timer_head *head = blade_info[bid]; 162 163 if (!head) { 164 head = kmalloc_node(sizeof(struct uv_rtc_timer_head) + 165 (uv_blade_nr_possible_cpus(bid) * 166 2 * sizeof(u64)), 167 GFP_KERNEL, nid); 168 if (!head) { 169 uv_rtc_deallocate_timers(); 170 return -ENOMEM; 171 } 172 spin_lock_init(&head->lock); 173 head->ncpus = uv_blade_nr_possible_cpus(bid); 174 head->next_cpu = -1; 175 blade_info[bid] = head; 176 } 177 178 head->cpu[bcpu].lcpu = cpu; 179 head->cpu[bcpu].expires = ULLONG_MAX; 180 } 181 182 return 0; 183} 184 185/* Find and set the next expiring timer. */ 186static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode) 187{ 188 u64 lowest = ULLONG_MAX; 189 int c, bcpu = -1; 190 191 head->next_cpu = -1; 192 for (c = 0; c < head->ncpus; c++) { 193 u64 exp = head->cpu[c].expires; 194 if (exp < lowest) { 195 bcpu = c; 196 lowest = exp; 197 } 198 } 199 if (bcpu >= 0) { 200 head->next_cpu = bcpu; 201 c = head->cpu[bcpu].lcpu; 202 if (uv_setup_intr(c, lowest)) 203 /* If we didn't set it up in time, trigger */ 204 uv_rtc_send_IPI(c); 205 } else { 206 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, 207 UVH_RTC1_INT_CONFIG_M_MASK); 208 } 209} 210 211/* 212 * Set expiration time for current cpu. 213 * 214 * Returns 1 if we missed the expiration time. 215 */ 216static int uv_rtc_set_timer(int cpu, u64 expires) 217{ 218 int pnode = uv_cpu_to_pnode(cpu); 219 int bid = uv_cpu_to_blade_id(cpu); 220 struct uv_rtc_timer_head *head = blade_info[bid]; 221 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; 222 u64 *t = &head->cpu[bcpu].expires; 223 unsigned long flags; 224 int next_cpu; 225 226 spin_lock_irqsave(&head->lock, flags); 227 228 next_cpu = head->next_cpu; 229 *t = expires; 230 231 /* Will this one be next to go off? */ 232 if (next_cpu < 0 || bcpu == next_cpu || 233 expires < head->cpu[next_cpu].expires) { 234 head->next_cpu = bcpu; 235 if (uv_setup_intr(cpu, expires)) { 236 *t = ULLONG_MAX; 237 uv_rtc_find_next_timer(head, pnode); 238 spin_unlock_irqrestore(&head->lock, flags); 239 return -ETIME; 240 } 241 } 242 243 spin_unlock_irqrestore(&head->lock, flags); 244 return 0; 245} 246 247/* 248 * Unset expiration time for current cpu. 249 * 250 * Returns 1 if this timer was pending. 251 */ 252static int uv_rtc_unset_timer(int cpu, int force) 253{ 254 int pnode = uv_cpu_to_pnode(cpu); 255 int bid = uv_cpu_to_blade_id(cpu); 256 struct uv_rtc_timer_head *head = blade_info[bid]; 257 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; 258 u64 *t = &head->cpu[bcpu].expires; 259 unsigned long flags; 260 int rc = 0; 261 262 spin_lock_irqsave(&head->lock, flags); 263 264 if ((head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) || force) 265 rc = 1; 266 267 if (rc) { 268 *t = ULLONG_MAX; 269 /* Was the hardware setup for this timer? */ 270 if (head->next_cpu == bcpu) 271 uv_rtc_find_next_timer(head, pnode); 272 } 273 274 spin_unlock_irqrestore(&head->lock, flags); 275 276 return rc; 277} 278 279 280/* 281 * Kernel interface routines. 282 */ 283 284/* 285 * Read the RTC. 286 * 287 * Starting with HUB rev 2.0, the UV RTC register is replicated across all 288 * cachelines of it's own page. This allows faster simultaneous reads 289 * from a given socket. 290 */ 291static cycle_t uv_read_rtc(struct clocksource *cs) 292{ 293 unsigned long offset; 294 295 if (uv_get_min_hub_revision_id() == 1) 296 offset = 0; 297 else 298 offset = (uv_blade_processor_id() * L1_CACHE_BYTES) % PAGE_SIZE; 299 300 return (cycle_t)uv_read_local_mmr(UVH_RTC | offset); 301} 302 303/* 304 * Program the next event, relative to now 305 */ 306static int uv_rtc_next_event(unsigned long delta, 307 struct clock_event_device *ced) 308{ 309 int ced_cpu = cpumask_first(ced->cpumask); 310 311 return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL)); 312} 313 314/* 315 * Setup the RTC timer in oneshot mode 316 */ 317static void uv_rtc_timer_setup(enum clock_event_mode mode, 318 struct clock_event_device *evt) 319{ 320 int ced_cpu = cpumask_first(evt->cpumask); 321 322 switch (mode) { 323 case CLOCK_EVT_MODE_PERIODIC: 324 case CLOCK_EVT_MODE_ONESHOT: 325 case CLOCK_EVT_MODE_RESUME: 326 /* Nothing to do here yet */ 327 break; 328 case CLOCK_EVT_MODE_UNUSED: 329 case CLOCK_EVT_MODE_SHUTDOWN: 330 uv_rtc_unset_timer(ced_cpu, 1); 331 break; 332 } 333} 334 335static void uv_rtc_interrupt(void) 336{ 337 int cpu = smp_processor_id(); 338 struct clock_event_device *ced = &per_cpu(cpu_ced, cpu); 339 340 if (!ced || !ced->event_handler) 341 return; 342 343 if (uv_rtc_unset_timer(cpu, 0) != 1) 344 return; 345 346 ced->event_handler(ced); 347} 348 349static int __init uv_enable_evt_rtc(char *str) 350{ 351 uv_rtc_evt_enable = 1; 352 353 return 1; 354} 355__setup("uvrtcevt", uv_enable_evt_rtc); 356 357static __init void uv_rtc_register_clockevents(struct work_struct *dummy) 358{ 359 struct clock_event_device *ced = &__get_cpu_var(cpu_ced); 360 361 *ced = clock_event_device_uv; 362 ced->cpumask = cpumask_of(smp_processor_id()); 363 clockevents_register_device(ced); 364} 365 366static __init int uv_rtc_setup_clock(void) 367{ 368 int rc; 369 370 if (!is_uv_system()) 371 return -ENODEV; 372 373 clocksource_uv.mult = clocksource_hz2mult(sn_rtc_cycles_per_second, 374 clocksource_uv.shift); 375 376 /* If single blade, prefer tsc */ 377 if (uv_num_possible_blades() == 1) 378 clocksource_uv.rating = 250; 379 380 rc = clocksource_register(&clocksource_uv); 381 if (rc) 382 printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc); 383 else 384 printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n", 385 sn_rtc_cycles_per_second/(unsigned long)1E6); 386 387 if (rc || !uv_rtc_evt_enable || x86_platform_ipi_callback) 388 return rc; 389 390 /* Setup and register clockevents */ 391 rc = uv_rtc_allocate_timers(); 392 if (rc) 393 goto error; 394 395 x86_platform_ipi_callback = uv_rtc_interrupt; 396 397 clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second, 398 NSEC_PER_SEC, clock_event_device_uv.shift); 399 400 clock_event_device_uv.min_delta_ns = NSEC_PER_SEC / 401 sn_rtc_cycles_per_second; 402 403 clock_event_device_uv.max_delta_ns = clocksource_uv.mask * 404 (NSEC_PER_SEC / sn_rtc_cycles_per_second); 405 406 rc = schedule_on_each_cpu(uv_rtc_register_clockevents); 407 if (rc) { 408 x86_platform_ipi_callback = NULL; 409 uv_rtc_deallocate_timers(); 410 goto error; 411 } 412 413 printk(KERN_INFO "UV RTC clockevents registered\n"); 414 415 return 0; 416 417error: 418 clocksource_unregister(&clocksource_uv); 419 printk(KERN_INFO "UV RTC clockevents failed rc %d\n", rc); 420 421 return rc; 422} 423arch_initcall(uv_rtc_setup_clock); 424