• Home
  • History
  • Annotate
  • Line#
  • Navigate
  • Raw
  • Download
  • only in /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/x86/kernel/
1#include <linux/kernel.h>
2#include <linux/sched.h>
3#include <linux/init.h>
4#include <linux/module.h>
5#include <linux/timer.h>
6#include <linux/acpi_pmtmr.h>
7#include <linux/cpufreq.h>
8#include <linux/dmi.h>
9#include <linux/delay.h>
10#include <linux/clocksource.h>
11#include <linux/percpu.h>
12#include <linux/timex.h>
13
14#include <asm/hpet.h>
15#include <asm/timer.h>
16#include <asm/vgtod.h>
17#include <asm/time.h>
18#include <asm/delay.h>
19#include <asm/hypervisor.h>
20#include <asm/nmi.h>
21#include <asm/x86_init.h>
22
23unsigned int __read_mostly cpu_khz;	/* TSC clocks / usec, not used here */
24EXPORT_SYMBOL(cpu_khz);
25
26unsigned int __read_mostly tsc_khz;
27EXPORT_SYMBOL(tsc_khz);
28
29/*
30 * TSC can be unstable due to cpufreq or due to unsynced TSCs
31 */
32static int __read_mostly tsc_unstable;
33
34/* native_sched_clock() is called before tsc_init(), so
35   we must start with the TSC soft disabled to prevent
36   erroneous rdtsc usage on !cpu_has_tsc processors */
37static int __read_mostly tsc_disabled = -1;
38
39static int tsc_clocksource_reliable;
40/*
41 * Scheduler clock - returns current time in nanosec units.
42 */
43u64 native_sched_clock(void)
44{
45	u64 this_offset;
46
47	/*
48	 * Fall back to jiffies if there's no TSC available:
49	 * ( But note that we still use it if the TSC is marked
50	 *   unstable. We do this because unlike Time Of Day,
51	 *   the scheduler clock tolerates small errors and it's
52	 *   very important for it to be as fast as the platform
53	 *   can achieve it. )
54	 */
55	if (unlikely(tsc_disabled)) {
56		/* No locking but a rare wrong value is not a big deal: */
57		return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
58	}
59
60	/* read the Time Stamp Counter: */
61	rdtscll(this_offset);
62
63	/* return the value in ns */
64	return __cycles_2_ns(this_offset);
65}
66
67/* We need to define a real function for sched_clock, to override the
68   weak default version */
69#ifdef CONFIG_PARAVIRT
70unsigned long long sched_clock(void)
71{
72	return paravirt_sched_clock();
73}
74#else
75unsigned long long
76sched_clock(void) __attribute__((alias("native_sched_clock")));
77#endif
78
79int check_tsc_unstable(void)
80{
81	return tsc_unstable;
82}
83EXPORT_SYMBOL_GPL(check_tsc_unstable);
84
85#ifdef CONFIG_X86_TSC
86int __init notsc_setup(char *str)
87{
88	printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
89			"cannot disable TSC completely.\n");
90	tsc_disabled = 1;
91	return 1;
92}
93#else
94/*
95 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
96 * in cpu/common.c
97 */
98int __init notsc_setup(char *str)
99{
100	setup_clear_cpu_cap(X86_FEATURE_TSC);
101	return 1;
102}
103#endif
104
105__setup("notsc", notsc_setup);
106
107static int __init tsc_setup(char *str)
108{
109	if (!strcmp(str, "reliable"))
110		tsc_clocksource_reliable = 1;
111	return 1;
112}
113
114__setup("tsc=", tsc_setup);
115
116#define MAX_RETRIES     5
117#define SMI_TRESHOLD    50000
118
119/*
120 * Read TSC and the reference counters. Take care of SMI disturbance
121 */
122static u64 tsc_read_refs(u64 *p, int hpet)
123{
124	u64 t1, t2;
125	int i;
126
127	for (i = 0; i < MAX_RETRIES; i++) {
128		t1 = get_cycles();
129		if (hpet)
130			*p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
131		else
132			*p = acpi_pm_read_early();
133		t2 = get_cycles();
134		if ((t2 - t1) < SMI_TRESHOLD)
135			return t2;
136	}
137	return ULLONG_MAX;
138}
139
140/*
141 * Calculate the TSC frequency from HPET reference
142 */
143static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
144{
145	u64 tmp;
146
147	if (hpet2 < hpet1)
148		hpet2 += 0x100000000ULL;
149	hpet2 -= hpet1;
150	tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
151	do_div(tmp, 1000000);
152	do_div(deltatsc, tmp);
153
154	return (unsigned long) deltatsc;
155}
156
157/*
158 * Calculate the TSC frequency from PMTimer reference
159 */
160static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
161{
162	u64 tmp;
163
164	if (!pm1 && !pm2)
165		return ULONG_MAX;
166
167	if (pm2 < pm1)
168		pm2 += (u64)ACPI_PM_OVRRUN;
169	pm2 -= pm1;
170	tmp = pm2 * 1000000000LL;
171	do_div(tmp, PMTMR_TICKS_PER_SEC);
172	do_div(deltatsc, tmp);
173
174	return (unsigned long) deltatsc;
175}
176
177#define CAL_MS		10
178#define CAL_LATCH	(CLOCK_TICK_RATE / (1000 / CAL_MS))
179#define CAL_PIT_LOOPS	1000
180
181#define CAL2_MS		50
182#define CAL2_LATCH	(CLOCK_TICK_RATE / (1000 / CAL2_MS))
183#define CAL2_PIT_LOOPS	5000
184
185
186/*
187 * Try to calibrate the TSC against the Programmable
188 * Interrupt Timer and return the frequency of the TSC
189 * in kHz.
190 *
191 * Return ULONG_MAX on failure to calibrate.
192 */
193static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
194{
195	u64 tsc, t1, t2, delta;
196	unsigned long tscmin, tscmax;
197	int pitcnt;
198
199	/* Set the Gate high, disable speaker */
200	outb((inb(0x61) & ~0x02) | 0x01, 0x61);
201
202	/*
203	 * Setup CTC channel 2* for mode 0, (interrupt on terminal
204	 * count mode), binary count. Set the latch register to 50ms
205	 * (LSB then MSB) to begin countdown.
206	 */
207	outb(0xb0, 0x43);
208	outb(latch & 0xff, 0x42);
209	outb(latch >> 8, 0x42);
210
211	tsc = t1 = t2 = get_cycles();
212
213	pitcnt = 0;
214	tscmax = 0;
215	tscmin = ULONG_MAX;
216	while ((inb(0x61) & 0x20) == 0) {
217		t2 = get_cycles();
218		delta = t2 - tsc;
219		tsc = t2;
220		if ((unsigned long) delta < tscmin)
221			tscmin = (unsigned int) delta;
222		if ((unsigned long) delta > tscmax)
223			tscmax = (unsigned int) delta;
224		pitcnt++;
225	}
226
227	/*
228	 * Sanity checks:
229	 *
230	 * If we were not able to read the PIT more than loopmin
231	 * times, then we have been hit by a massive SMI
232	 *
233	 * If the maximum is 10 times larger than the minimum,
234	 * then we got hit by an SMI as well.
235	 */
236	if (pitcnt < loopmin || tscmax > 10 * tscmin)
237		return ULONG_MAX;
238
239	/* Calculate the PIT value */
240	delta = t2 - t1;
241	do_div(delta, ms);
242	return delta;
243}
244
245/*
246 * This reads the current MSB of the PIT counter, and
247 * checks if we are running on sufficiently fast and
248 * non-virtualized hardware.
249 *
250 * Our expectations are:
251 *
252 *  - the PIT is running at roughly 1.19MHz
253 *
254 *  - each IO is going to take about 1us on real hardware,
255 *    but we allow it to be much faster (by a factor of 10) or
256 *    _slightly_ slower (ie we allow up to a 2us read+counter
257 *    update - anything else implies a unacceptably slow CPU
258 *    or PIT for the fast calibration to work.
259 *
260 *  - with 256 PIT ticks to read the value, we have 214us to
261 *    see the same MSB (and overhead like doing a single TSC
262 *    read per MSB value etc).
263 *
264 *  - We're doing 2 reads per loop (LSB, MSB), and we expect
265 *    them each to take about a microsecond on real hardware.
266 *    So we expect a count value of around 100. But we'll be
267 *    generous, and accept anything over 50.
268 *
269 *  - if the PIT is stuck, and we see *many* more reads, we
270 *    return early (and the next caller of pit_expect_msb()
271 *    then consider it a failure when they don't see the
272 *    next expected value).
273 *
274 * These expectations mean that we know that we have seen the
275 * transition from one expected value to another with a fairly
276 * high accuracy, and we didn't miss any events. We can thus
277 * use the TSC value at the transitions to calculate a pretty
278 * good value for the TSC frequencty.
279 */
280static inline int pit_verify_msb(unsigned char val)
281{
282	/* Ignore LSB */
283	inb(0x42);
284	return inb(0x42) == val;
285}
286
287static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
288{
289	int count;
290	u64 tsc = 0;
291
292	for (count = 0; count < 50000; count++) {
293		if (!pit_verify_msb(val))
294			break;
295		tsc = get_cycles();
296	}
297	*deltap = get_cycles() - tsc;
298	*tscp = tsc;
299
300	/*
301	 * We require _some_ success, but the quality control
302	 * will be based on the error terms on the TSC values.
303	 */
304	return count > 5;
305}
306
307/*
308 * How many MSB values do we want to see? We aim for
309 * a maximum error rate of 500ppm (in practice the
310 * real error is much smaller), but refuse to spend
311 * more than 25ms on it.
312 */
313#define MAX_QUICK_PIT_MS 25
314#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
315
316static unsigned long quick_pit_calibrate(void)
317{
318	int i;
319	u64 tsc, delta;
320	unsigned long d1, d2;
321
322	/* Set the Gate high, disable speaker */
323	outb((inb(0x61) & ~0x02) | 0x01, 0x61);
324
325	/*
326	 * Counter 2, mode 0 (one-shot), binary count
327	 *
328	 * NOTE! Mode 2 decrements by two (and then the
329	 * output is flipped each time, giving the same
330	 * final output frequency as a decrement-by-one),
331	 * so mode 0 is much better when looking at the
332	 * individual counts.
333	 */
334	outb(0xb0, 0x43);
335
336	/* Start at 0xffff */
337	outb(0xff, 0x42);
338	outb(0xff, 0x42);
339
340	/*
341	 * The PIT starts counting at the next edge, so we
342	 * need to delay for a microsecond. The easiest way
343	 * to do that is to just read back the 16-bit counter
344	 * once from the PIT.
345	 */
346	pit_verify_msb(0);
347
348	if (pit_expect_msb(0xff, &tsc, &d1)) {
349		for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
350			if (!pit_expect_msb(0xff-i, &delta, &d2))
351				break;
352
353			/*
354			 * Iterate until the error is less than 500 ppm
355			 */
356			delta -= tsc;
357			if (d1+d2 >= delta >> 11)
358				continue;
359
360			/*
361			 * Check the PIT one more time to verify that
362			 * all TSC reads were stable wrt the PIT.
363			 *
364			 * This also guarantees serialization of the
365			 * last cycle read ('d2') in pit_expect_msb.
366			 */
367			if (!pit_verify_msb(0xfe - i))
368				break;
369			goto success;
370		}
371	}
372	printk("Fast TSC calibration failed\n");
373	return 0;
374
375success:
376	/*
377	 * Ok, if we get here, then we've seen the
378	 * MSB of the PIT decrement 'i' times, and the
379	 * error has shrunk to less than 500 ppm.
380	 *
381	 * As a result, we can depend on there not being
382	 * any odd delays anywhere, and the TSC reads are
383	 * reliable (within the error). We also adjust the
384	 * delta to the middle of the error bars, just
385	 * because it looks nicer.
386	 *
387	 * kHz = ticks / time-in-seconds / 1000;
388	 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
389	 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
390	 */
391	delta += (long)(d2 - d1)/2;
392	delta *= PIT_TICK_RATE;
393	do_div(delta, i*256*1000);
394	printk("Fast TSC calibration using PIT\n");
395	return delta;
396}
397
398/**
399 * native_calibrate_tsc - calibrate the tsc on boot
400 */
401unsigned long native_calibrate_tsc(void)
402{
403	u64 tsc1, tsc2, delta, ref1, ref2;
404	unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
405	unsigned long flags, latch, ms, fast_calibrate;
406	int hpet = is_hpet_enabled(), i, loopmin;
407
408	local_irq_save(flags);
409	fast_calibrate = quick_pit_calibrate();
410	local_irq_restore(flags);
411	if (fast_calibrate)
412		return fast_calibrate;
413
414	/*
415	 * Run 5 calibration loops to get the lowest frequency value
416	 * (the best estimate). We use two different calibration modes
417	 * here:
418	 *
419	 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
420	 * load a timeout of 50ms. We read the time right after we
421	 * started the timer and wait until the PIT count down reaches
422	 * zero. In each wait loop iteration we read the TSC and check
423	 * the delta to the previous read. We keep track of the min
424	 * and max values of that delta. The delta is mostly defined
425	 * by the IO time of the PIT access, so we can detect when a
426	 * SMI/SMM disturbance happend between the two reads. If the
427	 * maximum time is significantly larger than the minimum time,
428	 * then we discard the result and have another try.
429	 *
430	 * 2) Reference counter. If available we use the HPET or the
431	 * PMTIMER as a reference to check the sanity of that value.
432	 * We use separate TSC readouts and check inside of the
433	 * reference read for a SMI/SMM disturbance. We dicard
434	 * disturbed values here as well. We do that around the PIT
435	 * calibration delay loop as we have to wait for a certain
436	 * amount of time anyway.
437	 */
438
439	/* Preset PIT loop values */
440	latch = CAL_LATCH;
441	ms = CAL_MS;
442	loopmin = CAL_PIT_LOOPS;
443
444	for (i = 0; i < 3; i++) {
445		unsigned long tsc_pit_khz;
446
447		/*
448		 * Read the start value and the reference count of
449		 * hpet/pmtimer when available. Then do the PIT
450		 * calibration, which will take at least 50ms, and
451		 * read the end value.
452		 */
453		local_irq_save(flags);
454		tsc1 = tsc_read_refs(&ref1, hpet);
455		tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
456		tsc2 = tsc_read_refs(&ref2, hpet);
457		local_irq_restore(flags);
458
459		/* Pick the lowest PIT TSC calibration so far */
460		tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
461
462		/* hpet or pmtimer available ? */
463		if (!hpet && !ref1 && !ref2)
464			continue;
465
466		/* Check, whether the sampling was disturbed by an SMI */
467		if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
468			continue;
469
470		tsc2 = (tsc2 - tsc1) * 1000000LL;
471		if (hpet)
472			tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
473		else
474			tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
475
476		tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
477
478		/* Check the reference deviation */
479		delta = ((u64) tsc_pit_min) * 100;
480		do_div(delta, tsc_ref_min);
481
482		/*
483		 * If both calibration results are inside a 10% window
484		 * then we can be sure, that the calibration
485		 * succeeded. We break out of the loop right away. We
486		 * use the reference value, as it is more precise.
487		 */
488		if (delta >= 90 && delta <= 110) {
489			printk(KERN_INFO
490			       "TSC: PIT calibration matches %s. %d loops\n",
491			       hpet ? "HPET" : "PMTIMER", i + 1);
492			return tsc_ref_min;
493		}
494
495		/*
496		 * Check whether PIT failed more than once. This
497		 * happens in virtualized environments. We need to
498		 * give the virtual PC a slightly longer timeframe for
499		 * the HPET/PMTIMER to make the result precise.
500		 */
501		if (i == 1 && tsc_pit_min == ULONG_MAX) {
502			latch = CAL2_LATCH;
503			ms = CAL2_MS;
504			loopmin = CAL2_PIT_LOOPS;
505		}
506	}
507
508	/*
509	 * Now check the results.
510	 */
511	if (tsc_pit_min == ULONG_MAX) {
512		/* PIT gave no useful value */
513		printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n");
514
515		/* We don't have an alternative source, disable TSC */
516		if (!hpet && !ref1 && !ref2) {
517			printk("TSC: No reference (HPET/PMTIMER) available\n");
518			return 0;
519		}
520
521		/* The alternative source failed as well, disable TSC */
522		if (tsc_ref_min == ULONG_MAX) {
523			printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
524			       "failed.\n");
525			return 0;
526		}
527
528		/* Use the alternative source */
529		printk(KERN_INFO "TSC: using %s reference calibration\n",
530		       hpet ? "HPET" : "PMTIMER");
531
532		return tsc_ref_min;
533	}
534
535	/* We don't have an alternative source, use the PIT calibration value */
536	if (!hpet && !ref1 && !ref2) {
537		printk(KERN_INFO "TSC: Using PIT calibration value\n");
538		return tsc_pit_min;
539	}
540
541	/* The alternative source failed, use the PIT calibration value */
542	if (tsc_ref_min == ULONG_MAX) {
543		printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. "
544		       "Using PIT calibration\n");
545		return tsc_pit_min;
546	}
547
548	/*
549	 * The calibration values differ too much. In doubt, we use
550	 * the PIT value as we know that there are PMTIMERs around
551	 * running at double speed. At least we let the user know:
552	 */
553	printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
554	       hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
555	printk(KERN_INFO "TSC: Using PIT calibration value\n");
556	return tsc_pit_min;
557}
558
559int recalibrate_cpu_khz(void)
560{
561#ifndef CONFIG_SMP
562	unsigned long cpu_khz_old = cpu_khz;
563
564	if (cpu_has_tsc) {
565		tsc_khz = x86_platform.calibrate_tsc();
566		cpu_khz = tsc_khz;
567		cpu_data(0).loops_per_jiffy =
568			cpufreq_scale(cpu_data(0).loops_per_jiffy,
569					cpu_khz_old, cpu_khz);
570		return 0;
571	} else
572		return -ENODEV;
573#else
574	return -ENODEV;
575#endif
576}
577
578EXPORT_SYMBOL(recalibrate_cpu_khz);
579
580
581/* Accelerators for sched_clock()
582 * convert from cycles(64bits) => nanoseconds (64bits)
583 *  basic equation:
584 *              ns = cycles / (freq / ns_per_sec)
585 *              ns = cycles * (ns_per_sec / freq)
586 *              ns = cycles * (10^9 / (cpu_khz * 10^3))
587 *              ns = cycles * (10^6 / cpu_khz)
588 *
589 *      Then we use scaling math (suggested by george@mvista.com) to get:
590 *              ns = cycles * (10^6 * SC / cpu_khz) / SC
591 *              ns = cycles * cyc2ns_scale / SC
592 *
593 *      And since SC is a constant power of two, we can convert the div
594 *  into a shift.
595 *
596 *  We can use khz divisor instead of mhz to keep a better precision, since
597 *  cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
598 *  (mathieu.desnoyers@polymtl.ca)
599 *
600 *                      -johnstul@us.ibm.com "math is hard, lets go shopping!"
601 */
602
603DEFINE_PER_CPU(unsigned long, cyc2ns);
604DEFINE_PER_CPU(unsigned long long, cyc2ns_offset);
605
606static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
607{
608	unsigned long long tsc_now, ns_now, *offset;
609	unsigned long flags, *scale;
610
611	local_irq_save(flags);
612	sched_clock_idle_sleep_event();
613
614	scale = &per_cpu(cyc2ns, cpu);
615	offset = &per_cpu(cyc2ns_offset, cpu);
616
617	rdtscll(tsc_now);
618	ns_now = __cycles_2_ns(tsc_now);
619
620	if (cpu_khz) {
621		*scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
622		*offset = ns_now - (tsc_now * *scale >> CYC2NS_SCALE_FACTOR);
623	}
624
625	sched_clock_idle_wakeup_event(0);
626	local_irq_restore(flags);
627}
628
629static unsigned long long cyc2ns_suspend;
630
631void save_sched_clock_state(void)
632{
633	if (!sched_clock_stable)
634		return;
635
636	cyc2ns_suspend = sched_clock();
637}
638
639/*
640 * Even on processors with invariant TSC, TSC gets reset in some the
641 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
642 * arbitrary value (still sync'd across cpu's) during resume from such sleep
643 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
644 * that sched_clock() continues from the point where it was left off during
645 * suspend.
646 */
647void restore_sched_clock_state(void)
648{
649	unsigned long long offset;
650	unsigned long flags;
651	int cpu;
652
653	if (!sched_clock_stable)
654		return;
655
656	local_irq_save(flags);
657
658	__get_cpu_var(cyc2ns_offset) = 0;
659	offset = cyc2ns_suspend - sched_clock();
660
661	for_each_possible_cpu(cpu)
662		per_cpu(cyc2ns_offset, cpu) = offset;
663
664	local_irq_restore(flags);
665}
666
667#ifdef CONFIG_CPU_FREQ
668
669/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
670 * changes.
671 *
672 * RED-PEN: On SMP we assume all CPUs run with the same frequency.  It's
673 * not that important because current Opteron setups do not support
674 * scaling on SMP anyroads.
675 *
676 * Should fix up last_tsc too. Currently gettimeofday in the
677 * first tick after the change will be slightly wrong.
678 */
679
680static unsigned int  ref_freq;
681static unsigned long loops_per_jiffy_ref;
682static unsigned long tsc_khz_ref;
683
684static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
685				void *data)
686{
687	struct cpufreq_freqs *freq = data;
688	unsigned long *lpj;
689
690	if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
691		return 0;
692
693	lpj = &boot_cpu_data.loops_per_jiffy;
694#ifdef CONFIG_SMP
695	if (!(freq->flags & CPUFREQ_CONST_LOOPS))
696		lpj = &cpu_data(freq->cpu).loops_per_jiffy;
697#endif
698
699	if (!ref_freq) {
700		ref_freq = freq->old;
701		loops_per_jiffy_ref = *lpj;
702		tsc_khz_ref = tsc_khz;
703	}
704	if ((val == CPUFREQ_PRECHANGE  && freq->old < freq->new) ||
705			(val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
706			(val == CPUFREQ_RESUMECHANGE)) {
707		*lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
708
709		tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
710		if (!(freq->flags & CPUFREQ_CONST_LOOPS))
711			mark_tsc_unstable("cpufreq changes");
712	}
713
714	set_cyc2ns_scale(tsc_khz, freq->cpu);
715
716	return 0;
717}
718
719static struct notifier_block time_cpufreq_notifier_block = {
720	.notifier_call  = time_cpufreq_notifier
721};
722
723static int __init cpufreq_tsc(void)
724{
725	if (!cpu_has_tsc)
726		return 0;
727	if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
728		return 0;
729	cpufreq_register_notifier(&time_cpufreq_notifier_block,
730				CPUFREQ_TRANSITION_NOTIFIER);
731	return 0;
732}
733
734core_initcall(cpufreq_tsc);
735
736#endif /* CONFIG_CPU_FREQ */
737
738/* clocksource code */
739
740static struct clocksource clocksource_tsc;
741
742/*
743 * We compare the TSC to the cycle_last value in the clocksource
744 * structure to avoid a nasty time-warp. This can be observed in a
745 * very small window right after one CPU updated cycle_last under
746 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
747 * is smaller than the cycle_last reference value due to a TSC which
748 * is slighty behind. This delta is nowhere else observable, but in
749 * that case it results in a forward time jump in the range of hours
750 * due to the unsigned delta calculation of the time keeping core
751 * code, which is necessary to support wrapping clocksources like pm
752 * timer.
753 */
754static cycle_t read_tsc(struct clocksource *cs)
755{
756	cycle_t ret = (cycle_t)get_cycles();
757
758	return ret >= clocksource_tsc.cycle_last ?
759		ret : clocksource_tsc.cycle_last;
760}
761
762#ifdef CONFIG_X86_64
763static cycle_t __vsyscall_fn vread_tsc(void)
764{
765	cycle_t ret;
766
767	/*
768	 * Surround the RDTSC by barriers, to make sure it's not
769	 * speculated to outside the seqlock critical section and
770	 * does not cause time warps:
771	 */
772	rdtsc_barrier();
773	ret = (cycle_t)vget_cycles();
774	rdtsc_barrier();
775
776	return ret >= __vsyscall_gtod_data.clock.cycle_last ?
777		ret : __vsyscall_gtod_data.clock.cycle_last;
778}
779#endif
780
781static void resume_tsc(struct clocksource *cs)
782{
783	clocksource_tsc.cycle_last = 0;
784}
785
786static struct clocksource clocksource_tsc = {
787	.name                   = "tsc",
788	.rating                 = 300,
789	.read                   = read_tsc,
790	.resume			= resume_tsc,
791	.mask                   = CLOCKSOURCE_MASK(64),
792	.flags                  = CLOCK_SOURCE_IS_CONTINUOUS |
793				  CLOCK_SOURCE_MUST_VERIFY,
794#ifdef CONFIG_X86_64
795	.vread                  = vread_tsc,
796#endif
797};
798
799void mark_tsc_unstable(char *reason)
800{
801	if (!tsc_unstable) {
802		tsc_unstable = 1;
803		sched_clock_stable = 0;
804		printk(KERN_INFO "Marking TSC unstable due to %s\n", reason);
805		/* Change only the rating, when not registered */
806		if (clocksource_tsc.mult)
807			clocksource_mark_unstable(&clocksource_tsc);
808		else {
809			clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
810			clocksource_tsc.rating = 0;
811		}
812	}
813}
814
815EXPORT_SYMBOL_GPL(mark_tsc_unstable);
816
817static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d)
818{
819	printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
820			d->ident);
821	tsc_unstable = 1;
822	return 0;
823}
824
825/* List of systems that have known TSC problems */
826static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
827	{
828		.callback = dmi_mark_tsc_unstable,
829		.ident = "IBM Thinkpad 380XD",
830		.matches = {
831			DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
832			DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
833		},
834	},
835	{}
836};
837
838static void __init check_system_tsc_reliable(void)
839{
840#ifdef CONFIG_MGEODE_LX
841	/* RTSC counts during suspend */
842#define RTSC_SUSP 0x100
843	unsigned long res_low, res_high;
844
845	rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
846	/* Geode_LX - the OLPC CPU has a very reliable TSC */
847	if (res_low & RTSC_SUSP)
848		tsc_clocksource_reliable = 1;
849#endif
850	if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
851		tsc_clocksource_reliable = 1;
852}
853
854/*
855 * Make an educated guess if the TSC is trustworthy and synchronized
856 * over all CPUs.
857 */
858__cpuinit int unsynchronized_tsc(void)
859{
860	if (!cpu_has_tsc || tsc_unstable)
861		return 1;
862
863#ifdef CONFIG_SMP
864	if (apic_is_clustered_box())
865		return 1;
866#endif
867
868	if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
869		return 0;
870	/*
871	 * Intel systems are normally all synchronized.
872	 * Exceptions must mark TSC as unstable:
873	 */
874	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
875		/* assume multi socket systems are not synchronized: */
876		if (num_possible_cpus() > 1)
877			tsc_unstable = 1;
878	}
879
880	return tsc_unstable;
881}
882
883static void __init init_tsc_clocksource(void)
884{
885	if (tsc_clocksource_reliable)
886		clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
887	/* lower the rating if we already know its unstable: */
888	if (check_tsc_unstable()) {
889		clocksource_tsc.rating = 0;
890		clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
891	}
892	clocksource_register_khz(&clocksource_tsc, tsc_khz);
893}
894
895#ifdef CONFIG_X86_64
896/*
897 * calibrate_cpu is used on systems with fixed rate TSCs to determine
898 * processor frequency
899 */
900#define TICK_COUNT 100000000
901static unsigned long __init calibrate_cpu(void)
902{
903	int tsc_start, tsc_now;
904	int i, no_ctr_free;
905	unsigned long evntsel3 = 0, pmc3 = 0, pmc_now = 0;
906	unsigned long flags;
907
908	for (i = 0; i < 4; i++)
909		if (avail_to_resrv_perfctr_nmi_bit(i))
910			break;
911	no_ctr_free = (i == 4);
912	if (no_ctr_free) {
913		WARN(1, KERN_WARNING "Warning: AMD perfctrs busy ... "
914		     "cpu_khz value may be incorrect.\n");
915		i = 3;
916		rdmsrl(MSR_K7_EVNTSEL3, evntsel3);
917		wrmsrl(MSR_K7_EVNTSEL3, 0);
918		rdmsrl(MSR_K7_PERFCTR3, pmc3);
919	} else {
920		reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i);
921		reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
922	}
923	local_irq_save(flags);
924	/* start measuring cycles, incrementing from 0 */
925	wrmsrl(MSR_K7_PERFCTR0 + i, 0);
926	wrmsrl(MSR_K7_EVNTSEL0 + i, 1 << 22 | 3 << 16 | 0x76);
927	rdtscl(tsc_start);
928	do {
929		rdmsrl(MSR_K7_PERFCTR0 + i, pmc_now);
930		tsc_now = get_cycles();
931	} while ((tsc_now - tsc_start) < TICK_COUNT);
932
933	local_irq_restore(flags);
934	if (no_ctr_free) {
935		wrmsrl(MSR_K7_EVNTSEL3, 0);
936		wrmsrl(MSR_K7_PERFCTR3, pmc3);
937		wrmsrl(MSR_K7_EVNTSEL3, evntsel3);
938	} else {
939		release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
940		release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
941	}
942
943	return pmc_now * tsc_khz / (tsc_now - tsc_start);
944}
945#else
946static inline unsigned long calibrate_cpu(void) { return cpu_khz; }
947#endif
948
949void __init tsc_init(void)
950{
951	u64 lpj;
952	int cpu;
953
954	x86_init.timers.tsc_pre_init();
955
956	if (!cpu_has_tsc)
957		return;
958
959	tsc_khz = x86_platform.calibrate_tsc();
960	cpu_khz = tsc_khz;
961
962	if (!tsc_khz) {
963		mark_tsc_unstable("could not calculate TSC khz");
964		return;
965	}
966
967	if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
968			(boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
969		cpu_khz = calibrate_cpu();
970
971	printk("Detected %lu.%03lu MHz processor.\n",
972			(unsigned long)cpu_khz / 1000,
973			(unsigned long)cpu_khz % 1000);
974
975	/*
976	 * Secondary CPUs do not run through tsc_init(), so set up
977	 * all the scale factors for all CPUs, assuming the same
978	 * speed as the bootup CPU. (cpufreq notifiers will fix this
979	 * up if their speed diverges)
980	 */
981	for_each_possible_cpu(cpu)
982		set_cyc2ns_scale(cpu_khz, cpu);
983
984	if (tsc_disabled > 0)
985		return;
986
987	/* now allow native_sched_clock() to use rdtsc */
988	tsc_disabled = 0;
989
990	lpj = ((u64)tsc_khz * 1000);
991	do_div(lpj, HZ);
992	lpj_fine = lpj;
993
994	use_tsc_delay();
995	/* Check and install the TSC clocksource */
996	dmi_check_system(bad_tsc_dmi_table);
997
998	if (unsynchronized_tsc())
999		mark_tsc_unstable("TSCs unsynchronized");
1000
1001	check_system_tsc_reliable();
1002	init_tsc_clocksource();
1003}
1004