1/* Various workarounds for chipset bugs. 2 This code runs very early and can't use the regular PCI subsystem 3 The entries are keyed to PCI bridges which usually identify chipsets 4 uniquely. 5 This is only for whole classes of chipsets with specific problems which 6 need early invasive action (e.g. before the timers are initialized). 7 Most PCI device specific workarounds can be done later and should be 8 in standard PCI quirks 9 Mainboard specific bugs should be handled by DMI entries. 10 CPU specific bugs in setup.c */ 11 12#include <linux/pci.h> 13#include <linux/acpi.h> 14#include <linux/pci_ids.h> 15#include <asm/pci-direct.h> 16#include <asm/dma.h> 17#include <asm/io_apic.h> 18#include <asm/apic.h> 19#include <asm/iommu.h> 20#include <asm/gart.h> 21 22static void __init fix_hypertransport_config(int num, int slot, int func) 23{ 24 u32 htcfg; 25 /* 26 * we found a hypertransport bus 27 * make sure that we are broadcasting 28 * interrupts to all cpus on the ht bus 29 * if we're using extended apic ids 30 */ 31 htcfg = read_pci_config(num, slot, func, 0x68); 32 if (htcfg & (1 << 18)) { 33 printk(KERN_INFO "Detected use of extended apic ids " 34 "on hypertransport bus\n"); 35 if ((htcfg & (1 << 17)) == 0) { 36 printk(KERN_INFO "Enabling hypertransport extended " 37 "apic interrupt broadcast\n"); 38 printk(KERN_INFO "Note this is a bios bug, " 39 "please contact your hw vendor\n"); 40 htcfg |= (1 << 17); 41 write_pci_config(num, slot, func, 0x68, htcfg); 42 } 43 } 44 45 46} 47 48static void __init via_bugs(int num, int slot, int func) 49{ 50#ifdef CONFIG_GART_IOMMU 51 if ((max_pfn > MAX_DMA32_PFN || force_iommu) && 52 !gart_iommu_aperture_allowed) { 53 printk(KERN_INFO 54 "Looks like a VIA chipset. Disabling IOMMU." 55 " Override with iommu=allowed\n"); 56 gart_iommu_aperture_disabled = 1; 57 } 58#endif 59} 60 61#ifdef CONFIG_ACPI 62#ifdef CONFIG_X86_IO_APIC 63 64static int __init nvidia_hpet_check(struct acpi_table_header *header) 65{ 66 return 0; 67} 68#endif /* CONFIG_X86_IO_APIC */ 69#endif /* CONFIG_ACPI */ 70 71static void __init nvidia_bugs(int num, int slot, int func) 72{ 73#ifdef CONFIG_ACPI 74#ifdef CONFIG_X86_IO_APIC 75 /* 76 * All timer overrides on Nvidia are 77 * wrong unless HPET is enabled. 78 * Unfortunately that's not true on many Asus boards. 79 * We don't know yet how to detect this automatically, but 80 * at least allow a command line override. 81 */ 82 if (acpi_use_timer_override) 83 return; 84 85 if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) { 86 acpi_skip_timer_override = 1; 87 printk(KERN_INFO "Nvidia board " 88 "detected. Ignoring ACPI " 89 "timer override.\n"); 90 printk(KERN_INFO "If you got timer trouble " 91 "try acpi_use_timer_override\n"); 92 } 93#endif 94#endif 95 /* RED-PEN skip them on mptables too? */ 96 97} 98 99#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC) 100#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC) 101static u32 __init ati_ixp4x0_rev(int num, int slot, int func) 102{ 103 u32 d; 104 u8 b; 105 106 b = read_pci_config_byte(num, slot, func, 0xac); 107 b &= ~(1<<5); 108 write_pci_config_byte(num, slot, func, 0xac, b); 109 110 d = read_pci_config(num, slot, func, 0x70); 111 d |= 1<<8; 112 write_pci_config(num, slot, func, 0x70, d); 113 114 d = read_pci_config(num, slot, func, 0x8); 115 d &= 0xff; 116 return d; 117} 118#endif 119 120static void __init ati_bugs(int num, int slot, int func) 121{ 122 u32 d; 123 u8 b; 124 125 if (acpi_use_timer_override) 126 return; 127 128 d = ati_ixp4x0_rev(num, slot, func); 129 if (d < 0x82) 130 acpi_skip_timer_override = 1; 131 else { 132 /* check for IRQ0 interrupt swap */ 133 outb(0x72, 0xcd6); b = inb(0xcd7); 134 if (!(b & 0x2)) 135 acpi_skip_timer_override = 1; 136 } 137 138 if (acpi_skip_timer_override) { 139 printk(KERN_INFO "SB4X0 revision 0x%x\n", d); 140 printk(KERN_INFO "Ignoring ACPI timer override.\n"); 141 printk(KERN_INFO "If you got timer trouble " 142 "try acpi_use_timer_override\n"); 143 } 144} 145 146static u32 __init ati_sbx00_rev(int num, int slot, int func) 147{ 148 u32 old, d; 149 150 d = read_pci_config(num, slot, func, 0x70); 151 old = d; 152 d &= ~(1<<8); 153 write_pci_config(num, slot, func, 0x70, d); 154 d = read_pci_config(num, slot, func, 0x8); 155 d &= 0xff; 156 write_pci_config(num, slot, func, 0x70, old); 157 158 return d; 159} 160 161static void __init ati_bugs_contd(int num, int slot, int func) 162{ 163 u32 d, rev; 164 165 if (acpi_use_timer_override) 166 return; 167 168 rev = ati_sbx00_rev(num, slot, func); 169 if (rev > 0x13) 170 return; 171 172 /* check for IRQ0 interrupt swap */ 173 d = read_pci_config(num, slot, func, 0x64); 174 if (!(d & (1<<14))) 175 acpi_skip_timer_override = 1; 176 177 if (acpi_skip_timer_override) { 178 printk(KERN_INFO "SB600 revision 0x%x\n", rev); 179 printk(KERN_INFO "Ignoring ACPI timer override.\n"); 180 printk(KERN_INFO "If you got timer trouble " 181 "try acpi_use_timer_override\n"); 182 } 183} 184#else 185static void __init ati_bugs(int num, int slot, int func) 186{ 187} 188 189static void __init ati_bugs_contd(int num, int slot, int func) 190{ 191} 192#endif 193 194#define QFLAG_APPLY_ONCE 0x1 195#define QFLAG_APPLIED 0x2 196#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED) 197struct chipset { 198 u32 vendor; 199 u32 device; 200 u32 class; 201 u32 class_mask; 202 u32 flags; 203 void (*f)(int num, int slot, int func); 204}; 205 206/* 207 * Only works for devices on the root bus. If you add any devices 208 * not on bus 0 readd another loop level in early_quirks(). But 209 * be careful because at least the Nvidia quirk here relies on 210 * only matching on bus 0. 211 */ 212static struct chipset early_qrk[] __initdata = { 213 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 214 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs }, 215 { PCI_VENDOR_ID_VIA, PCI_ANY_ID, 216 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs }, 217 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB, 218 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config }, 219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS, 220 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs }, 221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 222 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd }, 223 {} 224}; 225 226/** 227 * check_dev_quirk - apply early quirks to a given PCI device 228 * @num: bus number 229 * @slot: slot number 230 * @func: PCI function 231 * 232 * Check the vendor & device ID against the early quirks table. 233 * 234 * If the device is single function, let early_quirks() know so we don't 235 * poke at this device again. 236 */ 237static int __init check_dev_quirk(int num, int slot, int func) 238{ 239 u16 class; 240 u16 vendor; 241 u16 device; 242 u8 type; 243 int i; 244 245 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE); 246 247 if (class == 0xffff) 248 return -1; /* no class, treat as single function */ 249 250 vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID); 251 252 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID); 253 254 for (i = 0; early_qrk[i].f != NULL; i++) { 255 if (((early_qrk[i].vendor == PCI_ANY_ID) || 256 (early_qrk[i].vendor == vendor)) && 257 ((early_qrk[i].device == PCI_ANY_ID) || 258 (early_qrk[i].device == device)) && 259 (!((early_qrk[i].class ^ class) & 260 early_qrk[i].class_mask))) { 261 if ((early_qrk[i].flags & 262 QFLAG_DONE) != QFLAG_DONE) 263 early_qrk[i].f(num, slot, func); 264 early_qrk[i].flags |= QFLAG_APPLIED; 265 } 266 } 267 268 type = read_pci_config_byte(num, slot, func, 269 PCI_HEADER_TYPE); 270 if (!(type & 0x80)) 271 return -1; 272 273 return 0; 274} 275 276void __init early_quirks(void) 277{ 278 int slot, func; 279 280 if (!early_pci_allowed()) 281 return; 282 283 /* Poor man's PCI discovery */ 284 /* Only scan the root bus */ 285 for (slot = 0; slot < 32; slot++) 286 for (func = 0; func < 8; func++) { 287 /* Only probe function 0 on single fn devices */ 288 if (check_dev_quirk(0, slot, func)) 289 break; 290 } 291} 292