1/* 2 * Netburst Perfomance Events (P4, old Xeon) 3 */ 4 5#ifndef PERF_EVENT_P4_H 6#define PERF_EVENT_P4_H 7 8#include <linux/cpu.h> 9#include <linux/bitops.h> 10 11/* 12 * NetBurst has perfomance MSRs shared between 13 * threads if HT is turned on, ie for both logical 14 * processors (mem: in turn in Atom with HT support 15 * perf-MSRs are not shared and every thread has its 16 * own perf-MSRs set) 17 */ 18#define ARCH_P4_TOTAL_ESCR (46) 19#define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */ 20#define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR) 21#define ARCH_P4_MAX_CCCR (18) 22 23#define P4_ESCR_EVENT_MASK 0x7e000000U 24#define P4_ESCR_EVENT_SHIFT 25 25#define P4_ESCR_EVENTMASK_MASK 0x01fffe00U 26#define P4_ESCR_EVENTMASK_SHIFT 9 27#define P4_ESCR_TAG_MASK 0x000001e0U 28#define P4_ESCR_TAG_SHIFT 5 29#define P4_ESCR_TAG_ENABLE 0x00000010U 30#define P4_ESCR_T0_OS 0x00000008U 31#define P4_ESCR_T0_USR 0x00000004U 32#define P4_ESCR_T1_OS 0x00000002U 33#define P4_ESCR_T1_USR 0x00000001U 34 35#define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT) 36#define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT) 37#define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT) 38 39/* Non HT mask */ 40#define P4_ESCR_MASK \ 41 (P4_ESCR_EVENT_MASK | \ 42 P4_ESCR_EVENTMASK_MASK | \ 43 P4_ESCR_TAG_MASK | \ 44 P4_ESCR_TAG_ENABLE | \ 45 P4_ESCR_T0_OS | \ 46 P4_ESCR_T0_USR) 47 48/* HT mask */ 49#define P4_ESCR_MASK_HT \ 50 (P4_ESCR_MASK | P4_ESCR_T1_OS | P4_ESCR_T1_USR) 51 52#define P4_CCCR_OVF 0x80000000U 53#define P4_CCCR_CASCADE 0x40000000U 54#define P4_CCCR_OVF_PMI_T0 0x04000000U 55#define P4_CCCR_OVF_PMI_T1 0x08000000U 56#define P4_CCCR_FORCE_OVF 0x02000000U 57#define P4_CCCR_EDGE 0x01000000U 58#define P4_CCCR_THRESHOLD_MASK 0x00f00000U 59#define P4_CCCR_THRESHOLD_SHIFT 20 60#define P4_CCCR_COMPLEMENT 0x00080000U 61#define P4_CCCR_COMPARE 0x00040000U 62#define P4_CCCR_ESCR_SELECT_MASK 0x0000e000U 63#define P4_CCCR_ESCR_SELECT_SHIFT 13 64#define P4_CCCR_ENABLE 0x00001000U 65#define P4_CCCR_THREAD_SINGLE 0x00010000U 66#define P4_CCCR_THREAD_BOTH 0x00020000U 67#define P4_CCCR_THREAD_ANY 0x00030000U 68#define P4_CCCR_RESERVED 0x00000fffU 69 70#define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT) 71#define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT) 72 73/* Non HT mask */ 74#define P4_CCCR_MASK \ 75 (P4_CCCR_OVF | \ 76 P4_CCCR_CASCADE | \ 77 P4_CCCR_OVF_PMI_T0 | \ 78 P4_CCCR_FORCE_OVF | \ 79 P4_CCCR_EDGE | \ 80 P4_CCCR_THRESHOLD_MASK | \ 81 P4_CCCR_COMPLEMENT | \ 82 P4_CCCR_COMPARE | \ 83 P4_CCCR_ESCR_SELECT_MASK | \ 84 P4_CCCR_ENABLE) 85 86/* HT mask */ 87#define P4_CCCR_MASK_HT \ 88 (P4_CCCR_MASK | P4_CCCR_OVF_PMI_T1 | P4_CCCR_THREAD_ANY) 89 90#define P4_GEN_ESCR_EMASK(class, name, bit) \ 91 class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT) 92#define P4_ESCR_EMASK_BIT(class, name) class##__##name 93 94/* 95 * config field is 64bit width and consists of 96 * HT << 63 | ESCR << 32 | CCCR 97 * where HT is HyperThreading bit (since ESCR 98 * has it reserved we may use it for own purpose) 99 * 100 * note that this is NOT the addresses of respective 101 * ESCR and CCCR but rather an only packed value should 102 * be unpacked and written to a proper addresses 103 * 104 * the base idea is to pack as much info as possible 105 */ 106#define p4_config_pack_escr(v) (((u64)(v)) << 32) 107#define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL) 108#define p4_config_unpack_escr(v) (((u64)(v)) >> 32) 109#define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL) 110 111#define p4_config_unpack_emask(v) \ 112 ({ \ 113 u32 t = p4_config_unpack_escr((v)); \ 114 t = t & P4_ESCR_EVENTMASK_MASK; \ 115 t = t >> P4_ESCR_EVENTMASK_SHIFT; \ 116 t; \ 117 }) 118 119#define p4_config_unpack_event(v) \ 120 ({ \ 121 u32 t = p4_config_unpack_escr((v)); \ 122 t = t & P4_ESCR_EVENT_MASK; \ 123 t = t >> P4_ESCR_EVENT_SHIFT; \ 124 t; \ 125 }) 126 127#define P4_CONFIG_HT_SHIFT 63 128#define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT) 129 130static inline bool p4_is_event_cascaded(u64 config) 131{ 132 u32 cccr = p4_config_unpack_cccr(config); 133 return !!(cccr & P4_CCCR_CASCADE); 134} 135 136static inline int p4_ht_config_thread(u64 config) 137{ 138 return !!(config & P4_CONFIG_HT); 139} 140 141static inline u64 p4_set_ht_bit(u64 config) 142{ 143 return config | P4_CONFIG_HT; 144} 145 146static inline u64 p4_clear_ht_bit(u64 config) 147{ 148 return config & ~P4_CONFIG_HT; 149} 150 151static inline int p4_ht_active(void) 152{ 153#ifdef CONFIG_SMP 154 return smp_num_siblings > 1; 155#endif 156 return 0; 157} 158 159static inline int p4_ht_thread(int cpu) 160{ 161#ifdef CONFIG_SMP 162 if (smp_num_siblings == 2) 163 return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map)); 164#endif 165 return 0; 166} 167 168static inline int p4_should_swap_ts(u64 config, int cpu) 169{ 170 return p4_ht_config_thread(config) ^ p4_ht_thread(cpu); 171} 172 173static inline u32 p4_default_cccr_conf(int cpu) 174{ 175 /* 176 * Note that P4_CCCR_THREAD_ANY is "required" on 177 * non-HT machines (on HT machines we count TS events 178 * regardless the state of second logical processor 179 */ 180 u32 cccr = P4_CCCR_THREAD_ANY; 181 182 if (!p4_ht_thread(cpu)) 183 cccr |= P4_CCCR_OVF_PMI_T0; 184 else 185 cccr |= P4_CCCR_OVF_PMI_T1; 186 187 return cccr; 188} 189 190static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr) 191{ 192 u32 escr = 0; 193 194 if (!p4_ht_thread(cpu)) { 195 if (!exclude_os) 196 escr |= P4_ESCR_T0_OS; 197 if (!exclude_usr) 198 escr |= P4_ESCR_T0_USR; 199 } else { 200 if (!exclude_os) 201 escr |= P4_ESCR_T1_OS; 202 if (!exclude_usr) 203 escr |= P4_ESCR_T1_USR; 204 } 205 206 return escr; 207} 208 209/* 210 * This are the events which should be used in "Event Select" 211 * field of ESCR register, they are like unique keys which allow 212 * the kernel to determinate which CCCR and COUNTER should be 213 * used to track an event 214 */ 215enum P4_EVENTS { 216 P4_EVENT_TC_DELIVER_MODE, 217 P4_EVENT_BPU_FETCH_REQUEST, 218 P4_EVENT_ITLB_REFERENCE, 219 P4_EVENT_MEMORY_CANCEL, 220 P4_EVENT_MEMORY_COMPLETE, 221 P4_EVENT_LOAD_PORT_REPLAY, 222 P4_EVENT_STORE_PORT_REPLAY, 223 P4_EVENT_MOB_LOAD_REPLAY, 224 P4_EVENT_PAGE_WALK_TYPE, 225 P4_EVENT_BSQ_CACHE_REFERENCE, 226 P4_EVENT_IOQ_ALLOCATION, 227 P4_EVENT_IOQ_ACTIVE_ENTRIES, 228 P4_EVENT_FSB_DATA_ACTIVITY, 229 P4_EVENT_BSQ_ALLOCATION, 230 P4_EVENT_BSQ_ACTIVE_ENTRIES, 231 P4_EVENT_SSE_INPUT_ASSIST, 232 P4_EVENT_PACKED_SP_UOP, 233 P4_EVENT_PACKED_DP_UOP, 234 P4_EVENT_SCALAR_SP_UOP, 235 P4_EVENT_SCALAR_DP_UOP, 236 P4_EVENT_64BIT_MMX_UOP, 237 P4_EVENT_128BIT_MMX_UOP, 238 P4_EVENT_X87_FP_UOP, 239 P4_EVENT_TC_MISC, 240 P4_EVENT_GLOBAL_POWER_EVENTS, 241 P4_EVENT_TC_MS_XFER, 242 P4_EVENT_UOP_QUEUE_WRITES, 243 P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, 244 P4_EVENT_RETIRED_BRANCH_TYPE, 245 P4_EVENT_RESOURCE_STALL, 246 P4_EVENT_WC_BUFFER, 247 P4_EVENT_B2B_CYCLES, 248 P4_EVENT_BNR, 249 P4_EVENT_SNOOP, 250 P4_EVENT_RESPONSE, 251 P4_EVENT_FRONT_END_EVENT, 252 P4_EVENT_EXECUTION_EVENT, 253 P4_EVENT_REPLAY_EVENT, 254 P4_EVENT_INSTR_RETIRED, 255 P4_EVENT_UOPS_RETIRED, 256 P4_EVENT_UOP_TYPE, 257 P4_EVENT_BRANCH_RETIRED, 258 P4_EVENT_MISPRED_BRANCH_RETIRED, 259 P4_EVENT_X87_ASSIST, 260 P4_EVENT_MACHINE_CLEAR, 261 P4_EVENT_INSTR_COMPLETED, 262}; 263 264#define P4_OPCODE(event) event##_OPCODE 265#define P4_OPCODE_ESEL(opcode) ((opcode & 0x00ff) >> 0) 266#define P4_OPCODE_EVNT(opcode) ((opcode & 0xff00) >> 8) 267#define P4_OPCODE_PACK(event, sel) (((event) << 8) | sel) 268 269/* 270 * Comments below the event represent ESCR restriction 271 * for this event and counter index per ESCR 272 * 273 * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early 274 * processor builds (family 0FH, models 01H-02H). These MSRs 275 * are not available on later versions, so that we don't use 276 * them completely 277 * 278 * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly 279 * working so that we should not use this CCCR and respective 280 * counter as result 281 */ 282enum P4_EVENT_OPCODES { 283 P4_OPCODE(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), 284 /* 285 * MSR_P4_TC_ESCR0: 4, 5 286 * MSR_P4_TC_ESCR1: 6, 7 287 */ 288 289 P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST) = P4_OPCODE_PACK(0x03, 0x00), 290 /* 291 * MSR_P4_BPU_ESCR0: 0, 1 292 * MSR_P4_BPU_ESCR1: 2, 3 293 */ 294 295 P4_OPCODE(P4_EVENT_ITLB_REFERENCE) = P4_OPCODE_PACK(0x18, 0x03), 296 /* 297 * MSR_P4_ITLB_ESCR0: 0, 1 298 * MSR_P4_ITLB_ESCR1: 2, 3 299 */ 300 301 P4_OPCODE(P4_EVENT_MEMORY_CANCEL) = P4_OPCODE_PACK(0x02, 0x05), 302 /* 303 * MSR_P4_DAC_ESCR0: 8, 9 304 * MSR_P4_DAC_ESCR1: 10, 11 305 */ 306 307 P4_OPCODE(P4_EVENT_MEMORY_COMPLETE) = P4_OPCODE_PACK(0x08, 0x02), 308 /* 309 * MSR_P4_SAAT_ESCR0: 8, 9 310 * MSR_P4_SAAT_ESCR1: 10, 11 311 */ 312 313 P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY) = P4_OPCODE_PACK(0x04, 0x02), 314 /* 315 * MSR_P4_SAAT_ESCR0: 8, 9 316 * MSR_P4_SAAT_ESCR1: 10, 11 317 */ 318 319 P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY) = P4_OPCODE_PACK(0x05, 0x02), 320 /* 321 * MSR_P4_SAAT_ESCR0: 8, 9 322 * MSR_P4_SAAT_ESCR1: 10, 11 323 */ 324 325 P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY) = P4_OPCODE_PACK(0x03, 0x02), 326 /* 327 * MSR_P4_MOB_ESCR0: 0, 1 328 * MSR_P4_MOB_ESCR1: 2, 3 329 */ 330 331 P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE) = P4_OPCODE_PACK(0x01, 0x04), 332 /* 333 * MSR_P4_PMH_ESCR0: 0, 1 334 * MSR_P4_PMH_ESCR1: 2, 3 335 */ 336 337 P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE) = P4_OPCODE_PACK(0x0c, 0x07), 338 /* 339 * MSR_P4_BSU_ESCR0: 0, 1 340 * MSR_P4_BSU_ESCR1: 2, 3 341 */ 342 343 P4_OPCODE(P4_EVENT_IOQ_ALLOCATION) = P4_OPCODE_PACK(0x03, 0x06), 344 /* 345 * MSR_P4_FSB_ESCR0: 0, 1 346 * MSR_P4_FSB_ESCR1: 2, 3 347 */ 348 349 P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x1a, 0x06), 350 /* 351 * MSR_P4_FSB_ESCR1: 2, 3 352 */ 353 354 P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY) = P4_OPCODE_PACK(0x17, 0x06), 355 /* 356 * MSR_P4_FSB_ESCR0: 0, 1 357 * MSR_P4_FSB_ESCR1: 2, 3 358 */ 359 360 P4_OPCODE(P4_EVENT_BSQ_ALLOCATION) = P4_OPCODE_PACK(0x05, 0x07), 361 /* 362 * MSR_P4_BSU_ESCR0: 0, 1 363 */ 364 365 P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x06, 0x07), 366 /* 367 * NOTE: no ESCR name in docs, it's guessed 368 * MSR_P4_BSU_ESCR1: 2, 3 369 */ 370 371 P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST) = P4_OPCODE_PACK(0x34, 0x01), 372 /* 373 * MSR_P4_FIRM_ESCR0: 8, 9 374 * MSR_P4_FIRM_ESCR1: 10, 11 375 */ 376 377 P4_OPCODE(P4_EVENT_PACKED_SP_UOP) = P4_OPCODE_PACK(0x08, 0x01), 378 /* 379 * MSR_P4_FIRM_ESCR0: 8, 9 380 * MSR_P4_FIRM_ESCR1: 10, 11 381 */ 382 383 P4_OPCODE(P4_EVENT_PACKED_DP_UOP) = P4_OPCODE_PACK(0x0c, 0x01), 384 /* 385 * MSR_P4_FIRM_ESCR0: 8, 9 386 * MSR_P4_FIRM_ESCR1: 10, 11 387 */ 388 389 P4_OPCODE(P4_EVENT_SCALAR_SP_UOP) = P4_OPCODE_PACK(0x0a, 0x01), 390 /* 391 * MSR_P4_FIRM_ESCR0: 8, 9 392 * MSR_P4_FIRM_ESCR1: 10, 11 393 */ 394 395 P4_OPCODE(P4_EVENT_SCALAR_DP_UOP) = P4_OPCODE_PACK(0x0e, 0x01), 396 /* 397 * MSR_P4_FIRM_ESCR0: 8, 9 398 * MSR_P4_FIRM_ESCR1: 10, 11 399 */ 400 401 P4_OPCODE(P4_EVENT_64BIT_MMX_UOP) = P4_OPCODE_PACK(0x02, 0x01), 402 /* 403 * MSR_P4_FIRM_ESCR0: 8, 9 404 * MSR_P4_FIRM_ESCR1: 10, 11 405 */ 406 407 P4_OPCODE(P4_EVENT_128BIT_MMX_UOP) = P4_OPCODE_PACK(0x1a, 0x01), 408 /* 409 * MSR_P4_FIRM_ESCR0: 8, 9 410 * MSR_P4_FIRM_ESCR1: 10, 11 411 */ 412 413 P4_OPCODE(P4_EVENT_X87_FP_UOP) = P4_OPCODE_PACK(0x04, 0x01), 414 /* 415 * MSR_P4_FIRM_ESCR0: 8, 9 416 * MSR_P4_FIRM_ESCR1: 10, 11 417 */ 418 419 P4_OPCODE(P4_EVENT_TC_MISC) = P4_OPCODE_PACK(0x06, 0x01), 420 /* 421 * MSR_P4_TC_ESCR0: 4, 5 422 * MSR_P4_TC_ESCR1: 6, 7 423 */ 424 425 P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS) = P4_OPCODE_PACK(0x13, 0x06), 426 /* 427 * MSR_P4_FSB_ESCR0: 0, 1 428 * MSR_P4_FSB_ESCR1: 2, 3 429 */ 430 431 P4_OPCODE(P4_EVENT_TC_MS_XFER) = P4_OPCODE_PACK(0x05, 0x00), 432 /* 433 * MSR_P4_MS_ESCR0: 4, 5 434 * MSR_P4_MS_ESCR1: 6, 7 435 */ 436 437 P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES) = P4_OPCODE_PACK(0x09, 0x00), 438 /* 439 * MSR_P4_MS_ESCR0: 4, 5 440 * MSR_P4_MS_ESCR1: 6, 7 441 */ 442 443 P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x05, 0x02), 444 /* 445 * MSR_P4_TBPU_ESCR0: 4, 5 446 * MSR_P4_TBPU_ESCR1: 6, 7 447 */ 448 449 P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x04, 0x02), 450 /* 451 * MSR_P4_TBPU_ESCR0: 4, 5 452 * MSR_P4_TBPU_ESCR1: 6, 7 453 */ 454 455 P4_OPCODE(P4_EVENT_RESOURCE_STALL) = P4_OPCODE_PACK(0x01, 0x01), 456 /* 457 * MSR_P4_ALF_ESCR0: 12, 13, 16 458 * MSR_P4_ALF_ESCR1: 14, 15, 17 459 */ 460 461 P4_OPCODE(P4_EVENT_WC_BUFFER) = P4_OPCODE_PACK(0x05, 0x05), 462 /* 463 * MSR_P4_DAC_ESCR0: 8, 9 464 * MSR_P4_DAC_ESCR1: 10, 11 465 */ 466 467 P4_OPCODE(P4_EVENT_B2B_CYCLES) = P4_OPCODE_PACK(0x16, 0x03), 468 /* 469 * MSR_P4_FSB_ESCR0: 0, 1 470 * MSR_P4_FSB_ESCR1: 2, 3 471 */ 472 473 P4_OPCODE(P4_EVENT_BNR) = P4_OPCODE_PACK(0x08, 0x03), 474 /* 475 * MSR_P4_FSB_ESCR0: 0, 1 476 * MSR_P4_FSB_ESCR1: 2, 3 477 */ 478 479 P4_OPCODE(P4_EVENT_SNOOP) = P4_OPCODE_PACK(0x06, 0x03), 480 /* 481 * MSR_P4_FSB_ESCR0: 0, 1 482 * MSR_P4_FSB_ESCR1: 2, 3 483 */ 484 485 P4_OPCODE(P4_EVENT_RESPONSE) = P4_OPCODE_PACK(0x04, 0x03), 486 /* 487 * MSR_P4_FSB_ESCR0: 0, 1 488 * MSR_P4_FSB_ESCR1: 2, 3 489 */ 490 491 P4_OPCODE(P4_EVENT_FRONT_END_EVENT) = P4_OPCODE_PACK(0x08, 0x05), 492 /* 493 * MSR_P4_CRU_ESCR2: 12, 13, 16 494 * MSR_P4_CRU_ESCR3: 14, 15, 17 495 */ 496 497 P4_OPCODE(P4_EVENT_EXECUTION_EVENT) = P4_OPCODE_PACK(0x0c, 0x05), 498 /* 499 * MSR_P4_CRU_ESCR2: 12, 13, 16 500 * MSR_P4_CRU_ESCR3: 14, 15, 17 501 */ 502 503 P4_OPCODE(P4_EVENT_REPLAY_EVENT) = P4_OPCODE_PACK(0x09, 0x05), 504 /* 505 * MSR_P4_CRU_ESCR2: 12, 13, 16 506 * MSR_P4_CRU_ESCR3: 14, 15, 17 507 */ 508 509 P4_OPCODE(P4_EVENT_INSTR_RETIRED) = P4_OPCODE_PACK(0x02, 0x04), 510 /* 511 * MSR_P4_CRU_ESCR0: 12, 13, 16 512 * MSR_P4_CRU_ESCR1: 14, 15, 17 513 */ 514 515 P4_OPCODE(P4_EVENT_UOPS_RETIRED) = P4_OPCODE_PACK(0x01, 0x04), 516 /* 517 * MSR_P4_CRU_ESCR0: 12, 13, 16 518 * MSR_P4_CRU_ESCR1: 14, 15, 17 519 */ 520 521 P4_OPCODE(P4_EVENT_UOP_TYPE) = P4_OPCODE_PACK(0x02, 0x02), 522 /* 523 * MSR_P4_RAT_ESCR0: 12, 13, 16 524 * MSR_P4_RAT_ESCR1: 14, 15, 17 525 */ 526 527 P4_OPCODE(P4_EVENT_BRANCH_RETIRED) = P4_OPCODE_PACK(0x06, 0x05), 528 /* 529 * MSR_P4_CRU_ESCR2: 12, 13, 16 530 * MSR_P4_CRU_ESCR3: 14, 15, 17 531 */ 532 533 P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED) = P4_OPCODE_PACK(0x03, 0x04), 534 /* 535 * MSR_P4_CRU_ESCR0: 12, 13, 16 536 * MSR_P4_CRU_ESCR1: 14, 15, 17 537 */ 538 539 P4_OPCODE(P4_EVENT_X87_ASSIST) = P4_OPCODE_PACK(0x03, 0x05), 540 /* 541 * MSR_P4_CRU_ESCR2: 12, 13, 16 542 * MSR_P4_CRU_ESCR3: 14, 15, 17 543 */ 544 545 P4_OPCODE(P4_EVENT_MACHINE_CLEAR) = P4_OPCODE_PACK(0x02, 0x05), 546 /* 547 * MSR_P4_CRU_ESCR2: 12, 13, 16 548 * MSR_P4_CRU_ESCR3: 14, 15, 17 549 */ 550 551 P4_OPCODE(P4_EVENT_INSTR_COMPLETED) = P4_OPCODE_PACK(0x07, 0x04), 552 /* 553 * MSR_P4_CRU_ESCR0: 12, 13, 16 554 * MSR_P4_CRU_ESCR1: 14, 15, 17 555 */ 556}; 557 558/* 559 * a caller should use P4_ESCR_EMASK_NAME helper to 560 * pick the EventMask needed, for example 561 * 562 * P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD) 563 */ 564enum P4_ESCR_EMASKS { 565 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0), 566 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1), 567 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2), 568 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3), 569 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4), 570 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5), 571 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6), 572 573 P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0), 574 575 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0), 576 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1), 577 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2), 578 579 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2), 580 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3), 581 582 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0), 583 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1), 584 585 P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1), 586 587 P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1), 588 589 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1), 590 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3), 591 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4), 592 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5), 593 594 P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0), 595 P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1), 596 597 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0), 598 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1), 599 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2), 600 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3), 601 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4), 602 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5), 603 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8), 604 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9), 605 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10), 606 607 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0), 608 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5), 609 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6), 610 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7), 611 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8), 612 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9), 613 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10), 614 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11), 615 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13), 616 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14), 617 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15), 618 619 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0), 620 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5), 621 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6), 622 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7), 623 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8), 624 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9), 625 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10), 626 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11), 627 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13), 628 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14), 629 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15), 630 631 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0), 632 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1), 633 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2), 634 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3), 635 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4), 636 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5), 637 638 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0), 639 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1), 640 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2), 641 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3), 642 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5), 643 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6), 644 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7), 645 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8), 646 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9), 647 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10), 648 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11), 649 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12), 650 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13), 651 652 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0), 653 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1), 654 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2), 655 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3), 656 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5), 657 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6), 658 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7), 659 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8), 660 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9), 661 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10), 662 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11), 663 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12), 664 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13), 665 666 P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15), 667 668 P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15), 669 670 P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15), 671 672 P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15), 673 674 P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15), 675 676 P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15), 677 678 P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15), 679 680 P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15), 681 682 P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4), 683 684 P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0), 685 686 P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0), 687 688 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0), 689 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1), 690 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2), 691 692 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1), 693 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2), 694 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3), 695 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4), 696 697 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1), 698 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2), 699 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3), 700 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4), 701 702 P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5), 703 704 P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0), 705 P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1), 706 707 P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0), 708 P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1), 709 710 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0), 711 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1), 712 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2), 713 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3), 714 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4), 715 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5), 716 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6), 717 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7), 718 719 P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0), 720 P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1), 721 722 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0), 723 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1), 724 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2), 725 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3), 726 727 P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0), 728 P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1), 729 730 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1), 731 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2), 732 733 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0), 734 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1), 735 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2), 736 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3), 737 738 P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0), 739 740 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0), 741 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1), 742 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2), 743 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3), 744 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4), 745 746 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0), 747 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1), 748 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2), 749 750 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0), 751 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1), 752}; 753 754/* 755 * P4 PEBS specifics (Replay Event only) 756 * 757 * Format (bits): 758 * 0-6: metric from P4_PEBS_METRIC enum 759 * 7 : reserved 760 * 8 : reserved 761 * 9-11 : reserved 762 * 763 * Note we have UOP and PEBS bits reserved for now 764 * just in case if we will need them once 765 */ 766#define P4_PEBS_CONFIG_ENABLE (1 << 7) 767#define P4_PEBS_CONFIG_UOP_TAG (1 << 8) 768#define P4_PEBS_CONFIG_METRIC_MASK 0x3f 769#define P4_PEBS_CONFIG_MASK 0xff 770 771/* 772 * mem: Only counters MSR_IQ_COUNTER4 (16) and 773 * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling 774 */ 775#define P4_PEBS_ENABLE 0x02000000U 776#define P4_PEBS_ENABLE_UOP_TAG 0x01000000U 777 778#define p4_config_unpack_metric(v) (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK) 779#define p4_config_unpack_pebs(v) (((u64)(v)) & P4_PEBS_CONFIG_MASK) 780 781#define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask)) 782 783enum P4_PEBS_METRIC { 784 P4_PEBS_METRIC__none, 785 786 P4_PEBS_METRIC__1stl_cache_load_miss_retired, 787 P4_PEBS_METRIC__2ndl_cache_load_miss_retired, 788 P4_PEBS_METRIC__dtlb_load_miss_retired, 789 P4_PEBS_METRIC__dtlb_store_miss_retired, 790 P4_PEBS_METRIC__dtlb_all_miss_retired, 791 P4_PEBS_METRIC__tagged_mispred_branch, 792 P4_PEBS_METRIC__mob_load_replay_retired, 793 P4_PEBS_METRIC__split_load_retired, 794 P4_PEBS_METRIC__split_store_retired, 795 796 P4_PEBS_METRIC__max 797}; 798 799#endif /* PERF_EVENT_P4_H */ 800