1#ifndef _ASM_X86_IRQ_VECTORS_H 2#define _ASM_X86_IRQ_VECTORS_H 3 4/* 5 * Linux IRQ vector layout. 6 * 7 * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can 8 * be defined by Linux. They are used as a jump table by the CPU when a 9 * given vector is triggered - by a CPU-external, CPU-internal or 10 * software-triggered event. 11 * 12 * Linux sets the kernel code address each entry jumps to early during 13 * bootup, and never changes them. This is the general layout of the 14 * IDT entries: 15 * 16 * Vectors 0 ... 31 : system traps and exceptions - hardcoded events 17 * Vectors 32 ... 127 : device interrupts 18 * Vector 128 : legacy int80 syscall interface 19 * Vectors 129 ... 237 : device interrupts 20 * Vectors 238 ... 255 : special interrupts 21 * 22 * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table. 23 * 24 * This file enumerates the exact layout of them: 25 */ 26 27#define NMI_VECTOR 0x02 28#define MCE_VECTOR 0x12 29 30/* 31 * IDT vectors usable for external interrupt sources start at 0x20. 32 * (0x80 is the syscall vector, 0x30-0x3f are for ISA) 33 */ 34#define FIRST_EXTERNAL_VECTOR 0x20 35/* 36 * We start allocating at 0x21 to spread out vectors evenly between 37 * priority levels. (0x80 is the syscall vector) 38 */ 39#define VECTOR_OFFSET_START 1 40 41/* 42 * Reserve the lowest usable vector (and hence lowest priority) 0x20 for 43 * triggering cleanup after irq migration. 0x21-0x2f will still be used 44 * for device interrupts. 45 */ 46#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR 47 48#define IA32_SYSCALL_VECTOR 0x80 49#ifdef CONFIG_X86_32 50# define SYSCALL_VECTOR 0x80 51#endif 52 53/* 54 * Vectors 0x30-0x3f are used for ISA interrupts. 55 * round up to the next 16-vector boundary 56 */ 57#define IRQ0_VECTOR ((FIRST_EXTERNAL_VECTOR + 16) & ~15) 58 59#define IRQ1_VECTOR (IRQ0_VECTOR + 1) 60#define IRQ2_VECTOR (IRQ0_VECTOR + 2) 61#define IRQ3_VECTOR (IRQ0_VECTOR + 3) 62#define IRQ4_VECTOR (IRQ0_VECTOR + 4) 63#define IRQ5_VECTOR (IRQ0_VECTOR + 5) 64#define IRQ6_VECTOR (IRQ0_VECTOR + 6) 65#define IRQ7_VECTOR (IRQ0_VECTOR + 7) 66#define IRQ8_VECTOR (IRQ0_VECTOR + 8) 67#define IRQ9_VECTOR (IRQ0_VECTOR + 9) 68#define IRQ10_VECTOR (IRQ0_VECTOR + 10) 69#define IRQ11_VECTOR (IRQ0_VECTOR + 11) 70#define IRQ12_VECTOR (IRQ0_VECTOR + 12) 71#define IRQ13_VECTOR (IRQ0_VECTOR + 13) 72#define IRQ14_VECTOR (IRQ0_VECTOR + 14) 73#define IRQ15_VECTOR (IRQ0_VECTOR + 15) 74 75/* 76 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff 77 * 78 * some of the following vectors are 'rare', they are merged 79 * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. 80 * TLB, reschedule and local APIC vectors are performance-critical. 81 */ 82 83#define SPURIOUS_APIC_VECTOR 0xff 84/* 85 * Sanity check 86 */ 87#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) 88# error SPURIOUS_APIC_VECTOR definition error 89#endif 90 91#define ERROR_APIC_VECTOR 0xfe 92#define RESCHEDULE_VECTOR 0xfd 93#define CALL_FUNCTION_VECTOR 0xfc 94#define CALL_FUNCTION_SINGLE_VECTOR 0xfb 95#define THERMAL_APIC_VECTOR 0xfa 96#define THRESHOLD_APIC_VECTOR 0xf9 97#define REBOOT_VECTOR 0xf8 98 99/* f0-f7 used for spreading out TLB flushes: */ 100#define INVALIDATE_TLB_VECTOR_END 0xf7 101#define INVALIDATE_TLB_VECTOR_START 0xf0 102#define NUM_INVALIDATE_TLB_VECTORS 8 103 104#define LOCAL_TIMER_VECTOR 0xef 105 106/* 107 * Generic system vector for platform specific use 108 */ 109#define X86_PLATFORM_IPI_VECTOR 0xed 110 111/* 112 * Performance monitoring pending work vector: 113 */ 114#define LOCAL_PENDING_VECTOR 0xec 115 116#define UV_BAU_MESSAGE 0xea 117 118/* 119 * Self IPI vector for machine checks 120 */ 121#define MCE_SELF_VECTOR 0xeb 122 123/* Xen vector callback to receive events in a HVM domain */ 124#define XEN_HVM_EVTCHN_CALLBACK 0xe9 125 126#define NR_VECTORS 256 127 128#define FPU_IRQ 13 129 130#define FIRST_VM86_IRQ 3 131#define LAST_VM86_IRQ 15 132 133#ifndef __ASSEMBLY__ 134static inline int invalid_vm86_irq(int irq) 135{ 136 return irq < FIRST_VM86_IRQ || irq > LAST_VM86_IRQ; 137} 138#endif 139 140/* 141 * Size the maximum number of interrupts. 142 * 143 * If the irq_desc[] array has a sparse layout, we can size things 144 * generously - it scales up linearly with the maximum number of CPUs, 145 * and the maximum number of IO-APICs, whichever is higher. 146 * 147 * In other cases we size more conservatively, to not create too large 148 * static arrays. 149 */ 150 151#define NR_IRQS_LEGACY 16 152 153#define IO_APIC_VECTOR_LIMIT ( 32 * MAX_IO_APICS ) 154 155#ifdef CONFIG_X86_IO_APIC 156# ifdef CONFIG_SPARSE_IRQ 157# define CPU_VECTOR_LIMIT (64 * NR_CPUS) 158# define NR_IRQS \ 159 (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \ 160 (NR_VECTORS + CPU_VECTOR_LIMIT) : \ 161 (NR_VECTORS + IO_APIC_VECTOR_LIMIT)) 162# else 163# define CPU_VECTOR_LIMIT (32 * NR_CPUS) 164# define NR_IRQS \ 165 (CPU_VECTOR_LIMIT < IO_APIC_VECTOR_LIMIT ? \ 166 (NR_VECTORS + CPU_VECTOR_LIMIT) : \ 167 (NR_VECTORS + IO_APIC_VECTOR_LIMIT)) 168# endif 169#else /* !CONFIG_X86_IO_APIC: */ 170# define NR_IRQS NR_IRQS_LEGACY 171#endif 172 173#endif /* _ASM_X86_IRQ_VECTORS_H */ 174