1/* 2 * Copyright 2010 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 */ 14 15#ifndef _ASM_TILE_PCI_BRIDGE_H 16#define _ASM_TILE_PCI_BRIDGE_H 17 18#include <linux/ioport.h> 19#include <linux/pci.h> 20 21struct device_node; 22struct pci_controller; 23 24/* 25 * pci_io_base returns the memory address at which you can access 26 * the I/O space for PCI bus number `bus' (or NULL on error). 27 */ 28extern void __iomem *pci_bus_io_base(unsigned int bus); 29extern unsigned long pci_bus_io_base_phys(unsigned int bus); 30extern unsigned long pci_bus_mem_base_phys(unsigned int bus); 31 32/* Allocate a new PCI host bridge structure */ 33extern struct pci_controller *pcibios_alloc_controller(void); 34 35/* Helper function for setting up resources */ 36extern void pci_init_resource(struct resource *res, unsigned long start, 37 unsigned long end, int flags, char *name); 38 39/* Get the PCI host controller for a bus */ 40extern struct pci_controller *pci_bus_to_hose(int bus); 41 42/* 43 * Structure of a PCI controller (host bridge) 44 */ 45struct pci_controller { 46 int index; /* PCI domain number */ 47 struct pci_bus *root_bus; 48 49 int first_busno; 50 int last_busno; 51 52 int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */ 53 int hv_mem_fd; /* fd to Hypervisor for MMIO operations */ 54 55 struct pci_ops *ops; 56 57 int irq_base; /* Base IRQ from the Hypervisor */ 58 int plx_gen1; /* flag for PLX Gen 1 configuration */ 59 60 /* Address ranges that are routed to this controller/bridge. */ 61 struct resource mem_resources[3]; 62}; 63 64static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus) 65{ 66 return bus->sysdata; 67} 68 69extern void setup_indirect_pci_nomap(struct pci_controller *hose, 70 void __iomem *cfg_addr, void __iomem *cfg_data); 71extern void setup_indirect_pci(struct pci_controller *hose, 72 u32 cfg_addr, u32 cfg_data); 73extern void setup_grackle(struct pci_controller *hose); 74 75extern unsigned char common_swizzle(struct pci_dev *, unsigned char *); 76 77/* 78 * The following code swizzles for exactly one bridge. The routine 79 * common_swizzle below handles multiple bridges. But there are a 80 * some boards that don't follow the PCI spec's suggestion so we 81 * break this piece out separately. 82 */ 83static inline unsigned char bridge_swizzle(unsigned char pin, 84 unsigned char idsel) 85{ 86 return (((pin-1) + idsel) % 4) + 1; 87} 88 89/* 90 * The following macro is used to lookup irqs in a standard table 91 * format for those PPC systems that do not already have PCI 92 * interrupts properly routed. 93 */ 94#define PCI_IRQ_TABLE_LOOKUP ({ \ 95 long _ctl_ = -1; \ 96 if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \ 97 _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \ 98 _ctl_; \ 99}) 100 101/* 102 * Scan the buses below a given PCI host bridge and assign suitable 103 * resources to all devices found. 104 */ 105extern int pciauto_bus_scan(struct pci_controller *, int); 106 107#ifdef CONFIG_PCI 108extern unsigned long pci_address_to_pio(phys_addr_t address); 109#else 110static inline unsigned long pci_address_to_pio(phys_addr_t address) 111{ 112 return (unsigned long)-1; 113} 114#endif 115 116#endif /* _ASM_TILE_PCI_BRIDGE_H */ 117