1/* 2 * include/asm/processor.h 3 * 4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) 5 */ 6 7#ifndef __ASM_SPARC64_PROCESSOR_H 8#define __ASM_SPARC64_PROCESSOR_H 9 10/* 11 * Sparc64 implementation of macro that returns current 12 * instruction pointer ("program counter"). 13 */ 14#define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; }) 15 16#include <asm/asi.h> 17#include <asm/pstate.h> 18#include <asm/ptrace.h> 19#include <asm/page.h> 20 21/* The sparc has no problems with write protection */ 22#define wp_works_ok 1 23#define wp_works_ok__is_a_macro /* for versions in ksyms.c */ 24 25#define VA_BITS 44 26#ifndef __ASSEMBLY__ 27#define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3)) 28#else 29#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3)) 30#endif 31 32#define TASK_SIZE_OF(tsk) \ 33 (test_tsk_thread_flag(tsk,TIF_32BIT) ? \ 34 (1UL << 32UL) : ((unsigned long)-VPTE_SIZE)) 35#define TASK_SIZE TASK_SIZE_OF(current) 36#ifdef __KERNEL__ 37 38#define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE) 39#define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL)) 40 41#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ 42 STACK_TOP32 : STACK_TOP64) 43 44#define STACK_TOP_MAX STACK_TOP64 45 46#endif 47 48#ifndef __ASSEMBLY__ 49 50typedef struct { 51 unsigned char seg; 52} mm_segment_t; 53 54/* The Sparc processor specific thread struct. */ 55struct thread_struct { 56#ifdef CONFIG_DEBUG_SPINLOCK 57 /* How many spinlocks held by this thread. 58 * Used with spin lock debugging to catch tasks 59 * sleeping illegally with locks held. 60 */ 61 int smp_lock_count; 62 unsigned int smp_lock_pc; 63#else 64 int dummy; /* f'in gcc bug... */ 65#endif 66}; 67 68#endif /* !(__ASSEMBLY__) */ 69 70#ifndef CONFIG_DEBUG_SPINLOCK 71#define INIT_THREAD { \ 72 0, \ 73} 74#else /* CONFIG_DEBUG_SPINLOCK */ 75#define INIT_THREAD { \ 76/* smp_lock_count, smp_lock_pc, */ \ 77 0, 0, \ 78} 79#endif /* !(CONFIG_DEBUG_SPINLOCK) */ 80 81#ifndef __ASSEMBLY__ 82 83#include <linux/types.h> 84 85/* Return saved PC of a blocked thread. */ 86struct task_struct; 87extern unsigned long thread_saved_pc(struct task_struct *); 88 89/* On Uniprocessor, even in RMO processes see TSO semantics */ 90#ifdef CONFIG_SMP 91#define TSTATE_INITIAL_MM TSTATE_TSO 92#else 93#define TSTATE_INITIAL_MM TSTATE_RMO 94#endif 95 96/* Do necessary setup to start up a newly executed thread. */ 97#define start_thread(regs, pc, sp) \ 98do { \ 99 unsigned long __asi = ASI_PNF; \ 100 regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (__asi << 24UL); \ 101 regs->tpc = ((pc & (~3)) - 4); \ 102 regs->tnpc = regs->tpc + 4; \ 103 regs->y = 0; \ 104 set_thread_wstate(1 << 3); \ 105 if (current_thread_info()->utraps) { \ 106 if (*(current_thread_info()->utraps) < 2) \ 107 kfree(current_thread_info()->utraps); \ 108 else \ 109 (*(current_thread_info()->utraps))--; \ 110 current_thread_info()->utraps = NULL; \ 111 } \ 112 __asm__ __volatile__( \ 113 "stx %%g0, [%0 + %2 + 0x00]\n\t" \ 114 "stx %%g0, [%0 + %2 + 0x08]\n\t" \ 115 "stx %%g0, [%0 + %2 + 0x10]\n\t" \ 116 "stx %%g0, [%0 + %2 + 0x18]\n\t" \ 117 "stx %%g0, [%0 + %2 + 0x20]\n\t" \ 118 "stx %%g0, [%0 + %2 + 0x28]\n\t" \ 119 "stx %%g0, [%0 + %2 + 0x30]\n\t" \ 120 "stx %%g0, [%0 + %2 + 0x38]\n\t" \ 121 "stx %%g0, [%0 + %2 + 0x40]\n\t" \ 122 "stx %%g0, [%0 + %2 + 0x48]\n\t" \ 123 "stx %%g0, [%0 + %2 + 0x50]\n\t" \ 124 "stx %%g0, [%0 + %2 + 0x58]\n\t" \ 125 "stx %%g0, [%0 + %2 + 0x60]\n\t" \ 126 "stx %%g0, [%0 + %2 + 0x68]\n\t" \ 127 "stx %1, [%0 + %2 + 0x70]\n\t" \ 128 "stx %%g0, [%0 + %2 + 0x78]\n\t" \ 129 "wrpr %%g0, (1 << 3), %%wstate\n\t" \ 130 : \ 131 : "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \ 132 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \ 133} while (0) 134 135#define start_thread32(regs, pc, sp) \ 136do { \ 137 unsigned long __asi = ASI_PNF; \ 138 pc &= 0x00000000ffffffffUL; \ 139 sp &= 0x00000000ffffffffUL; \ 140 regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM) | (__asi << 24UL); \ 141 regs->tpc = ((pc & (~3)) - 4); \ 142 regs->tnpc = regs->tpc + 4; \ 143 regs->y = 0; \ 144 set_thread_wstate(2 << 3); \ 145 if (current_thread_info()->utraps) { \ 146 if (*(current_thread_info()->utraps) < 2) \ 147 kfree(current_thread_info()->utraps); \ 148 else \ 149 (*(current_thread_info()->utraps))--; \ 150 current_thread_info()->utraps = NULL; \ 151 } \ 152 __asm__ __volatile__( \ 153 "stx %%g0, [%0 + %2 + 0x00]\n\t" \ 154 "stx %%g0, [%0 + %2 + 0x08]\n\t" \ 155 "stx %%g0, [%0 + %2 + 0x10]\n\t" \ 156 "stx %%g0, [%0 + %2 + 0x18]\n\t" \ 157 "stx %%g0, [%0 + %2 + 0x20]\n\t" \ 158 "stx %%g0, [%0 + %2 + 0x28]\n\t" \ 159 "stx %%g0, [%0 + %2 + 0x30]\n\t" \ 160 "stx %%g0, [%0 + %2 + 0x38]\n\t" \ 161 "stx %%g0, [%0 + %2 + 0x40]\n\t" \ 162 "stx %%g0, [%0 + %2 + 0x48]\n\t" \ 163 "stx %%g0, [%0 + %2 + 0x50]\n\t" \ 164 "stx %%g0, [%0 + %2 + 0x58]\n\t" \ 165 "stx %%g0, [%0 + %2 + 0x60]\n\t" \ 166 "stx %%g0, [%0 + %2 + 0x68]\n\t" \ 167 "stx %1, [%0 + %2 + 0x70]\n\t" \ 168 "stx %%g0, [%0 + %2 + 0x78]\n\t" \ 169 "wrpr %%g0, (2 << 3), %%wstate\n\t" \ 170 : \ 171 : "r" (regs), "r" (sp - sizeof(struct reg_window32)), \ 172 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \ 173} while (0) 174 175/* Free all resources held by a thread. */ 176#define release_thread(tsk) do { } while (0) 177 178/* Prepare to copy thread state - unlazy all lazy status */ 179#define prepare_to_copy(tsk) do { } while (0) 180 181extern pid_t kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); 182 183extern unsigned long get_wchan(struct task_struct *task); 184 185#define task_pt_regs(tsk) (task_thread_info(tsk)->kregs) 186#define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc) 187#define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP]) 188 189#define cpu_relax() barrier() 190 191/* Prefetch support. This is tuned for UltraSPARC-III and later. 192 * UltraSPARC-I will treat these as nops, and UltraSPARC-II has 193 * a shallower prefetch queue than later chips. 194 */ 195#define ARCH_HAS_PREFETCH 196#define ARCH_HAS_PREFETCHW 197#define ARCH_HAS_SPINLOCK_PREFETCH 198 199static inline void prefetch(const void *x) 200{ 201 /* We do not use the read prefetch mnemonic because that 202 * prefetches into the prefetch-cache which only is accessible 203 * by floating point operations in UltraSPARC-III and later. 204 * By contrast, "#one_write" prefetches into the L2 cache 205 * in shared state. 206 */ 207 __asm__ __volatile__("prefetch [%0], #one_write" 208 : /* no outputs */ 209 : "r" (x)); 210} 211 212static inline void prefetchw(const void *x) 213{ 214 /* The most optimal prefetch to use for writes is 215 * "#n_writes". This brings the cacheline into the 216 * L2 cache in "owned" state. 217 */ 218 __asm__ __volatile__("prefetch [%0], #n_writes" 219 : /* no outputs */ 220 : "r" (x)); 221} 222 223#define spin_lock_prefetch(x) prefetchw(x) 224 225#define HAVE_ARCH_PICK_MMAP_LAYOUT 226 227#endif /* !(__ASSEMBLY__) */ 228 229#endif /* !(__ASM_SPARC64_PROCESSOR_H) */ 230