1#ifndef _SPARC64_CHAFSR_H 2#define _SPARC64_CHAFSR_H 3 4/* Cheetah Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */ 5 6/* Comments indicate which processor variants on which the bit definition 7 * is valid. Codes are: 8 * ch --> cheetah 9 * ch+ --> cheetah plus 10 * jp --> jalapeno 11 */ 12 13/* All bits of this register except M_SYNDROME and E_SYNDROME are 14 * read, write 1 to clear. M_SYNDROME and E_SYNDROME are read-only. 15 */ 16 17/* Software bit set by linux trap handlers to indicate that the trap was 18 * signalled at %tl >= 1. 19 */ 20#define CHAFSR_TL1 (1UL << 63UL) /* n/a */ 21 22/* Unmapped error from system bus for prefetch queue or 23 * store queue read operation 24 */ 25#define CHPAFSR_DTO (1UL << 59UL) /* ch+ */ 26 27/* Bus error from system bus for prefetch queue or store queue 28 * read operation 29 */ 30#define CHPAFSR_DBERR (1UL << 58UL) /* ch+ */ 31 32/* Hardware corrected E-cache Tag ECC error */ 33#define CHPAFSR_THCE (1UL << 57UL) /* ch+ */ 34/* System interface protocol error, hw timeout caused */ 35#define JPAFSR_JETO (1UL << 57UL) /* jp */ 36 37/* SW handled correctable E-cache Tag ECC error */ 38#define CHPAFSR_TSCE (1UL << 56UL) /* ch+ */ 39/* Parity error on system snoop results */ 40#define JPAFSR_SCE (1UL << 56UL) /* jp */ 41 42/* Uncorrectable E-cache Tag ECC error */ 43#define CHPAFSR_TUE (1UL << 55UL) /* ch+ */ 44/* System interface protocol error, illegal command detected */ 45#define JPAFSR_JEIC (1UL << 55UL) /* jp */ 46 47/* Uncorrectable system bus data ECC error due to prefetch 48 * or store fill request 49 */ 50#define CHPAFSR_DUE (1UL << 54UL) /* ch+ */ 51/* System interface protocol error, illegal ADTYPE detected */ 52#define JPAFSR_JEIT (1UL << 54UL) /* jp */ 53 54/* Multiple errors of the same type have occurred. This bit is set when 55 * an uncorrectable error or a SW correctable error occurs and the status 56 * bit to report that error is already set. When multiple errors of 57 * different types are indicated by setting multiple status bits. 58 * 59 * This bit is not set if multiple HW corrected errors with the same 60 * status bit occur, only uncorrectable and SW correctable ones have 61 * this behavior. 62 * 63 * This bit is not set when multiple ECC errors happen within a single 64 * 64-byte system bus transaction. Only the first ECC error in a 16-byte 65 * subunit will be logged. All errors in subsequent 16-byte subunits 66 * from the same 64-byte transaction are ignored. 67 */ 68#define CHAFSR_ME (1UL << 53UL) /* ch,ch+,jp */ 69 70/* Privileged state error has occurred. This is a capture of PSTATE.PRIV 71 * at the time the error is detected. 72 */ 73#define CHAFSR_PRIV (1UL << 52UL) /* ch,ch+,jp */ 74 75/* The following bits 51 (CHAFSR_PERR) to 33 (CHAFSR_CE) are sticky error 76 * bits and record the most recently detected errors. Bits accumulate 77 * errors that have been detected since the last write to clear the bit. 78 */ 79 80/* System interface protocol error. The processor asserts its' ERROR 81 * pin when this event occurs and it also logs a specific cause code 82 * into a JTAG scannable flop. 83 */ 84#define CHAFSR_PERR (1UL << 51UL) /* ch,ch+,jp */ 85 86/* Internal processor error. The processor asserts its' ERROR 87 * pin when this event occurs and it also logs a specific cause code 88 * into a JTAG scannable flop. 89 */ 90#define CHAFSR_IERR (1UL << 50UL) /* ch,ch+,jp */ 91 92/* System request parity error on incoming address */ 93#define CHAFSR_ISAP (1UL << 49UL) /* ch,ch+,jp */ 94 95/* HW Corrected system bus MTAG ECC error */ 96#define CHAFSR_EMC (1UL << 48UL) /* ch,ch+ */ 97/* Parity error on L2 cache tag SRAM */ 98#define JPAFSR_ETP (1UL << 48UL) /* jp */ 99 100/* Uncorrectable system bus MTAG ECC error */ 101#define CHAFSR_EMU (1UL << 47UL) /* ch,ch+ */ 102/* Out of range memory error has occurred */ 103#define JPAFSR_OM (1UL << 47UL) /* jp */ 104 105/* HW Corrected system bus data ECC error for read of interrupt vector */ 106#define CHAFSR_IVC (1UL << 46UL) /* ch,ch+ */ 107/* Error due to unsupported store */ 108#define JPAFSR_UMS (1UL << 46UL) /* jp */ 109 110/* Uncorrectable system bus data ECC error for read of interrupt vector */ 111#define CHAFSR_IVU (1UL << 45UL) /* ch,ch+,jp */ 112 113/* Unmapped error from system bus */ 114#define CHAFSR_TO (1UL << 44UL) /* ch,ch+,jp */ 115 116/* Bus error response from system bus */ 117#define CHAFSR_BERR (1UL << 43UL) /* ch,ch+,jp */ 118 119/* SW Correctable E-cache ECC error for instruction fetch or data access 120 * other than block load. 121 */ 122#define CHAFSR_UCC (1UL << 42UL) /* ch,ch+,jp */ 123 124/* Uncorrectable E-cache ECC error for instruction fetch or data access 125 * other than block load. 126 */ 127#define CHAFSR_UCU (1UL << 41UL) /* ch,ch+,jp */ 128 129/* Copyout HW Corrected ECC error */ 130#define CHAFSR_CPC (1UL << 40UL) /* ch,ch+,jp */ 131 132/* Copyout Uncorrectable ECC error */ 133#define CHAFSR_CPU (1UL << 39UL) /* ch,ch+,jp */ 134 135/* HW Corrected ECC error from E-cache for writeback */ 136#define CHAFSR_WDC (1UL << 38UL) /* ch,ch+,jp */ 137 138/* Uncorrectable ECC error from E-cache for writeback */ 139#define CHAFSR_WDU (1UL << 37UL) /* ch,ch+,jp */ 140 141/* HW Corrected ECC error from E-cache for store merge or block load */ 142#define CHAFSR_EDC (1UL << 36UL) /* ch,ch+,jp */ 143 144/* Uncorrectable ECC error from E-cache for store merge or block load */ 145#define CHAFSR_EDU (1UL << 35UL) /* ch,ch+,jp */ 146 147/* Uncorrectable system bus data ECC error for read of memory or I/O */ 148#define CHAFSR_UE (1UL << 34UL) /* ch,ch+,jp */ 149 150/* HW Corrected system bus data ECC error for read of memory or I/O */ 151#define CHAFSR_CE (1UL << 33UL) /* ch,ch+,jp */ 152 153/* Uncorrectable ECC error from remote cache/memory */ 154#define JPAFSR_RUE (1UL << 32UL) /* jp */ 155 156/* Correctable ECC error from remote cache/memory */ 157#define JPAFSR_RCE (1UL << 31UL) /* jp */ 158 159/* JBUS parity error on returned read data */ 160#define JPAFSR_BP (1UL << 30UL) /* jp */ 161 162/* JBUS parity error on data for writeback or block store */ 163#define JPAFSR_WBP (1UL << 29UL) /* jp */ 164 165/* Foreign read to DRAM incurring correctable ECC error */ 166#define JPAFSR_FRC (1UL << 28UL) /* jp */ 167 168/* Foreign read to DRAM incurring uncorrectable ECC error */ 169#define JPAFSR_FRU (1UL << 27UL) /* jp */ 170 171#define CHAFSR_ERRORS (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \ 172 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \ 173 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \ 174 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \ 175 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE) 176#define CHPAFSR_ERRORS (CHPAFSR_DTO | CHPAFSR_DBERR | CHPAFSR_THCE | \ 177 CHPAFSR_TSCE | CHPAFSR_TUE | CHPAFSR_DUE | \ 178 CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \ 179 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \ 180 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \ 181 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \ 182 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE) 183#define JPAFSR_ERRORS (JPAFSR_JETO | JPAFSR_SCE | JPAFSR_JEIC | \ 184 JPAFSR_JEIT | CHAFSR_PERR | CHAFSR_IERR | \ 185 CHAFSR_ISAP | JPAFSR_ETP | JPAFSR_OM | \ 186 JPAFSR_UMS | CHAFSR_IVU | CHAFSR_TO | \ 187 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | \ 188 CHAFSR_CPC | CHAFSR_CPU | CHAFSR_WDC | \ 189 CHAFSR_WDU | CHAFSR_EDC | CHAFSR_EDU | \ 190 CHAFSR_UE | CHAFSR_CE | JPAFSR_RUE | \ 191 JPAFSR_RCE | JPAFSR_BP | JPAFSR_WBP | \ 192 JPAFSR_FRC | JPAFSR_FRU) 193 194/* Active JBUS request signal when error occurred */ 195#define JPAFSR_JBREQ (0x7UL << 24UL) /* jp */ 196#define JPAFSR_JBREQ_SHIFT 24UL 197 198/* L2 cache way information */ 199#define JPAFSR_ETW (0x3UL << 22UL) /* jp */ 200#define JPAFSR_ETW_SHIFT 22UL 201 202/* System bus MTAG ECC syndrome. This field captures the status of the 203 * first occurrence of the highest-priority error according to the M_SYND 204 * overwrite policy. After the AFSR sticky bit, corresponding to the error 205 * for which the M_SYND is reported, is cleared, the contents of the M_SYND 206 * field will be unchanged by will be unfrozen for further error capture. 207 */ 208#define CHAFSR_M_SYNDROME (0xfUL << 16UL) /* ch,ch+,jp */ 209#define CHAFSR_M_SYNDROME_SHIFT 16UL 210 211/* Agenid Id of the foreign device causing the UE/CE errors */ 212#define JPAFSR_AID (0x1fUL << 9UL) /* jp */ 213#define JPAFSR_AID_SHIFT 9UL 214 215/* System bus or E-cache data ECC syndrome. This field captures the status 216 * of the first occurrence of the highest-priority error according to the 217 * E_SYND overwrite policy. After the AFSR sticky bit, corresponding to the 218 * error for which the E_SYND is reported, is cleare, the contents of the E_SYND 219 * field will be unchanged but will be unfrozen for further error capture. 220 */ 221#define CHAFSR_E_SYNDROME (0x1ffUL << 0UL) /* ch,ch+,jp */ 222#define CHAFSR_E_SYNDROME_SHIFT 0UL 223 224/* The AFSR must be explicitly cleared by software, it is not cleared automatically 225 * by a read. Writes to bits <51:33> with bits set will clear the corresponding 226 * bits in the AFSR. Bits associated with disrupting traps must be cleared before 227 * interrupts are re-enabled to prevent multiple traps for the same error. I.e. 228 * PSTATE.IE and AFSR bits control delivery of disrupting traps. 229 * 230 * Since there is only one AFAR, when multiple events have been logged by the 231 * bits in the AFSR, at most one of these events will have its status captured 232 * in the AFAR. The highest priority of those event bits will get AFAR logging. 233 * The AFAR will be unlocked and available to capture the address of another event 234 * as soon as the one bit in AFSR that corresponds to the event logged in AFAR is 235 * cleared. For example, if AFSR.CE is detected, then AFSR.UE (which overwrites 236 * the AFAR), and AFSR.UE is cleared by not AFSR.CE, then the AFAR will be unlocked 237 * and ready for another event, even though AFSR.CE is still set. The same rules 238 * also apply to the M_SYNDROME and E_SYNDROME fields of the AFSR. 239 */ 240 241#endif /* _SPARC64_CHAFSR_H */ 242