1/* 2 * arch/sh/kernel/cpu/sh4/clock-sh4-202.c 3 * 4 * Additional SH4-202 support for the clock framework 5 * 6 * Copyright (C) 2005 Paul Mundt 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12#include <linux/init.h> 13#include <linux/kernel.h> 14#include <linux/err.h> 15#include <linux/io.h> 16#include <asm/clkdev.h> 17#include <asm/clock.h> 18#include <asm/freq.h> 19 20#define CPG2_FRQCR3 0xfe0a0018 21 22static int frqcr3_divisors[] = { 1, 2, 3, 4, 6, 8, 16 }; 23static int frqcr3_values[] = { 0, 1, 2, 3, 4, 5, 6 }; 24 25static unsigned long emi_clk_recalc(struct clk *clk) 26{ 27 int idx = __raw_readl(CPG2_FRQCR3) & 0x0007; 28 return clk->parent->rate / frqcr3_divisors[idx]; 29} 30 31static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) 32{ 33 int divisor = clk->parent->rate / rate; 34 int i; 35 36 for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++) 37 if (frqcr3_divisors[i] == divisor) 38 return frqcr3_values[i]; 39 40 /* Safe fallback */ 41 return 5; 42} 43 44static struct clk_ops sh4202_emi_clk_ops = { 45 .recalc = emi_clk_recalc, 46}; 47 48static struct clk sh4202_emi_clk = { 49 .flags = CLK_ENABLE_ON_INIT, 50 .ops = &sh4202_emi_clk_ops, 51}; 52 53static unsigned long femi_clk_recalc(struct clk *clk) 54{ 55 int idx = (__raw_readl(CPG2_FRQCR3) >> 3) & 0x0007; 56 return clk->parent->rate / frqcr3_divisors[idx]; 57} 58 59static struct clk_ops sh4202_femi_clk_ops = { 60 .recalc = femi_clk_recalc, 61}; 62 63static struct clk sh4202_femi_clk = { 64 .flags = CLK_ENABLE_ON_INIT, 65 .ops = &sh4202_femi_clk_ops, 66}; 67 68static void shoc_clk_init(struct clk *clk) 69{ 70 int i; 71 72 /* 73 * For some reason, the shoc_clk seems to be set to some really 74 * insane value at boot (values outside of the allowable frequency 75 * range for instance). We deal with this by scaling it back down 76 * to something sensible just in case. 77 * 78 * Start scaling from the high end down until we find something 79 * that passes rate verification.. 80 */ 81 for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++) { 82 int divisor = frqcr3_divisors[i]; 83 84 if (clk->ops->set_rate(clk, clk->parent->rate / 85 divisor, 0) == 0) 86 break; 87 } 88 89 WARN_ON(i == ARRAY_SIZE(frqcr3_divisors)); /* Undefined clock */ 90} 91 92static unsigned long shoc_clk_recalc(struct clk *clk) 93{ 94 int idx = (__raw_readl(CPG2_FRQCR3) >> 6) & 0x0007; 95 return clk->parent->rate / frqcr3_divisors[idx]; 96} 97 98static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate) 99{ 100 struct clk *bclk = clk_get(NULL, "bus_clk"); 101 unsigned long bclk_rate = clk_get_rate(bclk); 102 103 clk_put(bclk); 104 105 if (rate > bclk_rate) 106 return 1; 107 if (rate > 66000000) 108 return 1; 109 110 return 0; 111} 112 113static int shoc_clk_set_rate(struct clk *clk, unsigned long rate, int algo_id) 114{ 115 unsigned long frqcr3; 116 unsigned int tmp; 117 118 /* Make sure we have something sensible to switch to */ 119 if (shoc_clk_verify_rate(clk, rate) != 0) 120 return -EINVAL; 121 122 tmp = frqcr3_lookup(clk, rate); 123 124 frqcr3 = __raw_readl(CPG2_FRQCR3); 125 frqcr3 &= ~(0x0007 << 6); 126 frqcr3 |= tmp << 6; 127 __raw_writel(frqcr3, CPG2_FRQCR3); 128 129 clk->rate = clk->parent->rate / frqcr3_divisors[tmp]; 130 131 return 0; 132} 133 134static struct clk_ops sh4202_shoc_clk_ops = { 135 .init = shoc_clk_init, 136 .recalc = shoc_clk_recalc, 137 .set_rate = shoc_clk_set_rate, 138}; 139 140static struct clk sh4202_shoc_clk = { 141 .flags = CLK_ENABLE_ON_INIT, 142 .ops = &sh4202_shoc_clk_ops, 143}; 144 145static struct clk *sh4202_onchip_clocks[] = { 146 &sh4202_emi_clk, 147 &sh4202_femi_clk, 148 &sh4202_shoc_clk, 149}; 150 151#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 152 153static struct clk_lookup lookups[] = { 154 /* main clocks */ 155 CLKDEV_CON_ID("emi_clk", &sh4202_emi_clk), 156 CLKDEV_CON_ID("femi_clk", &sh4202_femi_clk), 157 CLKDEV_CON_ID("shoc_clk", &sh4202_shoc_clk), 158}; 159 160int __init arch_clk_init(void) 161{ 162 struct clk *clk; 163 int i, ret = 0; 164 165 cpg_clk_init(); 166 167 clk = clk_get(NULL, "master_clk"); 168 for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) { 169 struct clk *clkp = sh4202_onchip_clocks[i]; 170 171 clkp->parent = clk; 172 ret |= clk_register(clkp); 173 } 174 175 clk_put(clk); 176 177 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 178 179 return ret; 180} 181