1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H 2#define __ASM_SH_CPU_SH4_DMA_SH7780_H 3 4#if defined(CONFIG_CPU_SUBTYPE_SH7343) || defined(CONFIG_CPU_SUBTYPE_SH7730) 5#define DMTE0_IRQ 48 6#define DMTE4_IRQ 76 7#define DMAE0_IRQ 78 /* DMA Error IRQ*/ 8#define SH_DMAC_BASE0 0xFE008020 9#define SH_DMARS_BASE0 0xFE009000 10#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 11#define DMTE0_IRQ 48 12#define DMTE4_IRQ 76 13#define DMAE0_IRQ 78 /* DMA Error IRQ*/ 14#define SH_DMAC_BASE0 0xFE008020 15#define SH_DMARS_BASE0 0xFE009000 16#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 17 defined(CONFIG_CPU_SUBTYPE_SH7764) 18#define DMTE0_IRQ 34 19#define DMTE4_IRQ 44 20#define DMAE0_IRQ 38 21#define SH_DMAC_BASE0 0xFF608020 22#define SH_DMARS_BASE0 0xFF609000 23#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 24#define DMTE0_IRQ 48 /* DMAC0A*/ 25#define DMTE4_IRQ 76 /* DMAC0B */ 26#define DMTE6_IRQ 40 27#define DMTE8_IRQ 42 /* DMAC1A */ 28#define DMTE9_IRQ 43 29#define DMTE10_IRQ 72 /* DMAC1B */ 30#define DMTE11_IRQ 73 31#define DMAE0_IRQ 78 /* DMA Error IRQ*/ 32#define DMAE1_IRQ 74 /* DMA Error IRQ*/ 33#define SH_DMAC_BASE0 0xFE008020 34#define SH_DMAC_BASE1 0xFDC08020 35#define SH_DMARS_BASE0 0xFDC09000 36#elif defined(CONFIG_CPU_SUBTYPE_SH7724) 37#define DMTE0_IRQ 48 /* DMAC0A*/ 38#define DMTE4_IRQ 76 /* DMAC0B */ 39#define DMTE6_IRQ 40 40#define DMTE8_IRQ 42 /* DMAC1A */ 41#define DMTE9_IRQ 43 42#define DMTE10_IRQ 72 /* DMAC1B */ 43#define DMTE11_IRQ 73 44#define DMAE0_IRQ 78 /* DMA Error IRQ*/ 45#define DMAE1_IRQ 74 /* DMA Error IRQ*/ 46#define SH_DMAC_BASE0 0xFE008020 47#define SH_DMAC_BASE1 0xFDC08020 48#define SH_DMARS_BASE0 0xFE009000 49#define SH_DMARS_BASE1 0xFDC09000 50#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 51#define DMTE0_IRQ 34 52#define DMTE4_IRQ 44 53#define DMTE6_IRQ 46 54#define DMTE8_IRQ 92 55#define DMTE9_IRQ 93 56#define DMTE10_IRQ 94 57#define DMTE11_IRQ 95 58#define DMAE0_IRQ 38 /* DMA Error IRQ */ 59#define SH_DMAC_BASE0 0xFC808020 60#define SH_DMAC_BASE1 0xFC818020 61#define SH_DMARS_BASE0 0xFC809000 62#else /* SH7785 */ 63#define DMTE0_IRQ 33 64#define DMTE4_IRQ 37 65#define DMTE6_IRQ 52 66#define DMTE8_IRQ 54 67#define DMTE9_IRQ 55 68#define DMTE10_IRQ 56 69#define DMTE11_IRQ 57 70#define DMAE0_IRQ 39 /* DMA Error IRQ0 */ 71#define DMAE1_IRQ 58 /* DMA Error IRQ1 */ 72#define SH_DMAC_BASE0 0xFC808020 73#define SH_DMAC_BASE1 0xFCC08020 74#define SH_DMARS_BASE0 0xFC809000 75#endif 76 77#define REQ_HE 0x000000C0 78#define REQ_H 0x00000080 79#define REQ_LE 0x00000040 80#define TM_BURST 0x00000020 81 82#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */ 83