1/* 2 * include/asm-sh/cpu-sh2/watchdog.h 3 * 4 * Copyright (C) 2002, 2003 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10#ifndef __ASM_CPU_SH2_WATCHDOG_H 11#define __ASM_CPU_SH2_WATCHDOG_H 12 13/* 14 * More SH-2 brilliance .. its not good enough that we can't read 15 * and write the same sizes to WTCNT, now we have to read and write 16 * with different sizes at different addresses for WTCNT _and_ RSTCSR. 17 * 18 * At least on the bright side no one has managed to screw over WTCSR 19 * in this fashion .. yet. 20 */ 21/* Register definitions */ 22#define WTCNT 0xfffffe80 23#define WTCSR 0xfffffe80 24#define RSTCSR 0xfffffe82 25 26#define WTCNT_R (WTCNT + 1) 27#define RSTCSR_R (RSTCSR + 1) 28 29/* Bit definitions */ 30#define WTCSR_IOVF 0x80 31#define WTCSR_WT 0x40 32#define WTCSR_TME 0x20 33#define WTCSR_RSTS 0x00 34 35#define RSTCSR_RSTS 0x20 36 37/** 38 * sh_wdt_read_rstcsr - Read from Reset Control/Status Register 39 * 40 * Reads back the RSTCSR value. 41 */ 42static inline __u8 sh_wdt_read_rstcsr(void) 43{ 44 /* 45 * Same read/write brain-damage as for WTCNT here.. 46 */ 47 return __raw_readb(RSTCSR_R); 48} 49 50/** 51 * sh_wdt_write_csr - Write to Reset Control/Status Register 52 * 53 * @val: Value to write 54 * 55 * Writes the given value @val to the lower byte of the control/status 56 * register. The upper byte is set manually on each write. 57 */ 58static inline void sh_wdt_write_rstcsr(__u8 val) 59{ 60 /* 61 * Note: Due to the brain-damaged nature of this register, 62 * we can't presently touch the WOVF bit, since the upper byte 63 * has to be swapped for this. So just leave it alone.. 64 */ 65 __raw_writeb((WTCNT_HIGH << 8) | (__u16)val, RSTCSR); 66} 67 68#endif /* __ASM_CPU_SH2_WATCHDOG_H */ 69