1/* 2 * linux/arch/sh/boards/se/770x/setup.c 3 * 4 * Copyright (C) 2000 Kazumoto Kojima 5 * 6 * Hitachi SolutionEngine Support. 7 * 8 */ 9#include <linux/init.h> 10#include <linux/platform_device.h> 11#include <mach-se/mach/se.h> 12#include <mach-se/mach/mrshpc.h> 13#include <asm/machvec.h> 14#include <asm/io.h> 15#include <asm/smc37c93x.h> 16#include <asm/heartbeat.h> 17 18/* 19 * Configure the Super I/O chip 20 */ 21static void __init smsc_config(int index, int data) 22{ 23 outb_p(index, INDEX_PORT); 24 outb_p(data, DATA_PORT); 25} 26 27static void __init smsc_setup(char **cmdline_p) 28{ 29 outb_p(CONFIG_ENTER, CONFIG_PORT); 30 outb_p(CONFIG_ENTER, CONFIG_PORT); 31 32 /* FDC */ 33 smsc_config(CURRENT_LDN_INDEX, LDN_FDC); 34 smsc_config(ACTIVATE_INDEX, 0x01); 35 smsc_config(IRQ_SELECT_INDEX, 6); /* IRQ6 */ 36 37 /* AUXIO (GPIO): to use IDE1 */ 38 smsc_config(CURRENT_LDN_INDEX, LDN_AUXIO); 39 smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */ 40 smsc_config(GPIO47_INDEX, 0x00); /* nIOWOP */ 41 42 /* COM1 */ 43 smsc_config(CURRENT_LDN_INDEX, LDN_COM1); 44 smsc_config(ACTIVATE_INDEX, 0x01); 45 smsc_config(IO_BASE_HI_INDEX, 0x03); 46 smsc_config(IO_BASE_LO_INDEX, 0xf8); 47 smsc_config(IRQ_SELECT_INDEX, 4); /* IRQ4 */ 48 49 /* COM2 */ 50 smsc_config(CURRENT_LDN_INDEX, LDN_COM2); 51 smsc_config(ACTIVATE_INDEX, 0x01); 52 smsc_config(IO_BASE_HI_INDEX, 0x02); 53 smsc_config(IO_BASE_LO_INDEX, 0xf8); 54 smsc_config(IRQ_SELECT_INDEX, 3); /* IRQ3 */ 55 56 /* RTC */ 57 smsc_config(CURRENT_LDN_INDEX, LDN_RTC); 58 smsc_config(ACTIVATE_INDEX, 0x01); 59 smsc_config(IRQ_SELECT_INDEX, 8); /* IRQ8 */ 60 61 outb_p(CONFIG_EXIT, CONFIG_PORT); 62} 63 64 65static struct resource cf_ide_resources[] = { 66 [0] = { 67 .start = PA_MRSHPC_IO + 0x1f0, 68 .end = PA_MRSHPC_IO + 0x1f0 + 8, 69 .flags = IORESOURCE_MEM, 70 }, 71 [1] = { 72 .start = PA_MRSHPC_IO + 0x1f0 + 0x206, 73 .end = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8, 74 .flags = IORESOURCE_MEM, 75 }, 76 [2] = { 77 .start = IRQ_CFCARD, 78 .flags = IORESOURCE_IRQ, 79 }, 80}; 81 82static struct platform_device cf_ide_device = { 83 .name = "pata_platform", 84 .id = -1, 85 .num_resources = ARRAY_SIZE(cf_ide_resources), 86 .resource = cf_ide_resources, 87}; 88 89static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; 90 91static struct heartbeat_data heartbeat_data = { 92 .bit_pos = heartbeat_bit_pos, 93 .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), 94}; 95 96static struct resource heartbeat_resource = { 97 .start = PA_LED, 98 .end = PA_LED, 99 .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, 100}; 101 102static struct platform_device heartbeat_device = { 103 .name = "heartbeat", 104 .id = -1, 105 .dev = { 106 .platform_data = &heartbeat_data, 107 }, 108 .num_resources = 1, 109 .resource = &heartbeat_resource, 110}; 111 112#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 113/* SH771X Ethernet driver */ 114static struct resource sh_eth0_resources[] = { 115 [0] = { 116 .start = SH_ETH0_BASE, 117 .end = SH_ETH0_BASE + 0x1B8, 118 .flags = IORESOURCE_MEM, 119 }, 120 [1] = { 121 .start = SH_ETH0_IRQ, 122 .end = SH_ETH0_IRQ, 123 .flags = IORESOURCE_IRQ, 124 }, 125}; 126 127static struct platform_device sh_eth0_device = { 128 .name = "sh-eth", 129 .id = 0, 130 .dev = { 131 .platform_data = PHY_ID, 132 }, 133 .num_resources = ARRAY_SIZE(sh_eth0_resources), 134 .resource = sh_eth0_resources, 135}; 136 137static struct resource sh_eth1_resources[] = { 138 [0] = { 139 .start = SH_ETH1_BASE, 140 .end = SH_ETH1_BASE + 0x1B8, 141 .flags = IORESOURCE_MEM, 142 }, 143 [1] = { 144 .start = SH_ETH1_IRQ, 145 .end = SH_ETH1_IRQ, 146 .flags = IORESOURCE_IRQ, 147 }, 148}; 149 150static struct platform_device sh_eth1_device = { 151 .name = "sh-eth", 152 .id = 1, 153 .dev = { 154 .platform_data = PHY_ID, 155 }, 156 .num_resources = ARRAY_SIZE(sh_eth1_resources), 157 .resource = sh_eth1_resources, 158}; 159#endif 160 161static struct platform_device *se_devices[] __initdata = { 162 &heartbeat_device, 163 &cf_ide_device, 164#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 165 &sh_eth0_device, 166 &sh_eth1_device, 167#endif 168}; 169 170static int __init se_devices_setup(void) 171{ 172 mrshpc_setup_windows(); 173 return platform_add_devices(se_devices, ARRAY_SIZE(se_devices)); 174} 175device_initcall(se_devices_setup); 176 177/* 178 * The Machine Vector 179 */ 180static struct sh_machine_vector mv_se __initmv = { 181 .mv_name = "SolutionEngine", 182 .mv_setup = smsc_setup, 183#if defined(CONFIG_CPU_SH4) 184 .mv_nr_irqs = 48, 185#elif defined(CONFIG_CPU_SUBTYPE_SH7708) 186 .mv_nr_irqs = 32, 187#elif defined(CONFIG_CPU_SUBTYPE_SH7709) 188 .mv_nr_irqs = 61, 189#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 190 .mv_nr_irqs = 86, 191#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 192 .mv_nr_irqs = 104, 193#endif 194 195 .mv_inb = se_inb, 196 .mv_inw = se_inw, 197 .mv_inl = se_inl, 198 .mv_outb = se_outb, 199 .mv_outw = se_outw, 200 .mv_outl = se_outl, 201 202 .mv_inb_p = se_inb_p, 203 .mv_inw_p = se_inw, 204 .mv_inl_p = se_inl, 205 .mv_outb_p = se_outb_p, 206 .mv_outw_p = se_outw, 207 .mv_outl_p = se_outl, 208 209 .mv_insb = se_insb, 210 .mv_insw = se_insw, 211 .mv_insl = se_insl, 212 .mv_outsb = se_outsb, 213 .mv_outsw = se_outsw, 214 .mv_outsl = se_outsl, 215 216 .mv_init_irq = init_se_IRQ, 217}; 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