1/* 2 * GPIOs on MPC8349/8572/8610 and compatible 3 * 4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <linux/kernel.h> 12#include <linux/init.h> 13#include <linux/spinlock.h> 14#include <linux/io.h> 15#include <linux/of.h> 16#include <linux/of_gpio.h> 17#include <linux/gpio.h> 18#include <linux/slab.h> 19#include <linux/irq.h> 20 21#define MPC8XXX_GPIO_PINS 32 22 23#define GPIO_DIR 0x00 24#define GPIO_ODR 0x04 25#define GPIO_DAT 0x08 26#define GPIO_IER 0x0c 27#define GPIO_IMR 0x10 28#define GPIO_ICR 0x14 29 30struct mpc8xxx_gpio_chip { 31 struct of_mm_gpio_chip mm_gc; 32 spinlock_t lock; 33 34 /* 35 * shadowed data register to be able to clear/set output pins in 36 * open drain mode safely 37 */ 38 u32 data; 39 struct irq_host *irq; 40}; 41 42static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) 43{ 44 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio); 45} 46 47static inline struct mpc8xxx_gpio_chip * 48to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm) 49{ 50 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc); 51} 52 53static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm) 54{ 55 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); 56 57 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT); 58} 59 60static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) 61{ 62 u32 val; 63 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); 64 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); 65 66 val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR); 67 68 return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio); 69} 70 71static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio) 72{ 73 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); 74 75 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); 76} 77 78static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 79{ 80 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); 81 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); 82 unsigned long flags; 83 84 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 85 86 if (val) 87 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio); 88 else 89 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio); 90 91 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); 92 93 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 94} 95 96static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 97{ 98 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); 99 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); 100 unsigned long flags; 101 102 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 103 104 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); 105 106 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 107 108 return 0; 109} 110 111static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 112{ 113 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); 114 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); 115 unsigned long flags; 116 117 mpc8xxx_gpio_set(gc, gpio, val); 118 119 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 120 121 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); 122 123 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 124 125 return 0; 126} 127 128static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 129{ 130 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); 131 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); 132 133 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) 134 return irq_create_mapping(mpc8xxx_gc->irq, offset); 135 else 136 return -ENXIO; 137} 138 139static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) 140{ 141 struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_desc_data(desc); 142 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 143 unsigned int mask; 144 145 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR); 146 if (mask) 147 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 148 32 - ffs(mask))); 149} 150 151static void mpc8xxx_irq_unmask(unsigned int virq) 152{ 153 struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); 154 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 155 unsigned long flags; 156 157 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 158 159 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq))); 160 161 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 162} 163 164static void mpc8xxx_irq_mask(unsigned int virq) 165{ 166 struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); 167 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 168 unsigned long flags; 169 170 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 171 172 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq))); 173 174 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 175} 176 177static void mpc8xxx_irq_ack(unsigned int virq) 178{ 179 struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); 180 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 181 182 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(virq_to_hw(virq))); 183} 184 185static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type) 186{ 187 struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); 188 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 189 unsigned long flags; 190 191 switch (flow_type) { 192 case IRQ_TYPE_EDGE_FALLING: 193 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 194 setbits32(mm->regs + GPIO_ICR, 195 mpc8xxx_gpio2mask(virq_to_hw(virq))); 196 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 197 break; 198 199 case IRQ_TYPE_EDGE_BOTH: 200 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 201 clrbits32(mm->regs + GPIO_ICR, 202 mpc8xxx_gpio2mask(virq_to_hw(virq))); 203 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 204 break; 205 206 default: 207 return -EINVAL; 208 } 209 210 return 0; 211} 212 213static struct irq_chip mpc8xxx_irq_chip = { 214 .name = "mpc8xxx-gpio", 215 .unmask = mpc8xxx_irq_unmask, 216 .mask = mpc8xxx_irq_mask, 217 .ack = mpc8xxx_irq_ack, 218 .set_type = mpc8xxx_irq_set_type, 219}; 220 221static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq, 222 irq_hw_number_t hw) 223{ 224 set_irq_chip_data(virq, h->host_data); 225 set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); 226 set_irq_type(virq, IRQ_TYPE_NONE); 227 228 return 0; 229} 230 231static int mpc8xxx_gpio_irq_xlate(struct irq_host *h, struct device_node *ct, 232 const u32 *intspec, unsigned int intsize, 233 irq_hw_number_t *out_hwirq, 234 unsigned int *out_flags) 235 236{ 237 /* interrupt sense values coming from the device tree equal either 238 * EDGE_FALLING or EDGE_BOTH 239 */ 240 *out_hwirq = intspec[0]; 241 *out_flags = intspec[1]; 242 243 return 0; 244} 245 246static struct irq_host_ops mpc8xxx_gpio_irq_ops = { 247 .map = mpc8xxx_gpio_irq_map, 248 .xlate = mpc8xxx_gpio_irq_xlate, 249}; 250 251static void __init mpc8xxx_add_controller(struct device_node *np) 252{ 253 struct mpc8xxx_gpio_chip *mpc8xxx_gc; 254 struct of_mm_gpio_chip *mm_gc; 255 struct gpio_chip *gc; 256 unsigned hwirq; 257 int ret; 258 259 mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL); 260 if (!mpc8xxx_gc) { 261 ret = -ENOMEM; 262 goto err; 263 } 264 265 spin_lock_init(&mpc8xxx_gc->lock); 266 267 mm_gc = &mpc8xxx_gc->mm_gc; 268 gc = &mm_gc->gc; 269 270 mm_gc->save_regs = mpc8xxx_gpio_save_regs; 271 gc->ngpio = MPC8XXX_GPIO_PINS; 272 gc->direction_input = mpc8xxx_gpio_dir_in; 273 gc->direction_output = mpc8xxx_gpio_dir_out; 274 if (of_device_is_compatible(np, "fsl,mpc8572-gpio")) 275 gc->get = mpc8572_gpio_get; 276 else 277 gc->get = mpc8xxx_gpio_get; 278 gc->set = mpc8xxx_gpio_set; 279 gc->to_irq = mpc8xxx_gpio_to_irq; 280 281 ret = of_mm_gpiochip_add(np, mm_gc); 282 if (ret) 283 goto err; 284 285 hwirq = irq_of_parse_and_map(np, 0); 286 if (hwirq == NO_IRQ) 287 goto skip_irq; 288 289 mpc8xxx_gc->irq = 290 irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, MPC8XXX_GPIO_PINS, 291 &mpc8xxx_gpio_irq_ops, MPC8XXX_GPIO_PINS); 292 if (!mpc8xxx_gc->irq) 293 goto skip_irq; 294 295 mpc8xxx_gc->irq->host_data = mpc8xxx_gc; 296 297 /* ack and mask all irqs */ 298 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); 299 out_be32(mm_gc->regs + GPIO_IMR, 0); 300 301 set_irq_data(hwirq, mpc8xxx_gc); 302 set_irq_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); 303 304skip_irq: 305 return; 306 307err: 308 pr_err("%s: registration failed with status %d\n", 309 np->full_name, ret); 310 kfree(mpc8xxx_gc); 311 312 return; 313} 314 315static int __init mpc8xxx_add_gpiochips(void) 316{ 317 struct device_node *np; 318 319 for_each_compatible_node(np, NULL, "fsl,mpc8349-gpio") 320 mpc8xxx_add_controller(np); 321 322 for_each_compatible_node(np, NULL, "fsl,mpc8572-gpio") 323 mpc8xxx_add_controller(np); 324 325 for_each_compatible_node(np, NULL, "fsl,mpc8610-gpio") 326 mpc8xxx_add_controller(np); 327 328 return 0; 329} 330arch_initcall(mpc8xxx_add_gpiochips); 331