1/* 2 * SMP support for power macintosh. 3 * 4 * We support both the old "powersurge" SMP architecture 5 * and the current Core99 (G4 PowerMac) machines. 6 * 7 * Note that we don't support the very first rev. of 8 * Apple/DayStar 2 CPUs board, the one with the funky 9 * watchdog. Hopefully, none of these should be there except 10 * maybe internally to Apple. I should probably still add some 11 * code to detect this card though and disable SMP. --BenH. 12 * 13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net) 14 * and Ben Herrenschmidt <benh@kernel.crashing.org>. 15 * 16 * Support for DayStar quad CPU cards 17 * Copyright (C) XLR8, Inc. 1994-2000 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 22 * 2 of the License, or (at your option) any later version. 23 */ 24#include <linux/kernel.h> 25#include <linux/sched.h> 26#include <linux/smp.h> 27#include <linux/interrupt.h> 28#include <linux/kernel_stat.h> 29#include <linux/delay.h> 30#include <linux/init.h> 31#include <linux/spinlock.h> 32#include <linux/errno.h> 33#include <linux/hardirq.h> 34#include <linux/cpu.h> 35#include <linux/compiler.h> 36 37#include <asm/ptrace.h> 38#include <asm/atomic.h> 39#include <asm/code-patching.h> 40#include <asm/irq.h> 41#include <asm/page.h> 42#include <asm/pgtable.h> 43#include <asm/sections.h> 44#include <asm/io.h> 45#include <asm/prom.h> 46#include <asm/smp.h> 47#include <asm/machdep.h> 48#include <asm/pmac_feature.h> 49#include <asm/time.h> 50#include <asm/mpic.h> 51#include <asm/cacheflush.h> 52#include <asm/keylargo.h> 53#include <asm/pmac_low_i2c.h> 54#include <asm/pmac_pfunc.h> 55 56#include "pmac.h" 57 58#undef DEBUG 59 60#ifdef DEBUG 61#define DBG(fmt...) udbg_printf(fmt) 62#else 63#define DBG(fmt...) 64#endif 65 66extern void __secondary_start_pmac_0(void); 67extern int pmac_pfunc_base_install(void); 68 69static void (*pmac_tb_freeze)(int freeze); 70static u64 timebase; 71static int tb_req; 72 73#ifdef CONFIG_PPC32 74 75/* 76 * Powersurge (old powermac SMP) support. 77 */ 78 79/* Addresses for powersurge registers */ 80#define HAMMERHEAD_BASE 0xf8000000 81#define HHEAD_CONFIG 0x90 82#define HHEAD_SEC_INTR 0xc0 83 84/* register for interrupting the primary processor on the powersurge */ 85/* N.B. this is actually the ethernet ROM! */ 86#define PSURGE_PRI_INTR 0xf3019000 87 88/* register for storing the start address for the secondary processor */ 89/* N.B. this is the PCI config space address register for the 1st bridge */ 90#define PSURGE_START 0xf2800000 91 92/* Daystar/XLR8 4-CPU card */ 93#define PSURGE_QUAD_REG_ADDR 0xf8800000 94 95#define PSURGE_QUAD_IRQ_SET 0 96#define PSURGE_QUAD_IRQ_CLR 1 97#define PSURGE_QUAD_IRQ_PRIMARY 2 98#define PSURGE_QUAD_CKSTOP_CTL 3 99#define PSURGE_QUAD_PRIMARY_ARB 4 100#define PSURGE_QUAD_BOARD_ID 6 101#define PSURGE_QUAD_WHICH_CPU 7 102#define PSURGE_QUAD_CKSTOP_RDBK 8 103#define PSURGE_QUAD_RESET_CTL 11 104 105#define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v))) 106#define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f) 107#define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v))) 108#define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v))) 109 110/* virtual addresses for the above */ 111static volatile u8 __iomem *hhead_base; 112static volatile u8 __iomem *quad_base; 113static volatile u32 __iomem *psurge_pri_intr; 114static volatile u8 __iomem *psurge_sec_intr; 115static volatile u32 __iomem *psurge_start; 116 117/* values for psurge_type */ 118#define PSURGE_NONE -1 119#define PSURGE_DUAL 0 120#define PSURGE_QUAD_OKEE 1 121#define PSURGE_QUAD_COTTON 2 122#define PSURGE_QUAD_ICEGRASS 3 123 124/* what sort of powersurge board we have */ 125static int psurge_type = PSURGE_NONE; 126 127/* 128 * Set and clear IPIs for powersurge. 129 */ 130static inline void psurge_set_ipi(int cpu) 131{ 132 if (psurge_type == PSURGE_NONE) 133 return; 134 if (cpu == 0) 135 in_be32(psurge_pri_intr); 136 else if (psurge_type == PSURGE_DUAL) 137 out_8(psurge_sec_intr, 0); 138 else 139 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu); 140} 141 142static inline void psurge_clr_ipi(int cpu) 143{ 144 if (cpu > 0) { 145 switch(psurge_type) { 146 case PSURGE_DUAL: 147 out_8(psurge_sec_intr, ~0); 148 case PSURGE_NONE: 149 break; 150 default: 151 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu); 152 } 153 } 154} 155 156/* 157 * On powersurge (old SMP powermac architecture) we don't have 158 * separate IPIs for separate messages like openpic does. Instead 159 * we have a bitmap for each processor, where a 1 bit means that 160 * the corresponding message is pending for that processor. 161 * Ideally each cpu's entry would be in a different cache line. 162 * -- paulus. 163 */ 164static unsigned long psurge_smp_message[NR_CPUS]; 165 166void psurge_smp_message_recv(void) 167{ 168 int cpu = smp_processor_id(); 169 int msg; 170 171 /* clear interrupt */ 172 psurge_clr_ipi(cpu); 173 174 if (num_online_cpus() < 2) 175 return; 176 177 /* make sure there is a message there */ 178 for (msg = 0; msg < 4; msg++) 179 if (test_and_clear_bit(msg, &psurge_smp_message[cpu])) 180 smp_message_recv(msg); 181} 182 183irqreturn_t psurge_primary_intr(int irq, void *d) 184{ 185 psurge_smp_message_recv(); 186 return IRQ_HANDLED; 187} 188 189static void smp_psurge_message_pass(int target, int msg) 190{ 191 int i; 192 193 if (num_online_cpus() < 2) 194 return; 195 196 for_each_online_cpu(i) { 197 if (target == MSG_ALL 198 || (target == MSG_ALL_BUT_SELF && i != smp_processor_id()) 199 || target == i) { 200 set_bit(msg, &psurge_smp_message[i]); 201 psurge_set_ipi(i); 202 } 203 } 204} 205 206/* 207 * Determine a quad card presence. We read the board ID register, we 208 * force the data bus to change to something else, and we read it again. 209 * It it's stable, then the register probably exist (ugh !) 210 */ 211static int __init psurge_quad_probe(void) 212{ 213 int type; 214 unsigned int i; 215 216 type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID); 217 if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS 218 || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 219 return PSURGE_DUAL; 220 221 /* looks OK, try a slightly more rigorous test */ 222 /* bogus is not necessarily cacheline-aligned, 223 though I don't suppose that really matters. -- paulus */ 224 for (i = 0; i < 100; i++) { 225 volatile u32 bogus[8]; 226 bogus[(0+i)%8] = 0x00000000; 227 bogus[(1+i)%8] = 0x55555555; 228 bogus[(2+i)%8] = 0xFFFFFFFF; 229 bogus[(3+i)%8] = 0xAAAAAAAA; 230 bogus[(4+i)%8] = 0x33333333; 231 bogus[(5+i)%8] = 0xCCCCCCCC; 232 bogus[(6+i)%8] = 0xCCCCCCCC; 233 bogus[(7+i)%8] = 0x33333333; 234 wmb(); 235 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory"); 236 mb(); 237 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 238 return PSURGE_DUAL; 239 } 240 return type; 241} 242 243static void __init psurge_quad_init(void) 244{ 245 int procbits; 246 247 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351); 248 procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU); 249 if (psurge_type == PSURGE_QUAD_ICEGRASS) 250 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 251 else 252 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits); 253 mdelay(33); 254 out_8(psurge_sec_intr, ~0); 255 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits); 256 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 257 if (psurge_type != PSURGE_QUAD_ICEGRASS) 258 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits); 259 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits); 260 mdelay(33); 261 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits); 262 mdelay(33); 263 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits); 264 mdelay(33); 265} 266 267static int __init smp_psurge_probe(void) 268{ 269 int i, ncpus; 270 struct device_node *dn; 271 272 /* We don't do SMP on the PPC601 -- paulus */ 273 if (PVR_VER(mfspr(SPRN_PVR)) == 1) 274 return 1; 275 276 /* 277 * The powersurge cpu board can be used in the generation 278 * of powermacs that have a socket for an upgradeable cpu card, 279 * including the 7500, 8500, 9500, 9600. 280 * The device tree doesn't tell you if you have 2 cpus because 281 * OF doesn't know anything about the 2nd processor. 282 * Instead we look for magic bits in magic registers, 283 * in the hammerhead memory controller in the case of the 284 * dual-cpu powersurge board. -- paulus. 285 */ 286 dn = of_find_node_by_name(NULL, "hammerhead"); 287 if (dn == NULL) 288 return 1; 289 of_node_put(dn); 290 291 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800); 292 quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024); 293 psurge_sec_intr = hhead_base + HHEAD_SEC_INTR; 294 295 psurge_type = psurge_quad_probe(); 296 if (psurge_type != PSURGE_DUAL) { 297 psurge_quad_init(); 298 /* All released cards using this HW design have 4 CPUs */ 299 ncpus = 4; 300 /* No sure how timebase sync works on those, let's use SW */ 301 smp_ops->give_timebase = smp_generic_give_timebase; 302 smp_ops->take_timebase = smp_generic_take_timebase; 303 } else { 304 iounmap(quad_base); 305 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { 306 /* not a dual-cpu card */ 307 iounmap(hhead_base); 308 psurge_type = PSURGE_NONE; 309 return 1; 310 } 311 ncpus = 2; 312 } 313 314 psurge_start = ioremap(PSURGE_START, 4); 315 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); 316 317 /* This is necessary because OF doesn't know about the 318 * secondary cpu(s), and thus there aren't nodes in the 319 * device tree for them, and smp_setup_cpu_maps hasn't 320 * set their bits in cpu_present_mask. 321 */ 322 if (ncpus > NR_CPUS) 323 ncpus = NR_CPUS; 324 for (i = 1; i < ncpus ; ++i) 325 set_cpu_present(i, true); 326 327 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); 328 329 return ncpus; 330} 331 332static void __init smp_psurge_kick_cpu(int nr) 333{ 334 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; 335 unsigned long a, flags; 336 int i, j; 337 338 /* Defining this here is evil ... but I prefer hiding that 339 * crap to avoid giving people ideas that they can do the 340 * same. 341 */ 342 extern volatile unsigned int cpu_callin_map[NR_CPUS]; 343 344 /* may need to flush here if secondary bats aren't setup */ 345 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) 346 asm volatile("dcbf 0,%0" : : "r" (a) : "memory"); 347 asm volatile("sync"); 348 349 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); 350 351 /* This is going to freeze the timeebase, we disable interrupts */ 352 local_irq_save(flags); 353 354 out_be32(psurge_start, start); 355 mb(); 356 357 psurge_set_ipi(nr); 358 359 /* 360 * We can't use udelay here because the timebase is now frozen. 361 */ 362 for (i = 0; i < 2000; ++i) 363 asm volatile("nop" : : : "memory"); 364 psurge_clr_ipi(nr); 365 366 /* 367 * Also, because the timebase is frozen, we must not return to the 368 * caller which will try to do udelay's etc... Instead, we wait -here- 369 * for the CPU to callin. 370 */ 371 for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) { 372 for (j = 1; j < 10000; j++) 373 asm volatile("nop" : : : "memory"); 374 asm volatile("sync" : : : "memory"); 375 } 376 if (!cpu_callin_map[nr]) 377 goto stuck; 378 379 /* And we do the TB sync here too for standard dual CPU cards */ 380 if (psurge_type == PSURGE_DUAL) { 381 while(!tb_req) 382 barrier(); 383 tb_req = 0; 384 mb(); 385 timebase = get_tb(); 386 mb(); 387 while (timebase) 388 barrier(); 389 mb(); 390 } 391 stuck: 392 /* now interrupt the secondary, restarting both TBs */ 393 if (psurge_type == PSURGE_DUAL) 394 psurge_set_ipi(1); 395 396 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); 397} 398 399static struct irqaction psurge_irqaction = { 400 .handler = psurge_primary_intr, 401 .flags = IRQF_DISABLED, 402 .name = "primary IPI", 403}; 404 405static void __init smp_psurge_setup_cpu(int cpu_nr) 406{ 407 if (cpu_nr != 0) 408 return; 409 410 /* reset the entry point so if we get another intr we won't 411 * try to startup again */ 412 out_be32(psurge_start, 0x100); 413 if (setup_irq(irq_create_mapping(NULL, 30), &psurge_irqaction)) 414 printk(KERN_ERR "Couldn't get primary IPI interrupt"); 415} 416 417void __init smp_psurge_take_timebase(void) 418{ 419 if (psurge_type != PSURGE_DUAL) 420 return; 421 422 tb_req = 1; 423 mb(); 424 while (!timebase) 425 barrier(); 426 mb(); 427 set_tb(timebase >> 32, timebase & 0xffffffff); 428 timebase = 0; 429 mb(); 430 set_dec(tb_ticks_per_jiffy/2); 431} 432 433void __init smp_psurge_give_timebase(void) 434{ 435 /* Nothing to do here */ 436} 437 438/* PowerSurge-style Macs */ 439struct smp_ops_t psurge_smp_ops = { 440 .message_pass = smp_psurge_message_pass, 441 .probe = smp_psurge_probe, 442 .kick_cpu = smp_psurge_kick_cpu, 443 .setup_cpu = smp_psurge_setup_cpu, 444 .give_timebase = smp_psurge_give_timebase, 445 .take_timebase = smp_psurge_take_timebase, 446}; 447#endif /* CONFIG_PPC32 - actually powersurge support */ 448 449/* 450 * Core 99 and later support 451 */ 452 453 454static void smp_core99_give_timebase(void) 455{ 456 unsigned long flags; 457 458 local_irq_save(flags); 459 460 while(!tb_req) 461 barrier(); 462 tb_req = 0; 463 (*pmac_tb_freeze)(1); 464 mb(); 465 timebase = get_tb(); 466 mb(); 467 while (timebase) 468 barrier(); 469 mb(); 470 (*pmac_tb_freeze)(0); 471 mb(); 472 473 local_irq_restore(flags); 474} 475 476 477static void __devinit smp_core99_take_timebase(void) 478{ 479 unsigned long flags; 480 481 local_irq_save(flags); 482 483 tb_req = 1; 484 mb(); 485 while (!timebase) 486 barrier(); 487 mb(); 488 set_tb(timebase >> 32, timebase & 0xffffffff); 489 timebase = 0; 490 mb(); 491 492 local_irq_restore(flags); 493} 494 495#ifdef CONFIG_PPC64 496/* 497 * G5s enable/disable the timebase via an i2c-connected clock chip. 498 */ 499static struct pmac_i2c_bus *pmac_tb_clock_chip_host; 500static u8 pmac_tb_pulsar_addr; 501 502static void smp_core99_cypress_tb_freeze(int freeze) 503{ 504 u8 data; 505 int rc; 506 507 /* Strangely, the device-tree says address is 0xd2, but darwin 508 * accesses 0xd0 ... 509 */ 510 pmac_i2c_setmode(pmac_tb_clock_chip_host, 511 pmac_i2c_mode_combined); 512 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 513 0xd0 | pmac_i2c_read, 514 1, 0x81, &data, 1); 515 if (rc != 0) 516 goto bail; 517 518 data = (data & 0xf3) | (freeze ? 0x00 : 0x0c); 519 520 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 521 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 522 0xd0 | pmac_i2c_write, 523 1, 0x81, &data, 1); 524 525 bail: 526 if (rc != 0) { 527 printk("Cypress Timebase %s rc: %d\n", 528 freeze ? "freeze" : "unfreeze", rc); 529 panic("Timebase freeze failed !\n"); 530 } 531} 532 533 534static void smp_core99_pulsar_tb_freeze(int freeze) 535{ 536 u8 data; 537 int rc; 538 539 pmac_i2c_setmode(pmac_tb_clock_chip_host, 540 pmac_i2c_mode_combined); 541 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 542 pmac_tb_pulsar_addr | pmac_i2c_read, 543 1, 0x2e, &data, 1); 544 if (rc != 0) 545 goto bail; 546 547 data = (data & 0x88) | (freeze ? 0x11 : 0x22); 548 549 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 550 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 551 pmac_tb_pulsar_addr | pmac_i2c_write, 552 1, 0x2e, &data, 1); 553 bail: 554 if (rc != 0) { 555 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n", 556 freeze ? "freeze" : "unfreeze", rc); 557 panic("Timebase freeze failed !\n"); 558 } 559} 560 561static void __init smp_core99_setup_i2c_hwsync(int ncpus) 562{ 563 struct device_node *cc = NULL; 564 struct device_node *p; 565 const char *name = NULL; 566 const u32 *reg; 567 int ok; 568 569 /* Look for the clock chip */ 570 while ((cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL) { 571 p = of_get_parent(cc); 572 ok = p && of_device_is_compatible(p, "uni-n-i2c"); 573 of_node_put(p); 574 if (!ok) 575 continue; 576 577 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc); 578 if (pmac_tb_clock_chip_host == NULL) 579 continue; 580 reg = of_get_property(cc, "reg", NULL); 581 if (reg == NULL) 582 continue; 583 switch (*reg) { 584 case 0xd2: 585 if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) { 586 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 587 pmac_tb_pulsar_addr = 0xd2; 588 name = "Pulsar"; 589 } else if (of_device_is_compatible(cc, "cy28508")) { 590 pmac_tb_freeze = smp_core99_cypress_tb_freeze; 591 name = "Cypress"; 592 } 593 break; 594 case 0xd4: 595 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 596 pmac_tb_pulsar_addr = 0xd4; 597 name = "Pulsar"; 598 break; 599 } 600 if (pmac_tb_freeze != NULL) 601 break; 602 } 603 if (pmac_tb_freeze != NULL) { 604 /* Open i2c bus for synchronous access */ 605 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) { 606 printk(KERN_ERR "Failed top open i2c bus for clock" 607 " sync, fallback to software sync !\n"); 608 goto no_i2c_sync; 609 } 610 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n", 611 name); 612 return; 613 } 614 no_i2c_sync: 615 pmac_tb_freeze = NULL; 616 pmac_tb_clock_chip_host = NULL; 617} 618 619 620 621/* 622 * Newer G5s uses a platform function 623 */ 624 625static void smp_core99_pfunc_tb_freeze(int freeze) 626{ 627 struct device_node *cpus; 628 struct pmf_args args; 629 630 cpus = of_find_node_by_path("/cpus"); 631 BUG_ON(cpus == NULL); 632 args.count = 1; 633 args.u[0].v = !freeze; 634 pmf_call_function(cpus, "cpu-timebase", &args); 635 of_node_put(cpus); 636} 637 638#else /* CONFIG_PPC64 */ 639 640/* 641 * SMP G4 use a GPIO to enable/disable the timebase. 642 */ 643 644static unsigned int core99_tb_gpio; /* Timebase freeze GPIO */ 645 646static void smp_core99_gpio_tb_freeze(int freeze) 647{ 648 if (freeze) 649 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4); 650 else 651 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0); 652 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0); 653} 654 655 656#endif /* !CONFIG_PPC64 */ 657 658/* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */ 659volatile static long int core99_l2_cache; 660volatile static long int core99_l3_cache; 661 662static void __devinit core99_init_caches(int cpu) 663{ 664#ifndef CONFIG_PPC64 665 if (!cpu_has_feature(CPU_FTR_L2CR)) 666 return; 667 668 if (cpu == 0) { 669 core99_l2_cache = _get_L2CR(); 670 printk("CPU0: L2CR is %lx\n", core99_l2_cache); 671 } else { 672 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR()); 673 _set_L2CR(0); 674 _set_L2CR(core99_l2_cache); 675 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache); 676 } 677 678 if (!cpu_has_feature(CPU_FTR_L3CR)) 679 return; 680 681 if (cpu == 0){ 682 core99_l3_cache = _get_L3CR(); 683 printk("CPU0: L3CR is %lx\n", core99_l3_cache); 684 } else { 685 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR()); 686 _set_L3CR(0); 687 _set_L3CR(core99_l3_cache); 688 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache); 689 } 690#endif /* !CONFIG_PPC64 */ 691} 692 693static void __init smp_core99_setup(int ncpus) 694{ 695#ifdef CONFIG_PPC64 696 697 /* i2c based HW sync on some G5s */ 698 if (of_machine_is_compatible("PowerMac7,2") || 699 of_machine_is_compatible("PowerMac7,3") || 700 of_machine_is_compatible("RackMac3,1")) 701 smp_core99_setup_i2c_hwsync(ncpus); 702 703 /* pfunc based HW sync on recent G5s */ 704 if (pmac_tb_freeze == NULL) { 705 struct device_node *cpus = 706 of_find_node_by_path("/cpus"); 707 if (cpus && 708 of_get_property(cpus, "platform-cpu-timebase", NULL)) { 709 pmac_tb_freeze = smp_core99_pfunc_tb_freeze; 710 printk(KERN_INFO "Processor timebase sync using" 711 " platform function\n"); 712 } 713 } 714 715#else /* CONFIG_PPC64 */ 716 717 /* GPIO based HW sync on ppc32 Core99 */ 718 if (pmac_tb_freeze == NULL && !of_machine_is_compatible("MacRISC4")) { 719 struct device_node *cpu; 720 const u32 *tbprop = NULL; 721 722 core99_tb_gpio = KL_GPIO_TB_ENABLE; /* default value */ 723 cpu = of_find_node_by_type(NULL, "cpu"); 724 if (cpu != NULL) { 725 tbprop = of_get_property(cpu, "timebase-enable", NULL); 726 if (tbprop) 727 core99_tb_gpio = *tbprop; 728 of_node_put(cpu); 729 } 730 pmac_tb_freeze = smp_core99_gpio_tb_freeze; 731 printk(KERN_INFO "Processor timebase sync using" 732 " GPIO 0x%02x\n", core99_tb_gpio); 733 } 734 735#endif /* CONFIG_PPC64 */ 736 737 /* No timebase sync, fallback to software */ 738 if (pmac_tb_freeze == NULL) { 739 smp_ops->give_timebase = smp_generic_give_timebase; 740 smp_ops->take_timebase = smp_generic_take_timebase; 741 printk(KERN_INFO "Processor timebase sync using software\n"); 742 } 743 744#ifndef CONFIG_PPC64 745 { 746 int i; 747 748 for (i = 1; i < ncpus; ++i) 749 set_hard_smp_processor_id(i, i); 750 } 751#endif 752 753 /* 32 bits SMP can't NAP */ 754 if (!of_machine_is_compatible("MacRISC4")) 755 powersave_nap = 0; 756} 757 758static int __init smp_core99_probe(void) 759{ 760 struct device_node *cpus; 761 int ncpus = 0; 762 763 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345); 764 765 /* Count CPUs in the device-tree */ 766 for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;) 767 ++ncpus; 768 769 printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus); 770 771 /* Nothing more to do if less than 2 of them */ 772 if (ncpus <= 1) 773 return 1; 774 775 /* We need to perform some early initialisations before we can start 776 * setting up SMP as we are running before initcalls 777 */ 778 pmac_pfunc_base_install(); 779 pmac_i2c_init(); 780 781 /* Setup various bits like timebase sync method, ability to nap, ... */ 782 smp_core99_setup(ncpus); 783 784 /* Install IPIs */ 785 mpic_request_ipis(); 786 787 /* Collect l2cr and l3cr values from CPU 0 */ 788 core99_init_caches(0); 789 790 return ncpus; 791} 792 793static void __devinit smp_core99_kick_cpu(int nr) 794{ 795 unsigned int save_vector; 796 unsigned long target, flags; 797 unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100); 798 799 if (nr < 0 || nr > 3) 800 return; 801 802 if (ppc_md.progress) 803 ppc_md.progress("smp_core99_kick_cpu", 0x346); 804 805 local_irq_save(flags); 806 807 /* Save reset vector */ 808 save_vector = *vector; 809 810 /* Setup fake reset vector that does 811 * b __secondary_start_pmac_0 + nr*8 812 */ 813 target = (unsigned long) __secondary_start_pmac_0 + nr * 8; 814 patch_branch(vector, target, BRANCH_SET_LINK); 815 816 /* Put some life in our friend */ 817 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0); 818 819 mdelay(1); 820 821 /* Restore our exception vector */ 822 *vector = save_vector; 823 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4); 824 825 local_irq_restore(flags); 826 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347); 827} 828 829static void __devinit smp_core99_setup_cpu(int cpu_nr) 830{ 831 /* Setup L2/L3 */ 832 if (cpu_nr != 0) 833 core99_init_caches(cpu_nr); 834 835 /* Setup openpic */ 836 mpic_setup_this_cpu(); 837 838 if (cpu_nr == 0) { 839#ifdef CONFIG_PPC64 840 extern void g5_phy_disable_cpu1(void); 841 842 /* Close i2c bus if it was used for tb sync */ 843 if (pmac_tb_clock_chip_host) { 844 pmac_i2c_close(pmac_tb_clock_chip_host); 845 pmac_tb_clock_chip_host = NULL; 846 } 847 848 /* If we didn't start the second CPU, we must take 849 * it off the bus 850 */ 851 if (of_machine_is_compatible("MacRISC4") && 852 num_online_cpus() < 2) 853 g5_phy_disable_cpu1(); 854#endif /* CONFIG_PPC64 */ 855 856 if (ppc_md.progress) 857 ppc_md.progress("core99_setup_cpu 0 done", 0x349); 858 } 859} 860 861 862#if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32) 863 864int smp_core99_cpu_disable(void) 865{ 866 set_cpu_online(smp_processor_id(), false); 867 868 mpic_cpu_set_priority(0xf); 869 asm volatile("mtdec %0" : : "r" (0x7fffffff)); 870 mb(); 871 udelay(20); 872 asm volatile("mtdec %0" : : "r" (0x7fffffff)); 873 return 0; 874} 875 876static int cpu_dead[NR_CPUS]; 877 878void pmac32_cpu_die(void) 879{ 880 local_irq_disable(); 881 cpu_dead[smp_processor_id()] = 1; 882 mb(); 883 low_cpu_die(); 884} 885 886void smp_core99_cpu_die(unsigned int cpu) 887{ 888 int timeout; 889 890 timeout = 1000; 891 while (!cpu_dead[cpu]) { 892 if (--timeout == 0) { 893 printk("CPU %u refused to die!\n", cpu); 894 break; 895 } 896 msleep(1); 897 } 898 cpu_dead[cpu] = 0; 899} 900 901#endif /* CONFIG_HOTPLUG_CPU && CONFIG_PP32 */ 902 903/* Core99 Macs (dual G4s and G5s) */ 904struct smp_ops_t core99_smp_ops = { 905 .message_pass = smp_mpic_message_pass, 906 .probe = smp_core99_probe, 907 .kick_cpu = smp_core99_kick_cpu, 908 .setup_cpu = smp_core99_setup_cpu, 909 .give_timebase = smp_core99_give_timebase, 910 .take_timebase = smp_core99_take_timebase, 911#if defined(CONFIG_HOTPLUG_CPU) 912# if defined(CONFIG_PPC32) 913 .cpu_disable = smp_core99_cpu_disable, 914 .cpu_die = smp_core99_cpu_die, 915# endif 916# if defined(CONFIG_PPC64) 917 .cpu_disable = generic_cpu_disable, 918 .cpu_die = generic_cpu_die, 919 /* intentionally do *NOT* assign cpu_enable, 920 * the generic code will use kick_cpu then! */ 921# endif 922#endif 923}; 924 925void __init pmac_setup_smp(void) 926{ 927 struct device_node *np; 928 929 /* Check for Core99 */ 930 np = of_find_node_by_name(NULL, "uni-n"); 931 if (!np) 932 np = of_find_node_by_name(NULL, "u3"); 933 if (!np) 934 np = of_find_node_by_name(NULL, "u4"); 935 if (np) { 936 of_node_put(np); 937 smp_ops = &core99_smp_ops; 938 } 939#ifdef CONFIG_PPC32 940 else { 941 /* We have to set bits in cpu_possible_mask here since the 942 * secondary CPU(s) aren't in the device tree. Various 943 * things won't be initialized for CPUs not in the possible 944 * map, so we really need to fix it up here. 945 */ 946 int cpu; 947 948 for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu) 949 set_cpu_possible(cpu, true); 950 smp_ops = &psurge_smp_ops; 951 } 952#endif /* CONFIG_PPC32 */ 953} 954