1/* 2 * PCI code for the Freescale MPC52xx embedded CPU. 3 * 4 * Copyright (C) 2006 Secret Lab Technologies Ltd. 5 * Grant Likely <grant.likely@secretlab.ca> 6 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com> 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 */ 12 13#undef DEBUG 14 15#include <asm/pci.h> 16#include <asm/mpc52xx.h> 17#include <asm/delay.h> 18#include <asm/machdep.h> 19#include <linux/kernel.h> 20 21 22/* ======================================================================== */ 23/* Structures mapping & Defines for PCI Unit */ 24/* ======================================================================== */ 25 26#define MPC52xx_PCI_GSCR_BM 0x40000000 27#define MPC52xx_PCI_GSCR_PE 0x20000000 28#define MPC52xx_PCI_GSCR_SE 0x10000000 29#define MPC52xx_PCI_GSCR_XLB2PCI_MASK 0x07000000 30#define MPC52xx_PCI_GSCR_XLB2PCI_SHIFT 24 31#define MPC52xx_PCI_GSCR_IPG2PCI_MASK 0x00070000 32#define MPC52xx_PCI_GSCR_IPG2PCI_SHIFT 16 33#define MPC52xx_PCI_GSCR_BME 0x00004000 34#define MPC52xx_PCI_GSCR_PEE 0x00002000 35#define MPC52xx_PCI_GSCR_SEE 0x00001000 36#define MPC52xx_PCI_GSCR_PR 0x00000001 37 38 39#define MPC52xx_PCI_IWBTAR_TRANSLATION(proc_ad,pci_ad,size) \ 40 ( ( (proc_ad) & 0xff000000 ) | \ 41 ( (((size) - 1) >> 8) & 0x00ff0000 ) | \ 42 ( ((pci_ad) >> 16) & 0x0000ff00 ) ) 43 44#define MPC52xx_PCI_IWCR_PACK(win0,win1,win2) (((win0) << 24) | \ 45 ((win1) << 16) | \ 46 ((win2) << 8)) 47 48#define MPC52xx_PCI_IWCR_DISABLE 0x0 49#define MPC52xx_PCI_IWCR_ENABLE 0x1 50#define MPC52xx_PCI_IWCR_READ 0x0 51#define MPC52xx_PCI_IWCR_READ_LINE 0x2 52#define MPC52xx_PCI_IWCR_READ_MULTI 0x4 53#define MPC52xx_PCI_IWCR_MEM 0x0 54#define MPC52xx_PCI_IWCR_IO 0x8 55 56#define MPC52xx_PCI_TCR_P 0x01000000 57#define MPC52xx_PCI_TCR_LD 0x00010000 58#define MPC52xx_PCI_TCR_WCT8 0x00000008 59 60#define MPC52xx_PCI_TBATR_DISABLE 0x0 61#define MPC52xx_PCI_TBATR_ENABLE 0x1 62 63struct mpc52xx_pci { 64 u32 idr; /* PCI + 0x00 */ 65 u32 scr; /* PCI + 0x04 */ 66 u32 ccrir; /* PCI + 0x08 */ 67 u32 cr1; /* PCI + 0x0C */ 68 u32 bar0; /* PCI + 0x10 */ 69 u32 bar1; /* PCI + 0x14 */ 70 u8 reserved1[16]; /* PCI + 0x18 */ 71 u32 ccpr; /* PCI + 0x28 */ 72 u32 sid; /* PCI + 0x2C */ 73 u32 erbar; /* PCI + 0x30 */ 74 u32 cpr; /* PCI + 0x34 */ 75 u8 reserved2[4]; /* PCI + 0x38 */ 76 u32 cr2; /* PCI + 0x3C */ 77 u8 reserved3[32]; /* PCI + 0x40 */ 78 u32 gscr; /* PCI + 0x60 */ 79 u32 tbatr0; /* PCI + 0x64 */ 80 u32 tbatr1; /* PCI + 0x68 */ 81 u32 tcr; /* PCI + 0x6C */ 82 u32 iw0btar; /* PCI + 0x70 */ 83 u32 iw1btar; /* PCI + 0x74 */ 84 u32 iw2btar; /* PCI + 0x78 */ 85 u8 reserved4[4]; /* PCI + 0x7C */ 86 u32 iwcr; /* PCI + 0x80 */ 87 u32 icr; /* PCI + 0x84 */ 88 u32 isr; /* PCI + 0x88 */ 89 u32 arb; /* PCI + 0x8C */ 90 u8 reserved5[104]; /* PCI + 0x90 */ 91 u32 car; /* PCI + 0xF8 */ 92 u8 reserved6[4]; /* PCI + 0xFC */ 93}; 94 95/* MPC5200 device tree match tables */ 96const struct of_device_id mpc52xx_pci_ids[] __initdata = { 97 { .type = "pci", .compatible = "fsl,mpc5200-pci", }, 98 { .type = "pci", .compatible = "mpc5200-pci", }, 99 {} 100}; 101 102/* ======================================================================== */ 103/* PCI configuration access */ 104/* ======================================================================== */ 105 106static int 107mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, 108 int offset, int len, u32 *val) 109{ 110 struct pci_controller *hose = pci_bus_to_host(bus); 111 u32 value; 112 113 if (ppc_md.pci_exclude_device) 114 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 115 return PCIBIOS_DEVICE_NOT_FOUND; 116 117 out_be32(hose->cfg_addr, 118 (1 << 31) | 119 (bus->number << 16) | 120 (devfn << 8) | 121 (offset & 0xfc)); 122 mb(); 123 124#if defined(CONFIG_PPC_MPC5200_BUGFIX) 125 if (bus->number) { 126 switch (len) { 127 case 1: 128 value = in_8(((u8 __iomem *)hose->cfg_data) + 129 (offset & 3)); 130 break; 131 case 2: 132 value = in_le16(((u16 __iomem *)hose->cfg_data) + 133 ((offset>>1) & 1)); 134 break; 135 136 default: 137 value = in_le16((u16 __iomem *)hose->cfg_data) | 138 (in_le16(((u16 __iomem *)hose->cfg_data) + 1) << 16); 139 break; 140 } 141 } 142 else 143#endif 144 { 145 value = in_le32(hose->cfg_data); 146 147 if (len != 4) { 148 value >>= ((offset & 0x3) << 3); 149 value &= 0xffffffff >> (32 - (len << 3)); 150 } 151 } 152 153 *val = value; 154 155 out_be32(hose->cfg_addr, 0); 156 mb(); 157 158 return PCIBIOS_SUCCESSFUL; 159} 160 161static int 162mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, 163 int offset, int len, u32 val) 164{ 165 struct pci_controller *hose = pci_bus_to_host(bus); 166 u32 value, mask; 167 168 if (ppc_md.pci_exclude_device) 169 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 170 return PCIBIOS_DEVICE_NOT_FOUND; 171 172 out_be32(hose->cfg_addr, 173 (1 << 31) | 174 (bus->number << 16) | 175 (devfn << 8) | 176 (offset & 0xfc)); 177 mb(); 178 179#if defined(CONFIG_PPC_MPC5200_BUGFIX) 180 if (bus->number) { 181 switch (len) { 182 case 1: 183 out_8(((u8 __iomem *)hose->cfg_data) + 184 (offset & 3), val); 185 break; 186 case 2: 187 out_le16(((u16 __iomem *)hose->cfg_data) + 188 ((offset>>1) & 1), val); 189 break; 190 191 default: 192 out_le16((u16 __iomem *)hose->cfg_data, 193 (u16)val); 194 out_le16(((u16 __iomem *)hose->cfg_data) + 1, 195 (u16)(val>>16)); 196 break; 197 } 198 } 199 else 200#endif 201 { 202 if (len != 4) { 203 value = in_le32(hose->cfg_data); 204 205 offset = (offset & 0x3) << 3; 206 mask = (0xffffffff >> (32 - (len << 3))); 207 mask <<= offset; 208 209 value &= ~mask; 210 val = value | ((val << offset) & mask); 211 } 212 213 out_le32(hose->cfg_data, val); 214 } 215 mb(); 216 217 out_be32(hose->cfg_addr, 0); 218 mb(); 219 220 return PCIBIOS_SUCCESSFUL; 221} 222 223static struct pci_ops mpc52xx_pci_ops = { 224 .read = mpc52xx_pci_read_config, 225 .write = mpc52xx_pci_write_config 226}; 227 228 229/* ======================================================================== */ 230/* PCI setup */ 231/* ======================================================================== */ 232 233static void __init 234mpc52xx_pci_setup(struct pci_controller *hose, 235 struct mpc52xx_pci __iomem *pci_regs, phys_addr_t pci_phys) 236{ 237 struct resource *res; 238 u32 tmp; 239 int iwcr0 = 0, iwcr1 = 0, iwcr2 = 0; 240 241 pr_debug("mpc52xx_pci_setup(hose=%p, pci_regs=%p)\n", hose, pci_regs); 242 243 /* pci_process_bridge_OF_ranges() found all our addresses for us; 244 * now store them in the right places */ 245 hose->cfg_addr = &pci_regs->car; 246 hose->cfg_data = hose->io_base_virt; 247 248 /* Control regs */ 249 tmp = in_be32(&pci_regs->scr); 250 tmp |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 251 out_be32(&pci_regs->scr, tmp); 252 253 /* Memory windows */ 254 res = &hose->mem_resources[0]; 255 if (res->flags) { 256 pr_debug("mem_resource[0] = " 257 "{.start=%llx, .end=%llx, .flags=%llx}\n", 258 (unsigned long long)res->start, 259 (unsigned long long)res->end, 260 (unsigned long long)res->flags); 261 out_be32(&pci_regs->iw0btar, 262 MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start, 263 res->end - res->start + 1)); 264 iwcr0 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_MEM; 265 if (res->flags & IORESOURCE_PREFETCH) 266 iwcr0 |= MPC52xx_PCI_IWCR_READ_MULTI; 267 else 268 iwcr0 |= MPC52xx_PCI_IWCR_READ; 269 } 270 271 res = &hose->mem_resources[1]; 272 if (res->flags) { 273 pr_debug("mem_resource[1] = {.start=%x, .end=%x, .flags=%lx}\n", 274 res->start, res->end, res->flags); 275 out_be32(&pci_regs->iw1btar, 276 MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start, 277 res->end - res->start + 1)); 278 iwcr1 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_MEM; 279 if (res->flags & IORESOURCE_PREFETCH) 280 iwcr1 |= MPC52xx_PCI_IWCR_READ_MULTI; 281 else 282 iwcr1 |= MPC52xx_PCI_IWCR_READ; 283 } 284 285 /* IO resources */ 286 res = &hose->io_resource; 287 if (!res) { 288 printk(KERN_ERR "%s: Didn't find IO resources\n", __FILE__); 289 return; 290 } 291 pr_debug(".io_resource={.start=%llx,.end=%llx,.flags=%llx} " 292 ".io_base_phys=0x%p\n", 293 (unsigned long long)res->start, 294 (unsigned long long)res->end, 295 (unsigned long long)res->flags, (void*)hose->io_base_phys); 296 out_be32(&pci_regs->iw2btar, 297 MPC52xx_PCI_IWBTAR_TRANSLATION(hose->io_base_phys, 298 res->start, 299 res->end - res->start + 1)); 300 iwcr2 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_IO; 301 302 /* Set all the IWCR fields at once; they're in the same reg */ 303 out_be32(&pci_regs->iwcr, MPC52xx_PCI_IWCR_PACK(iwcr0, iwcr1, iwcr2)); 304 305 /* Map IMMR onto PCI bus */ 306 pci_phys &= 0xfffc0000; /* bar0 has only 14 significant bits */ 307 out_be32(&pci_regs->tbatr0, MPC52xx_PCI_TBATR_ENABLE | pci_phys); 308 out_be32(&pci_regs->bar0, PCI_BASE_ADDRESS_MEM_PREFETCH | pci_phys); 309 310 /* Map memory onto PCI bus */ 311 out_be32(&pci_regs->tbatr1, MPC52xx_PCI_TBATR_ENABLE); 312 out_be32(&pci_regs->bar1, PCI_BASE_ADDRESS_MEM_PREFETCH); 313 314 out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD | MPC52xx_PCI_TCR_WCT8); 315 316 tmp = in_be32(&pci_regs->gscr); 317 318 /* Make sure the PCI bridge is out of reset */ 319 out_be32(&pci_regs->gscr, tmp & ~MPC52xx_PCI_GSCR_PR); 320} 321 322static void 323mpc52xx_pci_fixup_resources(struct pci_dev *dev) 324{ 325 int i; 326 327 pr_debug("mpc52xx_pci_fixup_resources() %.4x:%.4x\n", 328 dev->vendor, dev->device); 329 330 /* We don't rely on boot loader for PCI and resets all 331 devices */ 332 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 333 struct resource *res = &dev->resource[i]; 334 if (res->end > res->start) { /* Only valid resources */ 335 res->end -= res->start; 336 res->start = 0; 337 res->flags |= IORESOURCE_UNSET; 338 } 339 } 340 341 /* The PCI Host bridge of MPC52xx has a prefetch memory resource 342 fixed to 1Gb. Doesn't fit in the resource system so we remove it */ 343 if ( (dev->vendor == PCI_VENDOR_ID_MOTOROLA) && 344 ( dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200 345 || dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200B) ) { 346 struct resource *res = &dev->resource[1]; 347 res->start = res->end = res->flags = 0; 348 } 349} 350 351int __init 352mpc52xx_add_bridge(struct device_node *node) 353{ 354 int len; 355 struct mpc52xx_pci __iomem *pci_regs; 356 struct pci_controller *hose; 357 const int *bus_range; 358 struct resource rsrc; 359 360 pr_debug("Adding MPC52xx PCI host bridge %s\n", node->full_name); 361 362 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS); 363 364 if (of_address_to_resource(node, 0, &rsrc) != 0) { 365 printk(KERN_ERR "Can't get %s resources\n", node->full_name); 366 return -EINVAL; 367 } 368 369 bus_range = of_get_property(node, "bus-range", &len); 370 if (bus_range == NULL || len < 2 * sizeof(int)) { 371 printk(KERN_WARNING "Can't get %s bus-range, assume bus 0\n", 372 node->full_name); 373 bus_range = NULL; 374 } 375 376 /* There are some PCI quirks on the 52xx, register the hook to 377 * fix them. */ 378 ppc_md.pcibios_fixup_resources = mpc52xx_pci_fixup_resources; 379 380 /* Alloc and initialize the pci controller. Values in the device 381 * tree are needed to configure the 52xx PCI controller. Rather 382 * than parse the tree here, let pci_process_bridge_OF_ranges() 383 * do it for us and extract the values after the fact */ 384 hose = pcibios_alloc_controller(node); 385 if (!hose) 386 return -ENOMEM; 387 388 hose->first_busno = bus_range ? bus_range[0] : 0; 389 hose->last_busno = bus_range ? bus_range[1] : 0xff; 390 391 hose->ops = &mpc52xx_pci_ops; 392 393 pci_regs = ioremap(rsrc.start, rsrc.end - rsrc.start + 1); 394 if (!pci_regs) 395 return -ENOMEM; 396 397 pci_process_bridge_OF_ranges(hose, node, 1); 398 399 /* Finish setting up PCI using values obtained by 400 * pci_proces_bridge_OF_ranges */ 401 mpc52xx_pci_setup(hose, pci_regs, rsrc.start); 402 403 return 0; 404} 405 406void __init mpc52xx_setup_pci(void) 407{ 408 struct device_node *pci; 409 410 pci = of_find_matching_node(NULL, mpc52xx_pci_ids); 411 if (!pci) 412 return; 413 414 mpc52xx_add_bridge(pci); 415 of_node_put(pci); 416} 417