1/* 2 * This file contains the routines for flushing entries from the 3 * TLB and MMU hash table. 4 * 5 * Derived from arch/ppc64/mm/init.c: 6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 7 * 8 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) 9 * and Cort Dougan (PReP) (cort@cs.nmt.edu) 10 * Copyright (C) 1996 Paul Mackerras 11 * 12 * Derived from "arch/i386/mm/init.c" 13 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds 14 * 15 * Dave Engebretsen <engebret@us.ibm.com> 16 * Rework for PPC64 port. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License 20 * as published by the Free Software Foundation; either version 21 * 2 of the License, or (at your option) any later version. 22 */ 23 24#include <linux/kernel.h> 25#include <linux/mm.h> 26#include <linux/init.h> 27#include <linux/percpu.h> 28#include <linux/hardirq.h> 29#include <asm/pgalloc.h> 30#include <asm/tlbflush.h> 31#include <asm/tlb.h> 32#include <asm/bug.h> 33 34DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch); 35 36/* 37 * A linux PTE was changed and the corresponding hash table entry 38 * neesd to be flushed. This function will either perform the flush 39 * immediately or will batch it up if the current CPU has an active 40 * batch on it. 41 * 42 * Must be called from within some kind of spinlock/non-preempt region... 43 */ 44void hpte_need_flush(struct mm_struct *mm, unsigned long addr, 45 pte_t *ptep, unsigned long pte, int huge) 46{ 47 struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch); 48 unsigned long vsid, vaddr; 49 unsigned int psize; 50 int ssize; 51 real_pte_t rpte; 52 int i; 53 54 i = batch->index; 55 56 /* Get page size (maybe move back to caller). 57 * 58 * NOTE: when using special 64K mappings in 4K environment like 59 * for SPEs, we obtain the page size from the slice, which thus 60 * must still exist (and thus the VMA not reused) at the time 61 * of this call 62 */ 63 if (huge) { 64#ifdef CONFIG_HUGETLB_PAGE 65 psize = get_slice_psize(mm, addr); 66 /* Mask the address for the correct page size */ 67 addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1); 68#else 69 BUG(); 70 psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */ 71#endif 72 } else { 73 psize = pte_pagesize_index(mm, addr, pte); 74 /* Mask the address for the standard page size. If we 75 * have a 64k page kernel, but the hardware does not 76 * support 64k pages, this might be different from the 77 * hardware page size encoded in the slice table. */ 78 addr &= PAGE_MASK; 79 } 80 81 82 /* Build full vaddr */ 83 if (!is_kernel_addr(addr)) { 84 ssize = user_segment_size(addr); 85 vsid = get_vsid(mm->context.id, addr, ssize); 86 WARN_ON(vsid == 0); 87 } else { 88 vsid = get_kernel_vsid(addr, mmu_kernel_ssize); 89 ssize = mmu_kernel_ssize; 90 } 91 vaddr = hpt_va(addr, vsid, ssize); 92 rpte = __real_pte(__pte(pte), ptep); 93 94 /* 95 * Check if we have an active batch on this CPU. If not, just 96 * flush now and return. For now, we don global invalidates 97 * in that case, might be worth testing the mm cpu mask though 98 * and decide to use local invalidates instead... 99 */ 100 if (!batch->active) { 101 flush_hash_page(vaddr, rpte, psize, ssize, 0); 102 return; 103 } 104 105 /* 106 * This can happen when we are in the middle of a TLB batch and 107 * we encounter memory pressure (eg copy_page_range when it tries 108 * to allocate a new pte). If we have to reclaim memory and end 109 * up scanning and resetting referenced bits then our batch context 110 * will change mid stream. 111 * 112 * We also need to ensure only one page size is present in a given 113 * batch 114 */ 115 if (i != 0 && (mm != batch->mm || batch->psize != psize || 116 batch->ssize != ssize)) { 117 __flush_tlb_pending(batch); 118 i = 0; 119 } 120 if (i == 0) { 121 batch->mm = mm; 122 batch->psize = psize; 123 batch->ssize = ssize; 124 } 125 batch->pte[i] = rpte; 126 batch->vaddr[i] = vaddr; 127 batch->index = ++i; 128 if (i >= PPC64_TLB_BATCH_NR) 129 __flush_tlb_pending(batch); 130} 131 132/* 133 * This function is called when terminating an mmu batch or when a batch 134 * is full. It will perform the flush of all the entries currently stored 135 * in a batch. 136 * 137 * Must be called from within some kind of spinlock/non-preempt region... 138 */ 139void __flush_tlb_pending(struct ppc64_tlb_batch *batch) 140{ 141 const struct cpumask *tmp; 142 int i, local = 0; 143 144 i = batch->index; 145 tmp = cpumask_of(smp_processor_id()); 146 if (cpumask_equal(mm_cpumask(batch->mm), tmp)) 147 local = 1; 148 if (i == 1) 149 flush_hash_page(batch->vaddr[0], batch->pte[0], 150 batch->psize, batch->ssize, local); 151 else 152 flush_hash_range(i, local); 153 batch->index = 0; 154} 155 156void tlb_flush(struct mmu_gather *tlb) 157{ 158 struct ppc64_tlb_batch *tlbbatch = &__get_cpu_var(ppc64_tlb_batch); 159 160 /* If there's a TLB batch pending, then we must flush it because the 161 * pages are going to be freed and we really don't want to have a CPU 162 * access a freed page because it has a stale TLB 163 */ 164 if (tlbbatch->index) 165 __flush_tlb_pending(tlbbatch); 166 167 /* Push out batch of freed page tables */ 168 pte_free_finish(); 169} 170 171/** 172 * __flush_hash_table_range - Flush all HPTEs for a given address range 173 * from the hash table (and the TLB). But keeps 174 * the linux PTEs intact. 175 * 176 * @mm : mm_struct of the target address space (generally init_mm) 177 * @start : starting address 178 * @end : ending address (not included in the flush) 179 * 180 * This function is mostly to be used by some IO hotplug code in order 181 * to remove all hash entries from a given address range used to map IO 182 * space on a removed PCI-PCI bidge without tearing down the full mapping 183 * since 64K pages may overlap with other bridges when using 64K pages 184 * with 4K HW pages on IO space. 185 * 186 * Because of that usage pattern, it's only available with CONFIG_HOTPLUG 187 * and is implemented for small size rather than speed. 188 */ 189#ifdef CONFIG_HOTPLUG 190 191void __flush_hash_table_range(struct mm_struct *mm, unsigned long start, 192 unsigned long end) 193{ 194 unsigned long flags; 195 196 start = _ALIGN_DOWN(start, PAGE_SIZE); 197 end = _ALIGN_UP(end, PAGE_SIZE); 198 199 BUG_ON(!mm->pgd); 200 201 /* Note: Normally, we should only ever use a batch within a 202 * PTE locked section. This violates the rule, but will work 203 * since we don't actually modify the PTEs, we just flush the 204 * hash while leaving the PTEs intact (including their reference 205 * to being hashed). This is not the most performance oriented 206 * way to do things but is fine for our needs here. 207 */ 208 local_irq_save(flags); 209 arch_enter_lazy_mmu_mode(); 210 for (; start < end; start += PAGE_SIZE) { 211 pte_t *ptep = find_linux_pte(mm->pgd, start); 212 unsigned long pte; 213 214 if (ptep == NULL) 215 continue; 216 pte = pte_val(*ptep); 217 if (!(pte & _PAGE_HASHPTE)) 218 continue; 219 hpte_need_flush(mm, start, ptep, pte, 0); 220 } 221 arch_leave_lazy_mmu_mode(); 222 local_irq_restore(flags); 223} 224 225#endif /* CONFIG_HOTPLUG */ 226