1/* 2 * PowerPC version 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Derived from "arch/m68k/kernel/ptrace.c" 6 * Copyright (C) 1994 by Hamish Macdonald 7 * Taken from linux/kernel/ptrace.c and modified for M680x0. 8 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds 9 * 10 * Modified by Cort Dougan (cort@hq.fsmlabs.com) 11 * and Paul Mackerras (paulus@samba.org). 12 * 13 * This file is subject to the terms and conditions of the GNU General 14 * Public License. See the file README.legal in the main directory of 15 * this archive for more details. 16 */ 17 18#include <linux/kernel.h> 19#include <linux/sched.h> 20#include <linux/mm.h> 21#include <linux/smp.h> 22#include <linux/errno.h> 23#include <linux/ptrace.h> 24#include <linux/regset.h> 25#include <linux/tracehook.h> 26#include <linux/elf.h> 27#include <linux/user.h> 28#include <linux/security.h> 29#include <linux/signal.h> 30#include <linux/seccomp.h> 31#include <linux/audit.h> 32#ifdef CONFIG_PPC32 33#include <linux/module.h> 34#endif 35#include <linux/hw_breakpoint.h> 36#include <linux/perf_event.h> 37 38#include <asm/uaccess.h> 39#include <asm/page.h> 40#include <asm/pgtable.h> 41#include <asm/system.h> 42 43/* 44 * The parameter save area on the stack is used to store arguments being passed 45 * to callee function and is located at fixed offset from stack pointer. 46 */ 47#ifdef CONFIG_PPC32 48#define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */ 49#else /* CONFIG_PPC32 */ 50#define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */ 51#endif 52 53struct pt_regs_offset { 54 const char *name; 55 int offset; 56}; 57 58#define STR(s) #s /* convert to string */ 59#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} 60#define GPR_OFFSET_NAME(num) \ 61 {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])} 62#define REG_OFFSET_END {.name = NULL, .offset = 0} 63 64static const struct pt_regs_offset regoffset_table[] = { 65 GPR_OFFSET_NAME(0), 66 GPR_OFFSET_NAME(1), 67 GPR_OFFSET_NAME(2), 68 GPR_OFFSET_NAME(3), 69 GPR_OFFSET_NAME(4), 70 GPR_OFFSET_NAME(5), 71 GPR_OFFSET_NAME(6), 72 GPR_OFFSET_NAME(7), 73 GPR_OFFSET_NAME(8), 74 GPR_OFFSET_NAME(9), 75 GPR_OFFSET_NAME(10), 76 GPR_OFFSET_NAME(11), 77 GPR_OFFSET_NAME(12), 78 GPR_OFFSET_NAME(13), 79 GPR_OFFSET_NAME(14), 80 GPR_OFFSET_NAME(15), 81 GPR_OFFSET_NAME(16), 82 GPR_OFFSET_NAME(17), 83 GPR_OFFSET_NAME(18), 84 GPR_OFFSET_NAME(19), 85 GPR_OFFSET_NAME(20), 86 GPR_OFFSET_NAME(21), 87 GPR_OFFSET_NAME(22), 88 GPR_OFFSET_NAME(23), 89 GPR_OFFSET_NAME(24), 90 GPR_OFFSET_NAME(25), 91 GPR_OFFSET_NAME(26), 92 GPR_OFFSET_NAME(27), 93 GPR_OFFSET_NAME(28), 94 GPR_OFFSET_NAME(29), 95 GPR_OFFSET_NAME(30), 96 GPR_OFFSET_NAME(31), 97 REG_OFFSET_NAME(nip), 98 REG_OFFSET_NAME(msr), 99 REG_OFFSET_NAME(ctr), 100 REG_OFFSET_NAME(link), 101 REG_OFFSET_NAME(xer), 102 REG_OFFSET_NAME(ccr), 103#ifdef CONFIG_PPC64 104 REG_OFFSET_NAME(softe), 105#else 106 REG_OFFSET_NAME(mq), 107#endif 108 REG_OFFSET_NAME(trap), 109 REG_OFFSET_NAME(dar), 110 REG_OFFSET_NAME(dsisr), 111 REG_OFFSET_END, 112}; 113 114/** 115 * regs_query_register_offset() - query register offset from its name 116 * @name: the name of a register 117 * 118 * regs_query_register_offset() returns the offset of a register in struct 119 * pt_regs from its name. If the name is invalid, this returns -EINVAL; 120 */ 121int regs_query_register_offset(const char *name) 122{ 123 const struct pt_regs_offset *roff; 124 for (roff = regoffset_table; roff->name != NULL; roff++) 125 if (!strcmp(roff->name, name)) 126 return roff->offset; 127 return -EINVAL; 128} 129 130/** 131 * regs_query_register_name() - query register name from its offset 132 * @offset: the offset of a register in struct pt_regs. 133 * 134 * regs_query_register_name() returns the name of a register from its 135 * offset in struct pt_regs. If the @offset is invalid, this returns NULL; 136 */ 137const char *regs_query_register_name(unsigned int offset) 138{ 139 const struct pt_regs_offset *roff; 140 for (roff = regoffset_table; roff->name != NULL; roff++) 141 if (roff->offset == offset) 142 return roff->name; 143 return NULL; 144} 145 146/* 147 * does not yet catch signals sent when the child dies. 148 * in exit.c or in signal.c. 149 */ 150 151/* 152 * Set of msr bits that gdb can change on behalf of a process. 153 */ 154#ifdef CONFIG_PPC_ADV_DEBUG_REGS 155#define MSR_DEBUGCHANGE 0 156#else 157#define MSR_DEBUGCHANGE (MSR_SE | MSR_BE) 158#endif 159 160/* 161 * Max register writeable via put_reg 162 */ 163#ifdef CONFIG_PPC32 164#define PT_MAX_PUT_REG PT_MQ 165#else 166#define PT_MAX_PUT_REG PT_CCR 167#endif 168 169static unsigned long get_user_msr(struct task_struct *task) 170{ 171 return task->thread.regs->msr | task->thread.fpexc_mode; 172} 173 174static int set_user_msr(struct task_struct *task, unsigned long msr) 175{ 176 task->thread.regs->msr &= ~MSR_DEBUGCHANGE; 177 task->thread.regs->msr |= msr & MSR_DEBUGCHANGE; 178 return 0; 179} 180 181/* 182 * We prevent mucking around with the reserved area of trap 183 * which are used internally by the kernel. 184 */ 185static int set_user_trap(struct task_struct *task, unsigned long trap) 186{ 187 task->thread.regs->trap = trap & 0xfff0; 188 return 0; 189} 190 191/* 192 * Get contents of register REGNO in task TASK. 193 */ 194unsigned long ptrace_get_reg(struct task_struct *task, int regno) 195{ 196 if (task->thread.regs == NULL) 197 return -EIO; 198 199 if (regno == PT_MSR) 200 return get_user_msr(task); 201 202 if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) 203 return ((unsigned long *)task->thread.regs)[regno]; 204 205 return -EIO; 206} 207 208/* 209 * Write contents of register REGNO in task TASK. 210 */ 211int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data) 212{ 213 if (task->thread.regs == NULL) 214 return -EIO; 215 216 if (regno == PT_MSR) 217 return set_user_msr(task, data); 218 if (regno == PT_TRAP) 219 return set_user_trap(task, data); 220 221 if (regno <= PT_MAX_PUT_REG) { 222 ((unsigned long *)task->thread.regs)[regno] = data; 223 return 0; 224 } 225 return -EIO; 226} 227 228static int gpr_get(struct task_struct *target, const struct user_regset *regset, 229 unsigned int pos, unsigned int count, 230 void *kbuf, void __user *ubuf) 231{ 232 int ret; 233 234 if (target->thread.regs == NULL) 235 return -EIO; 236 237 CHECK_FULL_REGS(target->thread.regs); 238 239 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, 240 target->thread.regs, 241 0, offsetof(struct pt_regs, msr)); 242 if (!ret) { 243 unsigned long msr = get_user_msr(target); 244 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr, 245 offsetof(struct pt_regs, msr), 246 offsetof(struct pt_regs, msr) + 247 sizeof(msr)); 248 } 249 250 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != 251 offsetof(struct pt_regs, msr) + sizeof(long)); 252 253 if (!ret) 254 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, 255 &target->thread.regs->orig_gpr3, 256 offsetof(struct pt_regs, orig_gpr3), 257 sizeof(struct pt_regs)); 258 if (!ret) 259 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, 260 sizeof(struct pt_regs), -1); 261 262 return ret; 263} 264 265static int gpr_set(struct task_struct *target, const struct user_regset *regset, 266 unsigned int pos, unsigned int count, 267 const void *kbuf, const void __user *ubuf) 268{ 269 unsigned long reg; 270 int ret; 271 272 if (target->thread.regs == NULL) 273 return -EIO; 274 275 CHECK_FULL_REGS(target->thread.regs); 276 277 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 278 target->thread.regs, 279 0, PT_MSR * sizeof(reg)); 280 281 if (!ret && count > 0) { 282 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, 283 PT_MSR * sizeof(reg), 284 (PT_MSR + 1) * sizeof(reg)); 285 if (!ret) 286 ret = set_user_msr(target, reg); 287 } 288 289 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != 290 offsetof(struct pt_regs, msr) + sizeof(long)); 291 292 if (!ret) 293 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 294 &target->thread.regs->orig_gpr3, 295 PT_ORIG_R3 * sizeof(reg), 296 (PT_MAX_PUT_REG + 1) * sizeof(reg)); 297 298 if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret) 299 ret = user_regset_copyin_ignore( 300 &pos, &count, &kbuf, &ubuf, 301 (PT_MAX_PUT_REG + 1) * sizeof(reg), 302 PT_TRAP * sizeof(reg)); 303 304 if (!ret && count > 0) { 305 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, 306 PT_TRAP * sizeof(reg), 307 (PT_TRAP + 1) * sizeof(reg)); 308 if (!ret) 309 ret = set_user_trap(target, reg); 310 } 311 312 if (!ret) 313 ret = user_regset_copyin_ignore( 314 &pos, &count, &kbuf, &ubuf, 315 (PT_TRAP + 1) * sizeof(reg), -1); 316 317 return ret; 318} 319 320static int fpr_get(struct task_struct *target, const struct user_regset *regset, 321 unsigned int pos, unsigned int count, 322 void *kbuf, void __user *ubuf) 323{ 324#ifdef CONFIG_VSX 325 double buf[33]; 326 int i; 327#endif 328 flush_fp_to_thread(target); 329 330#ifdef CONFIG_VSX 331 /* copy to local buffer then write that out */ 332 for (i = 0; i < 32 ; i++) 333 buf[i] = target->thread.TS_FPR(i); 334 memcpy(&buf[32], &target->thread.fpscr, sizeof(double)); 335 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); 336 337#else 338 BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) != 339 offsetof(struct thread_struct, TS_FPR(32))); 340 341 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, 342 &target->thread.fpr, 0, -1); 343#endif 344} 345 346static int fpr_set(struct task_struct *target, const struct user_regset *regset, 347 unsigned int pos, unsigned int count, 348 const void *kbuf, const void __user *ubuf) 349{ 350#ifdef CONFIG_VSX 351 double buf[33]; 352 int i; 353#endif 354 flush_fp_to_thread(target); 355 356#ifdef CONFIG_VSX 357 /* copy to local buffer then write that out */ 358 i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); 359 if (i) 360 return i; 361 for (i = 0; i < 32 ; i++) 362 target->thread.TS_FPR(i) = buf[i]; 363 memcpy(&target->thread.fpscr, &buf[32], sizeof(double)); 364 return 0; 365#else 366 BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) != 367 offsetof(struct thread_struct, TS_FPR(32))); 368 369 return user_regset_copyin(&pos, &count, &kbuf, &ubuf, 370 &target->thread.fpr, 0, -1); 371#endif 372} 373 374#ifdef CONFIG_ALTIVEC 375/* 376 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. 377 * The transfer totals 34 quadword. Quadwords 0-31 contain the 378 * corresponding vector registers. Quadword 32 contains the vscr as the 379 * last word (offset 12) within that quadword. Quadword 33 contains the 380 * vrsave as the first word (offset 0) within the quadword. 381 * 382 * This definition of the VMX state is compatible with the current PPC32 383 * ptrace interface. This allows signal handling and ptrace to use the 384 * same structures. This also simplifies the implementation of a bi-arch 385 * (combined (32- and 64-bit) gdb. 386 */ 387 388static int vr_active(struct task_struct *target, 389 const struct user_regset *regset) 390{ 391 flush_altivec_to_thread(target); 392 return target->thread.used_vr ? regset->n : 0; 393} 394 395static int vr_get(struct task_struct *target, const struct user_regset *regset, 396 unsigned int pos, unsigned int count, 397 void *kbuf, void __user *ubuf) 398{ 399 int ret; 400 401 flush_altivec_to_thread(target); 402 403 BUILD_BUG_ON(offsetof(struct thread_struct, vscr) != 404 offsetof(struct thread_struct, vr[32])); 405 406 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, 407 &target->thread.vr, 0, 408 33 * sizeof(vector128)); 409 if (!ret) { 410 /* 411 * Copy out only the low-order word of vrsave. 412 */ 413 union { 414 elf_vrreg_t reg; 415 u32 word; 416 } vrsave; 417 memset(&vrsave, 0, sizeof(vrsave)); 418 vrsave.word = target->thread.vrsave; 419 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave, 420 33 * sizeof(vector128), -1); 421 } 422 423 return ret; 424} 425 426static int vr_set(struct task_struct *target, const struct user_regset *regset, 427 unsigned int pos, unsigned int count, 428 const void *kbuf, const void __user *ubuf) 429{ 430 int ret; 431 432 flush_altivec_to_thread(target); 433 434 BUILD_BUG_ON(offsetof(struct thread_struct, vscr) != 435 offsetof(struct thread_struct, vr[32])); 436 437 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 438 &target->thread.vr, 0, 33 * sizeof(vector128)); 439 if (!ret && count > 0) { 440 /* 441 * We use only the first word of vrsave. 442 */ 443 union { 444 elf_vrreg_t reg; 445 u32 word; 446 } vrsave; 447 memset(&vrsave, 0, sizeof(vrsave)); 448 vrsave.word = target->thread.vrsave; 449 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave, 450 33 * sizeof(vector128), -1); 451 if (!ret) 452 target->thread.vrsave = vrsave.word; 453 } 454 455 return ret; 456} 457#endif /* CONFIG_ALTIVEC */ 458 459#ifdef CONFIG_VSX 460/* 461 * Currently to set and and get all the vsx state, you need to call 462 * the fp and VMX calls aswell. This only get/sets the lower 32 463 * 128bit VSX registers. 464 */ 465 466static int vsr_active(struct task_struct *target, 467 const struct user_regset *regset) 468{ 469 flush_vsx_to_thread(target); 470 return target->thread.used_vsr ? regset->n : 0; 471} 472 473static int vsr_get(struct task_struct *target, const struct user_regset *regset, 474 unsigned int pos, unsigned int count, 475 void *kbuf, void __user *ubuf) 476{ 477 double buf[32]; 478 int ret, i; 479 480 flush_vsx_to_thread(target); 481 482 for (i = 0; i < 32 ; i++) 483 buf[i] = target->thread.fpr[i][TS_VSRLOWOFFSET]; 484 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, 485 buf, 0, 32 * sizeof(double)); 486 487 return ret; 488} 489 490static int vsr_set(struct task_struct *target, const struct user_regset *regset, 491 unsigned int pos, unsigned int count, 492 const void *kbuf, const void __user *ubuf) 493{ 494 double buf[32]; 495 int ret,i; 496 497 flush_vsx_to_thread(target); 498 499 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 500 buf, 0, 32 * sizeof(double)); 501 for (i = 0; i < 32 ; i++) 502 target->thread.fpr[i][TS_VSRLOWOFFSET] = buf[i]; 503 504 505 return ret; 506} 507#endif /* CONFIG_VSX */ 508 509#ifdef CONFIG_SPE 510 511/* 512 * For get_evrregs/set_evrregs functions 'data' has the following layout: 513 * 514 * struct { 515 * u32 evr[32]; 516 * u64 acc; 517 * u32 spefscr; 518 * } 519 */ 520 521static int evr_active(struct task_struct *target, 522 const struct user_regset *regset) 523{ 524 flush_spe_to_thread(target); 525 return target->thread.used_spe ? regset->n : 0; 526} 527 528static int evr_get(struct task_struct *target, const struct user_regset *regset, 529 unsigned int pos, unsigned int count, 530 void *kbuf, void __user *ubuf) 531{ 532 int ret; 533 534 flush_spe_to_thread(target); 535 536 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, 537 &target->thread.evr, 538 0, sizeof(target->thread.evr)); 539 540 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != 541 offsetof(struct thread_struct, spefscr)); 542 543 if (!ret) 544 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, 545 &target->thread.acc, 546 sizeof(target->thread.evr), -1); 547 548 return ret; 549} 550 551static int evr_set(struct task_struct *target, const struct user_regset *regset, 552 unsigned int pos, unsigned int count, 553 const void *kbuf, const void __user *ubuf) 554{ 555 int ret; 556 557 flush_spe_to_thread(target); 558 559 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 560 &target->thread.evr, 561 0, sizeof(target->thread.evr)); 562 563 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != 564 offsetof(struct thread_struct, spefscr)); 565 566 if (!ret) 567 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, 568 &target->thread.acc, 569 sizeof(target->thread.evr), -1); 570 571 return ret; 572} 573#endif /* CONFIG_SPE */ 574 575 576/* 577 * These are our native regset flavors. 578 */ 579enum powerpc_regset { 580 REGSET_GPR, 581 REGSET_FPR, 582#ifdef CONFIG_ALTIVEC 583 REGSET_VMX, 584#endif 585#ifdef CONFIG_VSX 586 REGSET_VSX, 587#endif 588#ifdef CONFIG_SPE 589 REGSET_SPE, 590#endif 591}; 592 593static const struct user_regset native_regsets[] = { 594 [REGSET_GPR] = { 595 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, 596 .size = sizeof(long), .align = sizeof(long), 597 .get = gpr_get, .set = gpr_set 598 }, 599 [REGSET_FPR] = { 600 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, 601 .size = sizeof(double), .align = sizeof(double), 602 .get = fpr_get, .set = fpr_set 603 }, 604#ifdef CONFIG_ALTIVEC 605 [REGSET_VMX] = { 606 .core_note_type = NT_PPC_VMX, .n = 34, 607 .size = sizeof(vector128), .align = sizeof(vector128), 608 .active = vr_active, .get = vr_get, .set = vr_set 609 }, 610#endif 611#ifdef CONFIG_VSX 612 [REGSET_VSX] = { 613 .core_note_type = NT_PPC_VSX, .n = 32, 614 .size = sizeof(double), .align = sizeof(double), 615 .active = vsr_active, .get = vsr_get, .set = vsr_set 616 }, 617#endif 618#ifdef CONFIG_SPE 619 [REGSET_SPE] = { 620 .n = 35, 621 .size = sizeof(u32), .align = sizeof(u32), 622 .active = evr_active, .get = evr_get, .set = evr_set 623 }, 624#endif 625}; 626 627static const struct user_regset_view user_ppc_native_view = { 628 .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI, 629 .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets) 630}; 631 632#ifdef CONFIG_PPC64 633#include <linux/compat.h> 634 635static int gpr32_get(struct task_struct *target, 636 const struct user_regset *regset, 637 unsigned int pos, unsigned int count, 638 void *kbuf, void __user *ubuf) 639{ 640 const unsigned long *regs = &target->thread.regs->gpr[0]; 641 compat_ulong_t *k = kbuf; 642 compat_ulong_t __user *u = ubuf; 643 compat_ulong_t reg; 644 645 if (target->thread.regs == NULL) 646 return -EIO; 647 648 CHECK_FULL_REGS(target->thread.regs); 649 650 pos /= sizeof(reg); 651 count /= sizeof(reg); 652 653 if (kbuf) 654 for (; count > 0 && pos < PT_MSR; --count) 655 *k++ = regs[pos++]; 656 else 657 for (; count > 0 && pos < PT_MSR; --count) 658 if (__put_user((compat_ulong_t) regs[pos++], u++)) 659 return -EFAULT; 660 661 if (count > 0 && pos == PT_MSR) { 662 reg = get_user_msr(target); 663 if (kbuf) 664 *k++ = reg; 665 else if (__put_user(reg, u++)) 666 return -EFAULT; 667 ++pos; 668 --count; 669 } 670 671 if (kbuf) 672 for (; count > 0 && pos < PT_REGS_COUNT; --count) 673 *k++ = regs[pos++]; 674 else 675 for (; count > 0 && pos < PT_REGS_COUNT; --count) 676 if (__put_user((compat_ulong_t) regs[pos++], u++)) 677 return -EFAULT; 678 679 kbuf = k; 680 ubuf = u; 681 pos *= sizeof(reg); 682 count *= sizeof(reg); 683 return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, 684 PT_REGS_COUNT * sizeof(reg), -1); 685} 686 687static int gpr32_set(struct task_struct *target, 688 const struct user_regset *regset, 689 unsigned int pos, unsigned int count, 690 const void *kbuf, const void __user *ubuf) 691{ 692 unsigned long *regs = &target->thread.regs->gpr[0]; 693 const compat_ulong_t *k = kbuf; 694 const compat_ulong_t __user *u = ubuf; 695 compat_ulong_t reg; 696 697 if (target->thread.regs == NULL) 698 return -EIO; 699 700 CHECK_FULL_REGS(target->thread.regs); 701 702 pos /= sizeof(reg); 703 count /= sizeof(reg); 704 705 if (kbuf) 706 for (; count > 0 && pos < PT_MSR; --count) 707 regs[pos++] = *k++; 708 else 709 for (; count > 0 && pos < PT_MSR; --count) { 710 if (__get_user(reg, u++)) 711 return -EFAULT; 712 regs[pos++] = reg; 713 } 714 715 716 if (count > 0 && pos == PT_MSR) { 717 if (kbuf) 718 reg = *k++; 719 else if (__get_user(reg, u++)) 720 return -EFAULT; 721 set_user_msr(target, reg); 722 ++pos; 723 --count; 724 } 725 726 if (kbuf) { 727 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) 728 regs[pos++] = *k++; 729 for (; count > 0 && pos < PT_TRAP; --count, ++pos) 730 ++k; 731 } else { 732 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) { 733 if (__get_user(reg, u++)) 734 return -EFAULT; 735 regs[pos++] = reg; 736 } 737 for (; count > 0 && pos < PT_TRAP; --count, ++pos) 738 if (__get_user(reg, u++)) 739 return -EFAULT; 740 } 741 742 if (count > 0 && pos == PT_TRAP) { 743 if (kbuf) 744 reg = *k++; 745 else if (__get_user(reg, u++)) 746 return -EFAULT; 747 set_user_trap(target, reg); 748 ++pos; 749 --count; 750 } 751 752 kbuf = k; 753 ubuf = u; 754 pos *= sizeof(reg); 755 count *= sizeof(reg); 756 return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, 757 (PT_TRAP + 1) * sizeof(reg), -1); 758} 759 760/* 761 * These are the regset flavors matching the CONFIG_PPC32 native set. 762 */ 763static const struct user_regset compat_regsets[] = { 764 [REGSET_GPR] = { 765 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, 766 .size = sizeof(compat_long_t), .align = sizeof(compat_long_t), 767 .get = gpr32_get, .set = gpr32_set 768 }, 769 [REGSET_FPR] = { 770 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, 771 .size = sizeof(double), .align = sizeof(double), 772 .get = fpr_get, .set = fpr_set 773 }, 774#ifdef CONFIG_ALTIVEC 775 [REGSET_VMX] = { 776 .core_note_type = NT_PPC_VMX, .n = 34, 777 .size = sizeof(vector128), .align = sizeof(vector128), 778 .active = vr_active, .get = vr_get, .set = vr_set 779 }, 780#endif 781#ifdef CONFIG_SPE 782 [REGSET_SPE] = { 783 .core_note_type = NT_PPC_SPE, .n = 35, 784 .size = sizeof(u32), .align = sizeof(u32), 785 .active = evr_active, .get = evr_get, .set = evr_set 786 }, 787#endif 788}; 789 790static const struct user_regset_view user_ppc_compat_view = { 791 .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI, 792 .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets) 793}; 794#endif /* CONFIG_PPC64 */ 795 796const struct user_regset_view *task_user_regset_view(struct task_struct *task) 797{ 798#ifdef CONFIG_PPC64 799 if (test_tsk_thread_flag(task, TIF_32BIT)) 800 return &user_ppc_compat_view; 801#endif 802 return &user_ppc_native_view; 803} 804 805 806void user_enable_single_step(struct task_struct *task) 807{ 808 struct pt_regs *regs = task->thread.regs; 809 810 if (regs != NULL) { 811#ifdef CONFIG_PPC_ADV_DEBUG_REGS 812 task->thread.dbcr0 &= ~DBCR0_BT; 813 task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; 814 regs->msr |= MSR_DE; 815#else 816 regs->msr &= ~MSR_BE; 817 regs->msr |= MSR_SE; 818#endif 819 } 820 set_tsk_thread_flag(task, TIF_SINGLESTEP); 821} 822 823void user_enable_block_step(struct task_struct *task) 824{ 825 struct pt_regs *regs = task->thread.regs; 826 827 if (regs != NULL) { 828#ifdef CONFIG_PPC_ADV_DEBUG_REGS 829 task->thread.dbcr0 &= ~DBCR0_IC; 830 task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT; 831 regs->msr |= MSR_DE; 832#else 833 regs->msr &= ~MSR_SE; 834 regs->msr |= MSR_BE; 835#endif 836 } 837 set_tsk_thread_flag(task, TIF_SINGLESTEP); 838} 839 840void user_disable_single_step(struct task_struct *task) 841{ 842 struct pt_regs *regs = task->thread.regs; 843 844 if (regs != NULL) { 845#ifdef CONFIG_PPC_ADV_DEBUG_REGS 846 /* 847 * The logic to disable single stepping should be as 848 * simple as turning off the Instruction Complete flag. 849 * And, after doing so, if all debug flags are off, turn 850 * off DBCR0(IDM) and MSR(DE) .... Torez 851 */ 852 task->thread.dbcr0 &= ~DBCR0_IC; 853 /* 854 * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set. 855 */ 856 if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0, 857 task->thread.dbcr1)) { 858 /* 859 * All debug events were off..... 860 */ 861 task->thread.dbcr0 &= ~DBCR0_IDM; 862 regs->msr &= ~MSR_DE; 863 } 864#else 865 regs->msr &= ~(MSR_SE | MSR_BE); 866#endif 867 } 868 clear_tsk_thread_flag(task, TIF_SINGLESTEP); 869} 870 871#ifdef CONFIG_HAVE_HW_BREAKPOINT 872void ptrace_triggered(struct perf_event *bp, int nmi, 873 struct perf_sample_data *data, struct pt_regs *regs) 874{ 875 struct perf_event_attr attr; 876 877 /* 878 * Disable the breakpoint request here since ptrace has defined a 879 * one-shot behaviour for breakpoint exceptions in PPC64. 880 * The SIGTRAP signal is generated automatically for us in do_dabr(). 881 * We don't have to do anything about that here 882 */ 883 attr = bp->attr; 884 attr.disabled = true; 885 modify_user_hw_breakpoint(bp, &attr); 886} 887#endif /* CONFIG_HAVE_HW_BREAKPOINT */ 888 889int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, 890 unsigned long data) 891{ 892#ifdef CONFIG_HAVE_HW_BREAKPOINT 893 int ret; 894 struct thread_struct *thread = &(task->thread); 895 struct perf_event *bp; 896 struct perf_event_attr attr; 897#endif /* CONFIG_HAVE_HW_BREAKPOINT */ 898 899 /* For ppc64 we support one DABR and no IABR's at the moment (ppc64). 900 * For embedded processors we support one DAC and no IAC's at the 901 * moment. 902 */ 903 if (addr > 0) 904 return -EINVAL; 905 906 /* The bottom 3 bits in dabr are flags */ 907 if ((data & ~0x7UL) >= TASK_SIZE) 908 return -EIO; 909 910#ifndef CONFIG_PPC_ADV_DEBUG_REGS 911 /* For processors using DABR (i.e. 970), the bottom 3 bits are flags. 912 * It was assumed, on previous implementations, that 3 bits were 913 * passed together with the data address, fitting the design of the 914 * DABR register, as follows: 915 * 916 * bit 0: Read flag 917 * bit 1: Write flag 918 * bit 2: Breakpoint translation 919 * 920 * Thus, we use them here as so. 921 */ 922 923 /* Ensure breakpoint translation bit is set */ 924 if (data && !(data & DABR_TRANSLATION)) 925 return -EIO; 926#ifdef CONFIG_HAVE_HW_BREAKPOINT 927 bp = thread->ptrace_bps[0]; 928 if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) { 929 if (bp) { 930 unregister_hw_breakpoint(bp); 931 thread->ptrace_bps[0] = NULL; 932 } 933 return 0; 934 } 935 if (bp) { 936 attr = bp->attr; 937 attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN; 938 arch_bp_generic_fields(data & 939 (DABR_DATA_WRITE | DABR_DATA_READ), 940 &attr.bp_type); 941 ret = modify_user_hw_breakpoint(bp, &attr); 942 if (ret) 943 return ret; 944 thread->ptrace_bps[0] = bp; 945 thread->dabr = data; 946 return 0; 947 } 948 949 /* Create a new breakpoint request if one doesn't exist already */ 950 hw_breakpoint_init(&attr); 951 attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN; 952 arch_bp_generic_fields(data & (DABR_DATA_WRITE | DABR_DATA_READ), 953 &attr.bp_type); 954 955 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr, 956 ptrace_triggered, task); 957 if (IS_ERR(bp)) { 958 thread->ptrace_bps[0] = NULL; 959 return PTR_ERR(bp); 960 } 961 962#endif /* CONFIG_HAVE_HW_BREAKPOINT */ 963 964 /* Move contents to the DABR register */ 965 task->thread.dabr = data; 966#else /* CONFIG_PPC_ADV_DEBUG_REGS */ 967 /* As described above, it was assumed 3 bits were passed with the data 968 * address, but we will assume only the mode bits will be passed 969 * as to not cause alignment restrictions for DAC-based processors. 970 */ 971 972 /* DAC's hold the whole address without any mode flags */ 973 task->thread.dac1 = data & ~0x3UL; 974 975 if (task->thread.dac1 == 0) { 976 dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W); 977 if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0, 978 task->thread.dbcr1)) { 979 task->thread.regs->msr &= ~MSR_DE; 980 task->thread.dbcr0 &= ~DBCR0_IDM; 981 } 982 return 0; 983 } 984 985 /* Read or Write bits must be set */ 986 987 if (!(data & 0x3UL)) 988 return -EINVAL; 989 990 /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0 991 register */ 992 task->thread.dbcr0 |= DBCR0_IDM; 993 994 /* Check for write and read flags and set DBCR0 995 accordingly */ 996 dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W); 997 if (data & 0x1UL) 998 dbcr_dac(task) |= DBCR_DAC1R; 999 if (data & 0x2UL) 1000 dbcr_dac(task) |= DBCR_DAC1W; 1001 task->thread.regs->msr |= MSR_DE; 1002#endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 1003 return 0; 1004} 1005 1006/* 1007 * Called by kernel/ptrace.c when detaching.. 1008 * 1009 * Make sure single step bits etc are not set. 1010 */ 1011void ptrace_disable(struct task_struct *child) 1012{ 1013 /* make sure the single step bit is not set. */ 1014 user_disable_single_step(child); 1015} 1016 1017#ifdef CONFIG_PPC_ADV_DEBUG_REGS 1018static long set_intruction_bp(struct task_struct *child, 1019 struct ppc_hw_breakpoint *bp_info) 1020{ 1021 int slot; 1022 int slot1_in_use = ((child->thread.dbcr0 & DBCR0_IAC1) != 0); 1023 int slot2_in_use = ((child->thread.dbcr0 & DBCR0_IAC2) != 0); 1024 int slot3_in_use = ((child->thread.dbcr0 & DBCR0_IAC3) != 0); 1025 int slot4_in_use = ((child->thread.dbcr0 & DBCR0_IAC4) != 0); 1026 1027 if (dbcr_iac_range(child) & DBCR_IAC12MODE) 1028 slot2_in_use = 1; 1029 if (dbcr_iac_range(child) & DBCR_IAC34MODE) 1030 slot4_in_use = 1; 1031 1032 if (bp_info->addr >= TASK_SIZE) 1033 return -EIO; 1034 1035 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) { 1036 1037 /* Make sure range is valid. */ 1038 if (bp_info->addr2 >= TASK_SIZE) 1039 return -EIO; 1040 1041 /* We need a pair of IAC regsisters */ 1042 if ((!slot1_in_use) && (!slot2_in_use)) { 1043 slot = 1; 1044 child->thread.iac1 = bp_info->addr; 1045 child->thread.iac2 = bp_info->addr2; 1046 child->thread.dbcr0 |= DBCR0_IAC1; 1047 if (bp_info->addr_mode == 1048 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) 1049 dbcr_iac_range(child) |= DBCR_IAC12X; 1050 else 1051 dbcr_iac_range(child) |= DBCR_IAC12I; 1052#if CONFIG_PPC_ADV_DEBUG_IACS > 2 1053 } else if ((!slot3_in_use) && (!slot4_in_use)) { 1054 slot = 3; 1055 child->thread.iac3 = bp_info->addr; 1056 child->thread.iac4 = bp_info->addr2; 1057 child->thread.dbcr0 |= DBCR0_IAC3; 1058 if (bp_info->addr_mode == 1059 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) 1060 dbcr_iac_range(child) |= DBCR_IAC34X; 1061 else 1062 dbcr_iac_range(child) |= DBCR_IAC34I; 1063#endif 1064 } else 1065 return -ENOSPC; 1066 } else { 1067 /* We only need one. If possible leave a pair free in 1068 * case a range is needed later 1069 */ 1070 if (!slot1_in_use) { 1071 /* 1072 * Don't use iac1 if iac1-iac2 are free and either 1073 * iac3 or iac4 (but not both) are free 1074 */ 1075 if (slot2_in_use || (slot3_in_use == slot4_in_use)) { 1076 slot = 1; 1077 child->thread.iac1 = bp_info->addr; 1078 child->thread.dbcr0 |= DBCR0_IAC1; 1079 goto out; 1080 } 1081 } 1082 if (!slot2_in_use) { 1083 slot = 2; 1084 child->thread.iac2 = bp_info->addr; 1085 child->thread.dbcr0 |= DBCR0_IAC2; 1086#if CONFIG_PPC_ADV_DEBUG_IACS > 2 1087 } else if (!slot3_in_use) { 1088 slot = 3; 1089 child->thread.iac3 = bp_info->addr; 1090 child->thread.dbcr0 |= DBCR0_IAC3; 1091 } else if (!slot4_in_use) { 1092 slot = 4; 1093 child->thread.iac4 = bp_info->addr; 1094 child->thread.dbcr0 |= DBCR0_IAC4; 1095#endif 1096 } else 1097 return -ENOSPC; 1098 } 1099out: 1100 child->thread.dbcr0 |= DBCR0_IDM; 1101 child->thread.regs->msr |= MSR_DE; 1102 1103 return slot; 1104} 1105 1106static int del_instruction_bp(struct task_struct *child, int slot) 1107{ 1108 switch (slot) { 1109 case 1: 1110 if ((child->thread.dbcr0 & DBCR0_IAC1) == 0) 1111 return -ENOENT; 1112 1113 if (dbcr_iac_range(child) & DBCR_IAC12MODE) { 1114 /* address range - clear slots 1 & 2 */ 1115 child->thread.iac2 = 0; 1116 dbcr_iac_range(child) &= ~DBCR_IAC12MODE; 1117 } 1118 child->thread.iac1 = 0; 1119 child->thread.dbcr0 &= ~DBCR0_IAC1; 1120 break; 1121 case 2: 1122 if ((child->thread.dbcr0 & DBCR0_IAC2) == 0) 1123 return -ENOENT; 1124 1125 if (dbcr_iac_range(child) & DBCR_IAC12MODE) 1126 /* used in a range */ 1127 return -EINVAL; 1128 child->thread.iac2 = 0; 1129 child->thread.dbcr0 &= ~DBCR0_IAC2; 1130 break; 1131#if CONFIG_PPC_ADV_DEBUG_IACS > 2 1132 case 3: 1133 if ((child->thread.dbcr0 & DBCR0_IAC3) == 0) 1134 return -ENOENT; 1135 1136 if (dbcr_iac_range(child) & DBCR_IAC34MODE) { 1137 /* address range - clear slots 3 & 4 */ 1138 child->thread.iac4 = 0; 1139 dbcr_iac_range(child) &= ~DBCR_IAC34MODE; 1140 } 1141 child->thread.iac3 = 0; 1142 child->thread.dbcr0 &= ~DBCR0_IAC3; 1143 break; 1144 case 4: 1145 if ((child->thread.dbcr0 & DBCR0_IAC4) == 0) 1146 return -ENOENT; 1147 1148 if (dbcr_iac_range(child) & DBCR_IAC34MODE) 1149 /* Used in a range */ 1150 return -EINVAL; 1151 child->thread.iac4 = 0; 1152 child->thread.dbcr0 &= ~DBCR0_IAC4; 1153 break; 1154#endif 1155 default: 1156 return -EINVAL; 1157 } 1158 return 0; 1159} 1160 1161static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) 1162{ 1163 int byte_enable = 1164 (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT) 1165 & 0xf; 1166 int condition_mode = 1167 bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE; 1168 int slot; 1169 1170 if (byte_enable && (condition_mode == 0)) 1171 return -EINVAL; 1172 1173 if (bp_info->addr >= TASK_SIZE) 1174 return -EIO; 1175 1176 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) { 1177 slot = 1; 1178 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) 1179 dbcr_dac(child) |= DBCR_DAC1R; 1180 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) 1181 dbcr_dac(child) |= DBCR_DAC1W; 1182 child->thread.dac1 = (unsigned long)bp_info->addr; 1183#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 1184 if (byte_enable) { 1185 child->thread.dvc1 = 1186 (unsigned long)bp_info->condition_value; 1187 child->thread.dbcr2 |= 1188 ((byte_enable << DBCR2_DVC1BE_SHIFT) | 1189 (condition_mode << DBCR2_DVC1M_SHIFT)); 1190 } 1191#endif 1192#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1193 } else if (child->thread.dbcr2 & DBCR2_DAC12MODE) { 1194 /* Both dac1 and dac2 are part of a range */ 1195 return -ENOSPC; 1196#endif 1197 } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) { 1198 slot = 2; 1199 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) 1200 dbcr_dac(child) |= DBCR_DAC2R; 1201 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) 1202 dbcr_dac(child) |= DBCR_DAC2W; 1203 child->thread.dac2 = (unsigned long)bp_info->addr; 1204#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 1205 if (byte_enable) { 1206 child->thread.dvc2 = 1207 (unsigned long)bp_info->condition_value; 1208 child->thread.dbcr2 |= 1209 ((byte_enable << DBCR2_DVC2BE_SHIFT) | 1210 (condition_mode << DBCR2_DVC2M_SHIFT)); 1211 } 1212#endif 1213 } else 1214 return -ENOSPC; 1215 child->thread.dbcr0 |= DBCR0_IDM; 1216 child->thread.regs->msr |= MSR_DE; 1217 1218 return slot + 4; 1219} 1220 1221static int del_dac(struct task_struct *child, int slot) 1222{ 1223 if (slot == 1) { 1224 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) 1225 return -ENOENT; 1226 1227 child->thread.dac1 = 0; 1228 dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1229#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1230 if (child->thread.dbcr2 & DBCR2_DAC12MODE) { 1231 child->thread.dac2 = 0; 1232 child->thread.dbcr2 &= ~DBCR2_DAC12MODE; 1233 } 1234 child->thread.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE); 1235#endif 1236#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 1237 child->thread.dvc1 = 0; 1238#endif 1239 } else if (slot == 2) { 1240 if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) 1241 return -ENOENT; 1242 1243#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1244 if (child->thread.dbcr2 & DBCR2_DAC12MODE) 1245 /* Part of a range */ 1246 return -EINVAL; 1247 child->thread.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE); 1248#endif 1249#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 1250 child->thread.dvc2 = 0; 1251#endif 1252 child->thread.dac2 = 0; 1253 dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1254 } else 1255 return -EINVAL; 1256 1257 return 0; 1258} 1259#endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 1260 1261#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1262static int set_dac_range(struct task_struct *child, 1263 struct ppc_hw_breakpoint *bp_info) 1264{ 1265 int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK; 1266 1267 /* We don't allow range watchpoints to be used with DVC */ 1268 if (bp_info->condition_mode) 1269 return -EINVAL; 1270 1271 /* 1272 * Best effort to verify the address range. The user/supervisor bits 1273 * prevent trapping in kernel space, but let's fail on an obvious bad 1274 * range. The simple test on the mask is not fool-proof, and any 1275 * exclusive range will spill over into kernel space. 1276 */ 1277 if (bp_info->addr >= TASK_SIZE) 1278 return -EIO; 1279 if (mode == PPC_BREAKPOINT_MODE_MASK) { 1280 /* 1281 * dac2 is a bitmask. Don't allow a mask that makes a 1282 * kernel space address from a valid dac1 value 1283 */ 1284 if (~((unsigned long)bp_info->addr2) >= TASK_SIZE) 1285 return -EIO; 1286 } else { 1287 /* 1288 * For range breakpoints, addr2 must also be a valid address 1289 */ 1290 if (bp_info->addr2 >= TASK_SIZE) 1291 return -EIO; 1292 } 1293 1294 if (child->thread.dbcr0 & 1295 (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)) 1296 return -ENOSPC; 1297 1298 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) 1299 child->thread.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM); 1300 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) 1301 child->thread.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM); 1302 child->thread.dac1 = bp_info->addr; 1303 child->thread.dac2 = bp_info->addr2; 1304 if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) 1305 child->thread.dbcr2 |= DBCR2_DAC12M; 1306 else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) 1307 child->thread.dbcr2 |= DBCR2_DAC12MX; 1308 else /* PPC_BREAKPOINT_MODE_MASK */ 1309 child->thread.dbcr2 |= DBCR2_DAC12MM; 1310 child->thread.regs->msr |= MSR_DE; 1311 1312 return 5; 1313} 1314#endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */ 1315 1316static long ppc_set_hwdebug(struct task_struct *child, 1317 struct ppc_hw_breakpoint *bp_info) 1318{ 1319 if (bp_info->version != 1) 1320 return -ENOTSUPP; 1321#ifdef CONFIG_PPC_ADV_DEBUG_REGS 1322 /* 1323 * Check for invalid flags and combinations 1324 */ 1325 if ((bp_info->trigger_type == 0) || 1326 (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE | 1327 PPC_BREAKPOINT_TRIGGER_RW)) || 1328 (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) || 1329 (bp_info->condition_mode & 1330 ~(PPC_BREAKPOINT_CONDITION_MODE | 1331 PPC_BREAKPOINT_CONDITION_BE_ALL))) 1332 return -EINVAL; 1333#if CONFIG_PPC_ADV_DEBUG_DVCS == 0 1334 if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) 1335 return -EINVAL; 1336#endif 1337 1338 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) { 1339 if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) || 1340 (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)) 1341 return -EINVAL; 1342 return set_intruction_bp(child, bp_info); 1343 } 1344 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) 1345 return set_dac(child, bp_info); 1346 1347#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1348 return set_dac_range(child, bp_info); 1349#else 1350 return -EINVAL; 1351#endif 1352#else /* !CONFIG_PPC_ADV_DEBUG_DVCS */ 1353 /* 1354 * We only support one data breakpoint 1355 */ 1356 if (((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0) || 1357 ((bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0) || 1358 (bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_WRITE) || 1359 (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) || 1360 (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)) 1361 return -EINVAL; 1362 1363 if (child->thread.dabr) 1364 return -ENOSPC; 1365 1366 if ((unsigned long)bp_info->addr >= TASK_SIZE) 1367 return -EIO; 1368 1369 child->thread.dabr = (unsigned long)bp_info->addr; 1370 1371 return 1; 1372#endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */ 1373} 1374 1375static long ppc_del_hwdebug(struct task_struct *child, long addr, long data) 1376{ 1377#ifdef CONFIG_PPC_ADV_DEBUG_REGS 1378 int rc; 1379 1380 if (data <= 4) 1381 rc = del_instruction_bp(child, (int)data); 1382 else 1383 rc = del_dac(child, (int)data - 4); 1384 1385 if (!rc) { 1386 if (!DBCR_ACTIVE_EVENTS(child->thread.dbcr0, 1387 child->thread.dbcr1)) { 1388 child->thread.dbcr0 &= ~DBCR0_IDM; 1389 child->thread.regs->msr &= ~MSR_DE; 1390 } 1391 } 1392 return rc; 1393#else 1394 if (data != 1) 1395 return -EINVAL; 1396 if (child->thread.dabr == 0) 1397 return -ENOENT; 1398 1399 child->thread.dabr = 0; 1400 1401 return 0; 1402#endif 1403} 1404 1405/* 1406 * Here are the old "legacy" powerpc specific getregs/setregs ptrace calls, 1407 * we mark them as obsolete now, they will be removed in a future version 1408 */ 1409static long arch_ptrace_old(struct task_struct *child, long request, long addr, 1410 long data) 1411{ 1412 switch (request) { 1413 case PPC_PTRACE_GETREGS: /* Get GPRs 0 - 31. */ 1414 return copy_regset_to_user(child, &user_ppc_native_view, 1415 REGSET_GPR, 0, 32 * sizeof(long), 1416 (void __user *) data); 1417 1418 case PPC_PTRACE_SETREGS: /* Set GPRs 0 - 31. */ 1419 return copy_regset_from_user(child, &user_ppc_native_view, 1420 REGSET_GPR, 0, 32 * sizeof(long), 1421 (const void __user *) data); 1422 1423 case PPC_PTRACE_GETFPREGS: /* Get FPRs 0 - 31. */ 1424 return copy_regset_to_user(child, &user_ppc_native_view, 1425 REGSET_FPR, 0, 32 * sizeof(double), 1426 (void __user *) data); 1427 1428 case PPC_PTRACE_SETFPREGS: /* Set FPRs 0 - 31. */ 1429 return copy_regset_from_user(child, &user_ppc_native_view, 1430 REGSET_FPR, 0, 32 * sizeof(double), 1431 (const void __user *) data); 1432 } 1433 1434 return -EPERM; 1435} 1436 1437long arch_ptrace(struct task_struct *child, long request, long addr, long data) 1438{ 1439 int ret = -EPERM; 1440 1441 switch (request) { 1442 /* read the word at location addr in the USER area. */ 1443 case PTRACE_PEEKUSR: { 1444 unsigned long index, tmp; 1445 1446 ret = -EIO; 1447 /* convert to index and check */ 1448#ifdef CONFIG_PPC32 1449 index = (unsigned long) addr >> 2; 1450 if ((addr & 3) || (index > PT_FPSCR) 1451 || (child->thread.regs == NULL)) 1452#else 1453 index = (unsigned long) addr >> 3; 1454 if ((addr & 7) || (index > PT_FPSCR)) 1455#endif 1456 break; 1457 1458 CHECK_FULL_REGS(child->thread.regs); 1459 if (index < PT_FPR0) { 1460 tmp = ptrace_get_reg(child, (int) index); 1461 } else { 1462 flush_fp_to_thread(child); 1463 tmp = ((unsigned long *)child->thread.fpr) 1464 [TS_FPRWIDTH * (index - PT_FPR0)]; 1465 } 1466 ret = put_user(tmp,(unsigned long __user *) data); 1467 break; 1468 } 1469 1470 /* write the word at location addr in the USER area */ 1471 case PTRACE_POKEUSR: { 1472 unsigned long index; 1473 1474 ret = -EIO; 1475 /* convert to index and check */ 1476#ifdef CONFIG_PPC32 1477 index = (unsigned long) addr >> 2; 1478 if ((addr & 3) || (index > PT_FPSCR) 1479 || (child->thread.regs == NULL)) 1480#else 1481 index = (unsigned long) addr >> 3; 1482 if ((addr & 7) || (index > PT_FPSCR)) 1483#endif 1484 break; 1485 1486 CHECK_FULL_REGS(child->thread.regs); 1487 if (index < PT_FPR0) { 1488 ret = ptrace_put_reg(child, index, data); 1489 } else { 1490 flush_fp_to_thread(child); 1491 ((unsigned long *)child->thread.fpr) 1492 [TS_FPRWIDTH * (index - PT_FPR0)] = data; 1493 ret = 0; 1494 } 1495 break; 1496 } 1497 1498 case PPC_PTRACE_GETHWDBGINFO: { 1499 struct ppc_debug_info dbginfo; 1500 1501 dbginfo.version = 1; 1502#ifdef CONFIG_PPC_ADV_DEBUG_REGS 1503 dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS; 1504 dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS; 1505 dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS; 1506 dbginfo.data_bp_alignment = 4; 1507 dbginfo.sizeof_condition = 4; 1508 dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE | 1509 PPC_DEBUG_FEATURE_INSN_BP_MASK; 1510#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1511 dbginfo.features |= 1512 PPC_DEBUG_FEATURE_DATA_BP_RANGE | 1513 PPC_DEBUG_FEATURE_DATA_BP_MASK; 1514#endif 1515#else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 1516 dbginfo.num_instruction_bps = 0; 1517 dbginfo.num_data_bps = 1; 1518 dbginfo.num_condition_regs = 0; 1519#ifdef CONFIG_PPC64 1520 dbginfo.data_bp_alignment = 8; 1521#else 1522 dbginfo.data_bp_alignment = 4; 1523#endif 1524 dbginfo.sizeof_condition = 0; 1525 dbginfo.features = 0; 1526#endif /* CONFIG_PPC_ADV_DEBUG_REGS */ 1527 1528 if (!access_ok(VERIFY_WRITE, data, 1529 sizeof(struct ppc_debug_info))) 1530 return -EFAULT; 1531 ret = __copy_to_user((struct ppc_debug_info __user *)data, 1532 &dbginfo, sizeof(struct ppc_debug_info)) ? 1533 -EFAULT : 0; 1534 break; 1535 } 1536 1537 case PPC_PTRACE_SETHWDEBUG: { 1538 struct ppc_hw_breakpoint bp_info; 1539 1540 if (!access_ok(VERIFY_READ, data, 1541 sizeof(struct ppc_hw_breakpoint))) 1542 return -EFAULT; 1543 ret = __copy_from_user(&bp_info, 1544 (struct ppc_hw_breakpoint __user *)data, 1545 sizeof(struct ppc_hw_breakpoint)) ? 1546 -EFAULT : 0; 1547 if (!ret) 1548 ret = ppc_set_hwdebug(child, &bp_info); 1549 break; 1550 } 1551 1552 case PPC_PTRACE_DELHWDEBUG: { 1553 ret = ppc_del_hwdebug(child, addr, data); 1554 break; 1555 } 1556 1557 case PTRACE_GET_DEBUGREG: { 1558 ret = -EINVAL; 1559 /* We only support one DABR and no IABRS at the moment */ 1560 if (addr > 0) 1561 break; 1562#ifdef CONFIG_PPC_ADV_DEBUG_REGS 1563 ret = put_user(child->thread.dac1, 1564 (unsigned long __user *)data); 1565#else 1566 ret = put_user(child->thread.dabr, 1567 (unsigned long __user *)data); 1568#endif 1569 break; 1570 } 1571 1572 case PTRACE_SET_DEBUGREG: 1573 ret = ptrace_set_debugreg(child, addr, data); 1574 break; 1575 1576#ifdef CONFIG_PPC64 1577 case PTRACE_GETREGS64: 1578#endif 1579 case PTRACE_GETREGS: /* Get all pt_regs from the child. */ 1580 return copy_regset_to_user(child, &user_ppc_native_view, 1581 REGSET_GPR, 1582 0, sizeof(struct pt_regs), 1583 (void __user *) data); 1584 1585#ifdef CONFIG_PPC64 1586 case PTRACE_SETREGS64: 1587#endif 1588 case PTRACE_SETREGS: /* Set all gp regs in the child. */ 1589 return copy_regset_from_user(child, &user_ppc_native_view, 1590 REGSET_GPR, 1591 0, sizeof(struct pt_regs), 1592 (const void __user *) data); 1593 1594 case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */ 1595 return copy_regset_to_user(child, &user_ppc_native_view, 1596 REGSET_FPR, 1597 0, sizeof(elf_fpregset_t), 1598 (void __user *) data); 1599 1600 case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */ 1601 return copy_regset_from_user(child, &user_ppc_native_view, 1602 REGSET_FPR, 1603 0, sizeof(elf_fpregset_t), 1604 (const void __user *) data); 1605 1606#ifdef CONFIG_ALTIVEC 1607 case PTRACE_GETVRREGS: 1608 return copy_regset_to_user(child, &user_ppc_native_view, 1609 REGSET_VMX, 1610 0, (33 * sizeof(vector128) + 1611 sizeof(u32)), 1612 (void __user *) data); 1613 1614 case PTRACE_SETVRREGS: 1615 return copy_regset_from_user(child, &user_ppc_native_view, 1616 REGSET_VMX, 1617 0, (33 * sizeof(vector128) + 1618 sizeof(u32)), 1619 (const void __user *) data); 1620#endif 1621#ifdef CONFIG_VSX 1622 case PTRACE_GETVSRREGS: 1623 return copy_regset_to_user(child, &user_ppc_native_view, 1624 REGSET_VSX, 1625 0, 32 * sizeof(double), 1626 (void __user *) data); 1627 1628 case PTRACE_SETVSRREGS: 1629 return copy_regset_from_user(child, &user_ppc_native_view, 1630 REGSET_VSX, 1631 0, 32 * sizeof(double), 1632 (const void __user *) data); 1633#endif 1634#ifdef CONFIG_SPE 1635 case PTRACE_GETEVRREGS: 1636 /* Get the child spe register state. */ 1637 return copy_regset_to_user(child, &user_ppc_native_view, 1638 REGSET_SPE, 0, 35 * sizeof(u32), 1639 (void __user *) data); 1640 1641 case PTRACE_SETEVRREGS: 1642 /* Set the child spe register state. */ 1643 return copy_regset_from_user(child, &user_ppc_native_view, 1644 REGSET_SPE, 0, 35 * sizeof(u32), 1645 (const void __user *) data); 1646#endif 1647 1648 /* Old reverse args ptrace callss */ 1649 case PPC_PTRACE_GETREGS: /* Get GPRs 0 - 31. */ 1650 case PPC_PTRACE_SETREGS: /* Set GPRs 0 - 31. */ 1651 case PPC_PTRACE_GETFPREGS: /* Get FPRs 0 - 31. */ 1652 case PPC_PTRACE_SETFPREGS: /* Get FPRs 0 - 31. */ 1653 ret = arch_ptrace_old(child, request, addr, data); 1654 break; 1655 1656 default: 1657 ret = ptrace_request(child, request, addr, data); 1658 break; 1659 } 1660 return ret; 1661} 1662 1663/* 1664 * We must return the syscall number to actually look up in the table. 1665 * This can be -1L to skip running any syscall at all. 1666 */ 1667long do_syscall_trace_enter(struct pt_regs *regs) 1668{ 1669 long ret = 0; 1670 1671 secure_computing(regs->gpr[0]); 1672 1673 if (test_thread_flag(TIF_SYSCALL_TRACE) && 1674 tracehook_report_syscall_entry(regs)) 1675 /* 1676 * Tracing decided this syscall should not happen. 1677 * We'll return a bogus call number to get an ENOSYS 1678 * error, but leave the original number in regs->gpr[0]. 1679 */ 1680 ret = -1L; 1681 1682 if (unlikely(current->audit_context)) { 1683#ifdef CONFIG_PPC64 1684 if (!test_thread_flag(TIF_32BIT)) 1685 audit_syscall_entry(AUDIT_ARCH_PPC64, 1686 regs->gpr[0], 1687 regs->gpr[3], regs->gpr[4], 1688 regs->gpr[5], regs->gpr[6]); 1689 else 1690#endif 1691 audit_syscall_entry(AUDIT_ARCH_PPC, 1692 regs->gpr[0], 1693 regs->gpr[3] & 0xffffffff, 1694 regs->gpr[4] & 0xffffffff, 1695 regs->gpr[5] & 0xffffffff, 1696 regs->gpr[6] & 0xffffffff); 1697 } 1698 1699 return ret ?: regs->gpr[0]; 1700} 1701 1702void do_syscall_trace_leave(struct pt_regs *regs) 1703{ 1704 int step; 1705 1706 if (unlikely(current->audit_context)) 1707 audit_syscall_exit((regs->ccr&0x10000000)?AUDITSC_FAILURE:AUDITSC_SUCCESS, 1708 regs->result); 1709 1710 step = test_thread_flag(TIF_SINGLESTEP); 1711 if (step || test_thread_flag(TIF_SYSCALL_TRACE)) 1712 tracehook_report_syscall_exit(regs, step); 1713} 1714