1/* 2 * This file contains low level CPU setup functions. 3 * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org) 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 */ 11 12#include <asm/processor.h> 13#include <asm/page.h> 14#include <asm/cputable.h> 15#include <asm/ppc_asm.h> 16#include <asm/asm-offsets.h> 17#include <asm/cache.h> 18 19_GLOBAL(__cpu_preinit_ppc970) 20 /* Do nothing if not running in HV mode */ 21 mfmsr r0 22 rldicl. r0,r0,4,63 23 beqlr 24 25 /* Make sure HID4:rm_ci is off before MMU is turned off, that large 26 * pages are enabled with HID4:61 and clear HID5:DCBZ_size and 27 * HID5:DCBZ32_ill 28 */ 29 li r0,0 30 mfspr r3,SPRN_HID4 31 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 32 rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */ 33 sync 34 mtspr SPRN_HID4,r3 35 isync 36 sync 37 mfspr r3,SPRN_HID5 38 rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */ 39 sync 40 mtspr SPRN_HID5,r3 41 isync 42 sync 43 44 /* Setup some basic HID1 features */ 45 mfspr r0,SPRN_HID1 46 li r3,0x1200 /* enable i-fetch cacheability */ 47 sldi r3,r3,44 /* and prefetch */ 48 or r0,r0,r3 49 mtspr SPRN_HID1,r0 50 mtspr SPRN_HID1,r0 51 isync 52 53 /* Clear HIOR */ 54 li r0,0 55 sync 56 mtspr SPRN_HIOR,0 /* Clear interrupt prefix */ 57 isync 58 blr 59 60/* Definitions for the table use to save CPU states */ 61#define CS_HID0 0 62#define CS_HID1 8 63#define CS_HID4 16 64#define CS_HID5 24 65#define CS_SIZE 32 66 67 .data 68 .balign L1_CACHE_BYTES,0 69cpu_state_storage: 70 .space CS_SIZE 71 .balign L1_CACHE_BYTES,0 72 .text 73 74 75_GLOBAL(__setup_cpu_ppc970) 76 /* Do nothing if not running in HV mode */ 77 mfmsr r0 78 rldicl. r0,r0,4,63 79 beqlr 80 81 mfspr r0,SPRN_HID0 82 li r11,5 /* clear DOZE and SLEEP */ 83 rldimi r0,r11,52,8 /* set NAP and DPM */ 84 li r11,0 85 rldimi r0,r11,32,31 /* clear EN_ATTN */ 86 b load_hids /* Jump to shared code */ 87 88 89_GLOBAL(__setup_cpu_ppc970MP) 90 /* Do nothing if not running in HV mode */ 91 mfmsr r0 92 rldicl. r0,r0,4,63 93 beqlr 94 95 mfspr r0,SPRN_HID0 96 li r11,0x15 /* clear DOZE and SLEEP */ 97 rldimi r0,r11,52,6 /* set DEEPNAP, NAP and DPM */ 98 li r11,0 99 rldimi r0,r11,32,31 /* clear EN_ATTN */ 100 101load_hids: 102 mtspr SPRN_HID0,r0 103 mfspr r0,SPRN_HID0 104 mfspr r0,SPRN_HID0 105 mfspr r0,SPRN_HID0 106 mfspr r0,SPRN_HID0 107 mfspr r0,SPRN_HID0 108 mfspr r0,SPRN_HID0 109 sync 110 isync 111 112 /* Save away cpu state */ 113 LOAD_REG_ADDR(r5,cpu_state_storage) 114 115 /* Save HID0,1,4 and 5 */ 116 mfspr r3,SPRN_HID0 117 std r3,CS_HID0(r5) 118 mfspr r3,SPRN_HID1 119 std r3,CS_HID1(r5) 120 mfspr r3,SPRN_HID4 121 std r3,CS_HID4(r5) 122 mfspr r3,SPRN_HID5 123 std r3,CS_HID5(r5) 124 125 blr 126 127/* Called with no MMU context (typically MSR:IR/DR off) to 128 * restore CPU state as backed up by the previous 129 * function. This does not include cache setting 130 */ 131_GLOBAL(__restore_cpu_ppc970) 132 /* Do nothing if not running in HV mode */ 133 mfmsr r0 134 rldicl. r0,r0,4,63 135 beqlr 136 137 LOAD_REG_ADDR(r5,cpu_state_storage) 138 /* Before accessing memory, we make sure rm_ci is clear */ 139 li r0,0 140 mfspr r3,SPRN_HID4 141 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 142 sync 143 mtspr SPRN_HID4,r3 144 isync 145 sync 146 147 /* Clear interrupt prefix */ 148 li r0,0 149 sync 150 mtspr SPRN_HIOR,0 151 isync 152 153 /* Restore HID0 */ 154 ld r3,CS_HID0(r5) 155 sync 156 isync 157 mtspr SPRN_HID0,r3 158 mfspr r3,SPRN_HID0 159 mfspr r3,SPRN_HID0 160 mfspr r3,SPRN_HID0 161 mfspr r3,SPRN_HID0 162 mfspr r3,SPRN_HID0 163 mfspr r3,SPRN_HID0 164 sync 165 isync 166 167 /* Restore HID1 */ 168 ld r3,CS_HID1(r5) 169 sync 170 isync 171 mtspr SPRN_HID1,r3 172 mtspr SPRN_HID1,r3 173 sync 174 isync 175 176 /* Restore HID4 */ 177 ld r3,CS_HID4(r5) 178 sync 179 isync 180 mtspr SPRN_HID4,r3 181 sync 182 isync 183 184 /* Restore HID5 */ 185 ld r3,CS_HID5(r5) 186 sync 187 isync 188 mtspr SPRN_HID5,r3 189 sync 190 isync 191 blr 192