1 2 3#ifndef _ASM_POWERPC_REG_H 4#define _ASM_POWERPC_REG_H 5#ifdef __KERNEL__ 6 7#include <linux/stringify.h> 8#include <asm/cputable.h> 9 10/* Pickup Book E specific registers. */ 11#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 12#include <asm/reg_booke.h> 13#endif /* CONFIG_BOOKE || CONFIG_40x */ 14 15#ifdef CONFIG_FSL_EMB_PERFMON 16#include <asm/reg_fsl_emb.h> 17#endif 18 19#ifdef CONFIG_8xx 20#include <asm/reg_8xx.h> 21#endif /* CONFIG_8xx */ 22 23#define MSR_SF_LG 63 /* Enable 64 bit mode */ 24#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ 25#define MSR_HV_LG 60 /* Hypervisor state */ 26#define MSR_VEC_LG 25 /* Enable AltiVec */ 27#define MSR_VSX_LG 23 /* Enable VSX */ 28#define MSR_POW_LG 18 /* Enable Power Management */ 29#define MSR_WE_LG 18 /* Wait State Enable */ 30#define MSR_TGPR_LG 17 /* TLB Update registers in use */ 31#define MSR_CE_LG 17 /* Critical Interrupt Enable */ 32#define MSR_ILE_LG 16 /* Interrupt Little Endian */ 33#define MSR_EE_LG 15 /* External Interrupt Enable */ 34#define MSR_PR_LG 14 /* Problem State / Privilege Level */ 35#define MSR_FP_LG 13 /* Floating Point enable */ 36#define MSR_ME_LG 12 /* Machine Check Enable */ 37#define MSR_FE0_LG 11 /* Floating Exception mode 0 */ 38#define MSR_SE_LG 10 /* Single Step */ 39#define MSR_BE_LG 9 /* Branch Trace */ 40#define MSR_DE_LG 9 /* Debug Exception Enable */ 41#define MSR_FE1_LG 8 /* Floating Exception mode 1 */ 42#define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */ 43#define MSR_IR_LG 5 /* Instruction Relocate */ 44#define MSR_DR_LG 4 /* Data Relocate */ 45#define MSR_PE_LG 3 /* Protection Enable */ 46#define MSR_PX_LG 2 /* Protection Exclusive Mode */ 47#define MSR_PMM_LG 2 /* Performance monitor */ 48#define MSR_RI_LG 1 /* Recoverable Exception */ 49#define MSR_LE_LG 0 /* Little Endian */ 50 51#ifdef __ASSEMBLY__ 52#define __MASK(X) (1<<(X)) 53#else 54#define __MASK(X) (1UL<<(X)) 55#endif 56 57#ifdef CONFIG_PPC64 58#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ 59#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */ 60#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ 61#else 62/* so tests for these bits fail on 32-bit */ 63#define MSR_SF 0 64#define MSR_ISF 0 65#define MSR_HV 0 66#endif 67 68#define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */ 69#define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */ 70#define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */ 71#define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */ 72#define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */ 73#define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */ 74#define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */ 75#define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */ 76#define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */ 77#define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */ 78#define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */ 79#define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */ 80#define MSR_SE __MASK(MSR_SE_LG) /* Single Step */ 81#define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */ 82#define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */ 83#define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */ 84#define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */ 85#define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */ 86#define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */ 87#define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */ 88#define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */ 89#ifndef MSR_PMM 90#define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */ 91#endif 92#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */ 93#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */ 94 95#if defined(CONFIG_PPC_BOOK3S_64) 96/* Server variant */ 97#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV 98#define MSR_KERNEL MSR_ | MSR_SF 99#define MSR_USER32 MSR_ | MSR_PR | MSR_EE 100#define MSR_USER64 MSR_USER32 | MSR_SF 101#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx) 102/* Default MSR for kernel mode. */ 103#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) 104#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) 105#endif 106 107/* Floating Point Status and Control Register (FPSCR) Fields */ 108#define FPSCR_FX 0x80000000 /* FPU exception summary */ 109#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ 110#define FPSCR_VX 0x20000000 /* Invalid operation summary */ 111#define FPSCR_OX 0x10000000 /* Overflow exception summary */ 112#define FPSCR_UX 0x08000000 /* Underflow exception summary */ 113#define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */ 114#define FPSCR_XX 0x02000000 /* Inexact exception summary */ 115#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ 116#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ 117#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ 118#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ 119#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ 120#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ 121#define FPSCR_FR 0x00040000 /* Fraction rounded */ 122#define FPSCR_FI 0x00020000 /* Fraction inexact */ 123#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ 124#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ 125#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ 126#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ 127#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ 128#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ 129#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ 130#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ 131#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ 132#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ 133#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ 134#define FPSCR_RN 0x00000003 /* FPU rounding control */ 135 136/* Bit definitions for SPEFSCR. */ 137#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */ 138#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */ 139#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */ 140#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */ 141#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */ 142#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */ 143#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */ 144#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */ 145#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */ 146#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */ 147#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */ 148#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */ 149#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */ 150#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */ 151#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */ 152#define SPEFSCR_OV 0x00004000 /* Integer overflow */ 153#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */ 154#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */ 155#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */ 156#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */ 157#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */ 158#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */ 159#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */ 160#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */ 161#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */ 162#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */ 163#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */ 164#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ 165 166/* Special Purpose Registers (SPRNs)*/ 167#define SPRN_CTR 0x009 /* Count Register */ 168#define SPRN_DSCR 0x11 169#define SPRN_CTRLF 0x088 170#define SPRN_CTRLT 0x098 171#define CTRL_CT 0xc0000000 /* current thread */ 172#define CTRL_CT0 0x80000000 /* thread 0 */ 173#define CTRL_CT1 0x40000000 /* thread 1 */ 174#define CTRL_TE 0x00c00000 /* thread enable */ 175#define CTRL_RUNLATCH 0x1 176#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ 177#define DABR_TRANSLATION (1UL << 2) 178#define DABR_DATA_WRITE (1UL << 1) 179#define DABR_DATA_READ (1UL << 0) 180#define SPRN_DABR2 0x13D /* e300 */ 181#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */ 182#define DABRX_USER (1UL << 0) 183#define DABRX_KERNEL (1UL << 1) 184#define SPRN_DAR 0x013 /* Data Address Register */ 185#define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */ 186#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ 187#define DSISR_NOHPTE 0x40000000 /* no translation found */ 188#define DSISR_PROTFAULT 0x08000000 /* protection fault */ 189#define DSISR_ISSTORE 0x02000000 /* access was a store */ 190#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */ 191#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */ 192#define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */ 193#define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */ 194#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */ 195#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ 196#define SPRN_SPURR 0x134 /* Scaled PURR */ 197#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ 198#define SPRN_LPCR 0x13E /* LPAR Control Register */ 199#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ 200#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ 201#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ 202#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ 203#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ 204#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ 205#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ 206#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ 207#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ 208#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ 209#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ 210#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ 211#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ 212#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ 213#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ 214#define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */ 215 216#define SPRN_DEC 0x016 /* Decrement Register */ 217#define SPRN_DER 0x095 /* Debug Enable Regsiter */ 218#define DER_RSTE 0x40000000 /* Reset Interrupt */ 219#define DER_CHSTPE 0x20000000 /* Check Stop */ 220#define DER_MCIE 0x10000000 /* Machine Check Interrupt */ 221#define DER_EXTIE 0x02000000 /* External Interrupt */ 222#define DER_ALIE 0x01000000 /* Alignment Interrupt */ 223#define DER_PRIE 0x00800000 /* Program Interrupt */ 224#define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */ 225#define DER_DECIE 0x00200000 /* Decrementer Interrupt */ 226#define DER_SYSIE 0x00040000 /* System Call Interrupt */ 227#define DER_TRE 0x00020000 /* Trace Interrupt */ 228#define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */ 229#define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */ 230#define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */ 231#define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */ 232#define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */ 233#define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */ 234#define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */ 235#define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */ 236#define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */ 237#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ 238#define SPRN_EAR 0x11A /* External Address Register */ 239#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ 240#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ 241#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ 242#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ 243#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ 244#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ 245#define HID0_SBCLK (1<<27) 246#define HID0_EICE (1<<26) 247#define HID0_TBEN (1<<26) /* Timebase enable - 745x */ 248#define HID0_ECLK (1<<25) 249#define HID0_PAR (1<<24) 250#define HID0_STEN (1<<24) /* Software table search enable - 745x */ 251#define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */ 252#define HID0_DOZE (1<<23) 253#define HID0_NAP (1<<22) 254#define HID0_SLEEP (1<<21) 255#define HID0_DPM (1<<20) 256#define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */ 257#define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */ 258#define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/ 259#define HID0_ICE (1<<15) /* Instruction Cache Enable */ 260#define HID0_DCE (1<<14) /* Data Cache Enable */ 261#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ 262#define HID0_DLOCK (1<<12) /* Data Cache Lock */ 263#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ 264#define HID0_DCI (1<<10) /* Data Cache Invalidate */ 265#define HID0_SPD (1<<9) /* Speculative disable */ 266#define HID0_DAPUEN (1<<8) /* Debug APU enable */ 267#define HID0_SGE (1<<7) /* Store Gathering Enable */ 268#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ 269#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ 270#define HID0_LRSTK (1<<4) /* Link register stack - 745x */ 271#define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */ 272#define HID0_ABE (1<<3) /* Address Broadcast Enable */ 273#define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */ 274#define HID0_BHTE (1<<2) /* Branch History Table Enable */ 275#define HID0_BTCD (1<<1) /* Branch target cache disable */ 276#define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */ 277#define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */ 278 279#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ 280#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */ 281#define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */ 282#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */ 283#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */ 284#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */ 285#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */ 286#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */ 287#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ 288#define HID1_PS (1<<16) /* 750FX PLL selection */ 289#define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */ 290#define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */ 291#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ 292#define SPRN_IABR2 0x3FA /* 83xx */ 293#define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */ 294#define SPRN_HID4 0x3F4 /* 970 HID4 */ 295#define SPRN_HID4_GEKKO 0x3F3 /* Gekko HID4 */ 296#define SPRN_HID5 0x3F6 /* 970 HID5 */ 297#define SPRN_HID6 0x3F9 /* BE HID 6 */ 298#define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */ 299#define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */ 300#define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */ 301#define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */ 302#define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */ 303#define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */ 304#define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */ 305#define SPRN_TSC 0x3FD /* Thread switch control on others */ 306#define SPRN_TST 0x3FC /* Thread switch timeout on others */ 307#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2) 308#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ 309#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ 310#endif 311#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ 312#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ 313#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ 314#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ 315#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ 316#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ 317#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ 318#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ 319#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ 320#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ 321#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ 322#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ 323#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ 324#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ 325#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ 326#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ 327#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ 328#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ 329#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */ 330#define ICTRL_EICE 0x08000000 /* enable icache parity errs */ 331#define ICTRL_EDC 0x04000000 /* enable dcache parity errs */ 332#define ICTRL_EICP 0x00000100 /* enable icache par. check */ 333#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ 334#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ 335#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ 336#define SPRN_L2CR2 0x3f8 337#define L2CR_L2E 0x80000000 /* L2 enable */ 338#define L2CR_L2PE 0x40000000 /* L2 parity enable */ 339#define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */ 340#define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */ 341#define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */ 342#define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */ 343#define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */ 344#define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */ 345#define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */ 346#define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */ 347#define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */ 348#define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */ 349#define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */ 350#define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */ 351#define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */ 352#define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */ 353#define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */ 354#define L2CR_L2DO 0x00400000 /* L2 data only */ 355#define L2CR_L2I 0x00200000 /* L2 global invalidate */ 356#define L2CR_L2CTL 0x00100000 /* L2 RAM control */ 357#define L2CR_L2WT 0x00080000 /* L2 write-through */ 358#define L2CR_L2TS 0x00040000 /* L2 test support */ 359#define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */ 360#define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */ 361#define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */ 362#define L2CR_L2SL 0x00008000 /* L2 DLL slow */ 363#define L2CR_L2DF 0x00004000 /* L2 differential clock */ 364#define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */ 365#define L2CR_L2IP 0x00000001 /* L2 GI in progress */ 366#define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */ 367#define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */ 368#define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */ 369#define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */ 370#define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */ 371#define L3CR_L3E 0x80000000 /* L3 enable */ 372#define L3CR_L3PE 0x40000000 /* L3 data parity enable */ 373#define L3CR_L3APE 0x20000000 /* L3 addr parity enable */ 374#define L3CR_L3SIZ 0x10000000 /* L3 size */ 375#define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */ 376#define L3CR_L3RES 0x04000000 /* L3 special reserved bit */ 377#define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */ 378#define L3CR_L3IO 0x00400000 /* L3 instruction only */ 379#define L3CR_L3SPO 0x00040000 /* L3 sample point override */ 380#define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */ 381#define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */ 382#define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */ 383#define L3CR_L3HWF 0x00000800 /* L3 hardware flush */ 384#define L3CR_L3I 0x00000400 /* L3 global invalidate */ 385#define L3CR_L3RT 0x00000300 /* L3 SRAM type */ 386#define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */ 387#define L3CR_L3DO 0x00000040 /* L3 data only mode */ 388#define L3CR_PMEN 0x00000004 /* L3 private memory enable */ 389#define L3CR_PMSIZ 0x00000001 /* L3 private memory size */ 390 391#define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */ 392#define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */ 393#define SPRN_LDSTCR 0x3f8 /* Load/Store control register */ 394#define SPRN_LDSTDB 0x3f4 /* */ 395#define SPRN_LR 0x008 /* Link Register */ 396#ifndef SPRN_PIR 397#define SPRN_PIR 0x3FF /* Processor Identification Register */ 398#endif 399#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ 400#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ 401#define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ 402#define SPRN_PVR 0x11F /* Processor Version Register */ 403#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ 404#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ 405#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ 406#define SPRN_ASR 0x118 /* Address Space Register */ 407#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ 408#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ 409#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ 410#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ 411#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ 412#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ 413#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ 414#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ 415#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ 416#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ 417#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ 418#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */ 419#define SRR1_WAKERESET 0x00380000 /* System reset */ 420#define SRR1_WAKESYSERR 0x00300000 /* System error */ 421#define SRR1_WAKEEE 0x00200000 /* External interrupt */ 422#define SRR1_WAKEMT 0x00280000 /* mtctrl */ 423#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ 424#define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */ 425#define SRR1_PROGFPE 0x00100000 /* Floating Point Enabled */ 426#define SRR1_PROGPRIV 0x00040000 /* Privileged instruction */ 427#define SRR1_PROGTRAP 0x00020000 /* Trap */ 428#define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */ 429#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ 430#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ 431 432#define SPRN_TBCTL 0x35f /* PA6T Timebase control register */ 433#define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */ 434#define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */ 435#define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */ 436#define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */ 437 438#ifndef SPRN_SVR 439#define SPRN_SVR 0x11E /* System Version Register */ 440#endif 441#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ 442/* these bits were defined in inverted endian sense originally, ugh, confusing */ 443#define THRM1_TIN (1 << 31) 444#define THRM1_TIV (1 << 30) 445#define THRM1_THRES(x) ((x&0x7f)<<23) 446#define THRM3_SITV(x) ((x&0x3fff)<<1) 447#define THRM1_TID (1<<2) 448#define THRM1_TIE (1<<1) 449#define THRM1_V (1<<0) 450#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ 451#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ 452#define THRM3_E (1<<0) 453#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ 454#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ 455#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ 456#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ 457#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ 458#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ 459#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ 460#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ 461#define SPRN_VRSAVE 0x100 /* Vector Register Save Register */ 462#define SPRN_XER 0x001 /* Fixed Point Exception Register */ 463 464#define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */ 465#define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */ 466#define SPRN_PMC1_GEKKO 0x3B9 /* Gekko Performance Monitor Control 1 */ 467#define SPRN_PMC2_GEKKO 0x3BA /* Gekko Performance Monitor Control 2 */ 468#define SPRN_PMC3_GEKKO 0x3BD /* Gekko Performance Monitor Control 3 */ 469#define SPRN_PMC4_GEKKO 0x3BE /* Gekko Performance Monitor Control 4 */ 470#define SPRN_WPAR_GEKKO 0x399 /* Gekko Write Pipe Address Register */ 471 472#define SPRN_SCOMC 0x114 /* SCOM Access Control */ 473#define SPRN_SCOMD 0x115 /* SCOM Access DATA */ 474 475/* Performance monitor SPRs */ 476#ifdef CONFIG_PPC64 477#define SPRN_MMCR0 795 478#define MMCR0_FC 0x80000000UL /* freeze counters */ 479#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ 480#define MMCR0_KERNEL_DISABLE MMCR0_FCS 481#define MMCR0_FCP 0x20000000UL /* freeze in problem state */ 482#define MMCR0_PROBLEM_DISABLE MMCR0_FCP 483#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ 484#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ 485#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ 486#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ 487#define MMCR0_TBEE 0x00400000UL /* time base exception enable */ 488#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 489#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/ 490#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ 491#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */ 492#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */ 493#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */ 494#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */ 495#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */ 496#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */ 497#define SPRN_MMCR1 798 498#define SPRN_MMCRA 0x312 499#define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */ 500#define MMCRA_SDAR_DCACHE_MISS 0x40000000UL 501#define MMCRA_SDAR_ERAT_MISS 0x20000000UL 502#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ 503#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ 504#define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */ 505#define MMCRA_SLOT_SHIFT 24 506#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ 507#define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL /* SDAR/SIAR synced */ 508#define POWER6_MMCRA_SIHV 0x0000040000000000ULL 509#define POWER6_MMCRA_SIPR 0x0000020000000000ULL 510#define POWER6_MMCRA_THRM 0x00000020UL 511#define POWER6_MMCRA_OTHER 0x0000000EUL 512#define SPRN_PMC1 787 513#define SPRN_PMC2 788 514#define SPRN_PMC3 789 515#define SPRN_PMC4 790 516#define SPRN_PMC5 791 517#define SPRN_PMC6 792 518#define SPRN_PMC7 793 519#define SPRN_PMC8 794 520#define SPRN_SIAR 780 521#define SPRN_SDAR 781 522 523#define SPRN_PA6T_MMCR0 795 524#define PA6T_MMCR0_EN0 0x0000000000000001UL 525#define PA6T_MMCR0_EN1 0x0000000000000002UL 526#define PA6T_MMCR0_EN2 0x0000000000000004UL 527#define PA6T_MMCR0_EN3 0x0000000000000008UL 528#define PA6T_MMCR0_EN4 0x0000000000000010UL 529#define PA6T_MMCR0_EN5 0x0000000000000020UL 530#define PA6T_MMCR0_SUPEN 0x0000000000000040UL 531#define PA6T_MMCR0_PREN 0x0000000000000080UL 532#define PA6T_MMCR0_HYPEN 0x0000000000000100UL 533#define PA6T_MMCR0_FCM0 0x0000000000000200UL 534#define PA6T_MMCR0_FCM1 0x0000000000000400UL 535#define PA6T_MMCR0_INTGEN 0x0000000000000800UL 536#define PA6T_MMCR0_INTEN0 0x0000000000001000UL 537#define PA6T_MMCR0_INTEN1 0x0000000000002000UL 538#define PA6T_MMCR0_INTEN2 0x0000000000004000UL 539#define PA6T_MMCR0_INTEN3 0x0000000000008000UL 540#define PA6T_MMCR0_INTEN4 0x0000000000010000UL 541#define PA6T_MMCR0_INTEN5 0x0000000000020000UL 542#define PA6T_MMCR0_DISCNT 0x0000000000040000UL 543#define PA6T_MMCR0_UOP 0x0000000000080000UL 544#define PA6T_MMCR0_TRG 0x0000000000100000UL 545#define PA6T_MMCR0_TRGEN 0x0000000000200000UL 546#define PA6T_MMCR0_TRGREG 0x0000000001600000UL 547#define PA6T_MMCR0_SIARLOG 0x0000000002000000UL 548#define PA6T_MMCR0_SDARLOG 0x0000000004000000UL 549#define PA6T_MMCR0_PROEN 0x0000000008000000UL 550#define PA6T_MMCR0_PROLOG 0x0000000010000000UL 551#define PA6T_MMCR0_DAMEN2 0x0000000020000000UL 552#define PA6T_MMCR0_DAMEN3 0x0000000040000000UL 553#define PA6T_MMCR0_DAMEN4 0x0000000080000000UL 554#define PA6T_MMCR0_DAMEN5 0x0000000100000000UL 555#define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL 556#define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL 557#define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL 558#define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL 559#define PA6T_MMCR0_HANDDIS 0x0000002000000000UL 560#define PA6T_MMCR0_PCTEN 0x0000004000000000UL 561#define PA6T_MMCR0_SOCEN 0x0000008000000000UL 562#define PA6T_MMCR0_SOCMOD 0x0000010000000000UL 563 564#define SPRN_PA6T_MMCR1 798 565#define PA6T_MMCR1_ES2 0x00000000000000ffUL 566#define PA6T_MMCR1_ES3 0x000000000000ff00UL 567#define PA6T_MMCR1_ES4 0x0000000000ff0000UL 568#define PA6T_MMCR1_ES5 0x00000000ff000000UL 569 570#define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */ 571#define SPRN_PA6T_UPMC1 772 /* ... */ 572#define SPRN_PA6T_UPMC2 773 573#define SPRN_PA6T_UPMC3 774 574#define SPRN_PA6T_UPMC4 775 575#define SPRN_PA6T_UPMC5 776 576#define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */ 577#define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */ 578#define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */ 579#define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */ 580#define SPRN_PA6T_PMC0 787 581#define SPRN_PA6T_PMC1 788 582#define SPRN_PA6T_PMC2 789 583#define SPRN_PA6T_PMC3 790 584#define SPRN_PA6T_PMC4 791 585#define SPRN_PA6T_PMC5 792 586#define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */ 587#define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */ 588#define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */ 589#define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */ 590 591#define SPRN_PA6T_IER 981 /* Icache Error Register */ 592#define SPRN_PA6T_DER 982 /* Dcache Error Register */ 593#define SPRN_PA6T_BER 862 /* BIU Error Address Register */ 594#define SPRN_PA6T_MER 849 /* MMU Error Register */ 595 596#define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */ 597#define SPRN_PA6T_IMA1 881 /* ... */ 598#define SPRN_PA6T_IMA2 882 599#define SPRN_PA6T_IMA3 883 600#define SPRN_PA6T_IMA4 884 601#define SPRN_PA6T_IMA5 885 602#define SPRN_PA6T_IMA6 886 603#define SPRN_PA6T_IMA7 887 604#define SPRN_PA6T_IMA8 888 605#define SPRN_PA6T_IMA9 889 606#define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */ 607#define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */ 608#define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */ 609#define SPRN_BKMK 1020 /* Cell Bookmark Register */ 610#define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */ 611 612 613#else /* 32-bit */ 614#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */ 615#define MMCR0_FC 0x80000000UL /* freeze counters */ 616#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ 617#define MMCR0_FCP 0x20000000UL /* freeze in problem state */ 618#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ 619#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ 620#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ 621#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ 622#define MMCR0_TBEE 0x00400000UL /* time base exception enable */ 623#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 624#define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/ 625#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ 626#define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */ 627#define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */ 628 629#define SPRN_MMCR1 956 630#define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */ 631#define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */ 632#define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */ 633#define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */ 634#define SPRN_MMCR2 944 635#define SPRN_PMC1 953 /* Performance Counter Register 1 */ 636#define SPRN_PMC2 954 /* Performance Counter Register 2 */ 637#define SPRN_PMC3 957 /* Performance Counter Register 3 */ 638#define SPRN_PMC4 958 /* Performance Counter Register 4 */ 639#define SPRN_PMC5 945 /* Performance Counter Register 5 */ 640#define SPRN_PMC6 946 /* Performance Counter Register 6 */ 641 642#define SPRN_SIAR 955 /* Sampled Instruction Address Register */ 643 644/* Bit definitions for MMCR0 and PMC1 / PMC2. */ 645#define MMCR0_PMC1_CYCLES (1 << 7) 646#define MMCR0_PMC1_ICACHEMISS (5 << 7) 647#define MMCR0_PMC1_DTLB (6 << 7) 648#define MMCR0_PMC2_DCACHEMISS 0x6 649#define MMCR0_PMC2_CYCLES 0x1 650#define MMCR0_PMC2_ITLB 0x7 651#define MMCR0_PMC2_LOADMISSTIME 0x5 652#endif 653 654/* 655 * SPRG usage: 656 * 657 * All 64-bit: 658 * - SPRG1 stores PACA pointer 659 * 660 * 64-bit server: 661 * - SPRG0 unused (reserved for HV on Power4) 662 * - SPRG2 scratch for exception vectors 663 * - SPRG3 unused (user visible) 664 * 665 * 64-bit embedded 666 * - SPRG0 generic exception scratch 667 * - SPRG2 TLB exception stack 668 * - SPRG3 unused (user visible) 669 * - SPRG4 unused (user visible) 670 * - SPRG6 TLB miss scratch (user visible, sorry !) 671 * - SPRG7 critical exception scratch 672 * - SPRG8 machine check exception scratch 673 * - SPRG9 debug exception scratch 674 * 675 * All 32-bit: 676 * - SPRG3 current thread_info pointer 677 * (virtual on BookE, physical on others) 678 * 679 * 32-bit classic: 680 * - SPRG0 scratch for exception vectors 681 * - SPRG1 scratch for exception vectors 682 * - SPRG2 indicator that we are in RTAS 683 * - SPRG4 (603 only) pseudo TLB LRU data 684 * 685 * 32-bit 40x: 686 * - SPRG0 scratch for exception vectors 687 * - SPRG1 scratch for exception vectors 688 * - SPRG2 scratch for exception vectors 689 * - SPRG4 scratch for exception vectors (not 403) 690 * - SPRG5 scratch for exception vectors (not 403) 691 * - SPRG6 scratch for exception vectors (not 403) 692 * - SPRG7 scratch for exception vectors (not 403) 693 * 694 * 32-bit 440 and FSL BookE: 695 * - SPRG0 scratch for exception vectors 696 * - SPRG1 scratch for exception vectors (*) 697 * - SPRG2 scratch for crit interrupts handler 698 * - SPRG4 scratch for exception vectors 699 * - SPRG5 scratch for exception vectors 700 * - SPRG6 scratch for machine check handler 701 * - SPRG7 scratch for exception vectors 702 * - SPRG9 scratch for debug vectors (e500 only) 703 * 704 * Additionally, BookE separates "read" and "write" 705 * of those registers. That allows to use the userspace 706 * readable variant for reads, which can avoid a fault 707 * with KVM type virtualization. 708 * 709 * (*) Under KVM, the host SPRG1 is used to point to 710 * the current VCPU data structure 711 * 712 * 32-bit 8xx: 713 * - SPRG0 scratch for exception vectors 714 * - SPRG1 scratch for exception vectors 715 * - SPRG2 apparently unused but initialized 716 * 717 */ 718#ifdef CONFIG_PPC64 719#define SPRN_SPRG_PACA SPRN_SPRG1 720#else 721#define SPRN_SPRG_THREAD SPRN_SPRG3 722#endif 723 724#ifdef CONFIG_PPC_BOOK3S_64 725#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2 726#endif 727 728#ifdef CONFIG_PPC_BOOK3E_64 729#define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8 730#define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG7 731#define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9 732#define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2 733#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6 734#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0 735#endif 736 737#ifdef CONFIG_PPC_BOOK3S_32 738#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 739#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 740#define SPRN_SPRG_RTAS SPRN_SPRG2 741#define SPRN_SPRG_603_LRU SPRN_SPRG4 742#endif 743 744#ifdef CONFIG_40x 745#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 746#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 747#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2 748#define SPRN_SPRG_SCRATCH3 SPRN_SPRG4 749#define SPRN_SPRG_SCRATCH4 SPRN_SPRG5 750#define SPRN_SPRG_SCRATCH5 SPRN_SPRG6 751#define SPRN_SPRG_SCRATCH6 SPRN_SPRG7 752#endif 753 754#ifdef CONFIG_BOOKE 755#define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0 756#define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0 757#define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1 758#define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1 759#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2 760#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2 761#define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R 762#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W 763#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R 764#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W 765#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG6R 766#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG6W 767#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R 768#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W 769#ifdef CONFIG_E200 770#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG6R 771#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG6W 772#else 773#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9 774#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9 775#endif 776#define SPRN_SPRG_RVCPU SPRN_SPRG1 777#define SPRN_SPRG_WVCPU SPRN_SPRG1 778#endif 779 780#ifdef CONFIG_8xx 781#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 782#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 783#endif 784 785/* 786 * An mtfsf instruction with the L bit set. On CPUs that support this a 787 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored. 788 * 789 * Until binutils gets the new form of mtfsf, hardwire the instruction. 790 */ 791#ifdef CONFIG_PPC64 792#define MTFSF_L(REG) \ 793 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25)) 794#else 795#define MTFSF_L(REG) mtfsf 0xff, (REG) 796#endif 797 798/* Processor Version Register (PVR) field extraction */ 799 800#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ 801#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ 802 803#define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv)) 804 805/* 806 * IBM has further subdivided the standard PowerPC 16-bit version and 807 * revision subfields of the PVR for the PowerPC 403s into the following: 808 */ 809 810#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ 811#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ 812#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ 813#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ 814#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ 815#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ 816 817/* Processor Version Numbers */ 818 819#define PVR_403GA 0x00200000 820#define PVR_403GB 0x00200100 821#define PVR_403GC 0x00200200 822#define PVR_403GCX 0x00201400 823#define PVR_405GP 0x40110000 824#define PVR_476 0x11a52000 825#define PVR_STB03XXX 0x40310000 826#define PVR_NP405H 0x41410000 827#define PVR_NP405L 0x41610000 828#define PVR_601 0x00010000 829#define PVR_602 0x00050000 830#define PVR_603 0x00030000 831#define PVR_603e 0x00060000 832#define PVR_603ev 0x00070000 833#define PVR_603r 0x00071000 834#define PVR_604 0x00040000 835#define PVR_604e 0x00090000 836#define PVR_604r 0x000A0000 837#define PVR_620 0x00140000 838#define PVR_740 0x00080000 839#define PVR_750 PVR_740 840#define PVR_740P 0x10080000 841#define PVR_750P PVR_740P 842#define PVR_7400 0x000C0000 843#define PVR_7410 0x800C0000 844#define PVR_7450 0x80000000 845#define PVR_8540 0x80200000 846#define PVR_8560 0x80200000 847/* 848 * For the 8xx processors, all of them report the same PVR family for 849 * the PowerPC core. The various versions of these processors must be 850 * differentiated by the version number in the Communication Processor 851 * Module (CPM). 852 */ 853#define PVR_821 0x00500000 854#define PVR_823 PVR_821 855#define PVR_850 PVR_821 856#define PVR_860 PVR_821 857#define PVR_8240 0x00810100 858#define PVR_8245 0x80811014 859#define PVR_8260 PVR_8240 860 861/* 476 Simulator seems to currently have the PVR of the 602... */ 862#define PVR_476_ISS 0x00052000 863 864/* 64-bit processors */ 865#define PV_NORTHSTAR 0x0033 866#define PV_PULSAR 0x0034 867#define PV_POWER4 0x0035 868#define PV_ICESTAR 0x0036 869#define PV_SSTAR 0x0037 870#define PV_POWER4p 0x0038 871#define PV_970 0x0039 872#define PV_POWER5 0x003A 873#define PV_POWER5p 0x003B 874#define PV_970FX 0x003C 875#define PV_630 0x0040 876#define PV_630p 0x0041 877#define PV_970MP 0x0044 878#define PV_970GX 0x0045 879#define PV_BE 0x0070 880#define PV_PA6T 0x0090 881 882/* Macros for setting and retrieving special purpose registers */ 883#ifndef __ASSEMBLY__ 884#define mfmsr() ({unsigned long rval; \ 885 asm volatile("mfmsr %0" : "=r" (rval)); rval;}) 886#ifdef CONFIG_PPC_BOOK3S_64 887#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \ 888 : : "r" (v) : "memory") 889#define mtmsrd(v) __mtmsrd((v), 0) 890#define mtmsr(v) mtmsrd(v) 891#else 892#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v) : "memory") 893#endif 894 895#define mfspr(rn) ({unsigned long rval; \ 896 asm volatile("mfspr %0," __stringify(rn) \ 897 : "=r" (rval)); rval;}) 898#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)\ 899 : "memory") 900 901#ifdef __powerpc64__ 902#ifdef CONFIG_PPC_CELL 903#define mftb() ({unsigned long rval; \ 904 asm volatile( \ 905 "90: mftb %0;\n" \ 906 "97: cmpwi %0,0;\n" \ 907 " beq- 90b;\n" \ 908 "99:\n" \ 909 ".section __ftr_fixup,\"a\"\n" \ 910 ".align 3\n" \ 911 "98:\n" \ 912 " .llong %1\n" \ 913 " .llong %1\n" \ 914 " .llong 97b-98b\n" \ 915 " .llong 99b-98b\n" \ 916 " .llong 0\n" \ 917 " .llong 0\n" \ 918 ".previous" \ 919 : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;}) 920#else 921#define mftb() ({unsigned long rval; \ 922 asm volatile("mftb %0" : "=r" (rval)); rval;}) 923#endif /* !CONFIG_PPC_CELL */ 924 925#else /* __powerpc64__ */ 926 927#define mftbl() ({unsigned long rval; \ 928 asm volatile("mftbl %0" : "=r" (rval)); rval;}) 929#define mftbu() ({unsigned long rval; \ 930 asm volatile("mftbu %0" : "=r" (rval)); rval;}) 931#endif /* !__powerpc64__ */ 932 933#define mttbl(v) asm volatile("mttbl %0":: "r"(v)) 934#define mttbu(v) asm volatile("mttbu %0":: "r"(v)) 935 936#ifdef CONFIG_PPC32 937#define mfsrin(v) ({unsigned int rval; \ 938 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \ 939 rval;}) 940#endif 941 942#define proc_trap() asm volatile("trap") 943 944#ifdef CONFIG_PPC64 945 946extern void ppc64_runlatch_on(void); 947extern void __ppc64_runlatch_off(void); 948 949#define ppc64_runlatch_off() \ 950 do { \ 951 if (cpu_has_feature(CPU_FTR_CTRL) && \ 952 test_thread_flag(TIF_RUNLATCH)) \ 953 __ppc64_runlatch_off(); \ 954 } while (0) 955 956extern unsigned long scom970_read(unsigned int address); 957extern void scom970_write(unsigned int address, unsigned long value); 958 959#else 960#define ppc64_runlatch_on() 961#define ppc64_runlatch_off() 962 963#endif /* CONFIG_PPC64 */ 964 965#define __get_SP() ({unsigned long sp; \ 966 asm volatile("mr %0,1": "=r" (sp)); sp;}) 967 968struct pt_regs; 969 970extern void ppc_save_regs(struct pt_regs *regs); 971 972#endif /* __ASSEMBLY__ */ 973#endif /* __KERNEL__ */ 974#endif /* _ASM_POWERPC_REG_H */ 975