1/* 2 * SBC8641D Device Tree Source 3 * 4 * Copyright 2008 Wind River Systems Inc. 5 * 6 * Paul Gortmaker (see MAINTAINERS for contact information) 7 * 8 * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16/dts-v1/; 17 18/ { 19 model = "SBC8641D"; 20 compatible = "wind,sbc8641"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 24 aliases { 25 ethernet0 = &enet0; 26 ethernet1 = &enet1; 27 ethernet2 = &enet2; 28 ethernet3 = &enet3; 29 serial0 = &serial0; 30 serial1 = &serial1; 31 pci0 = &pci0; 32 pci1 = &pci1; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 PowerPC,8641@0 { 40 device_type = "cpu"; 41 reg = <0>; 42 d-cache-line-size = <32>; 43 i-cache-line-size = <32>; 44 d-cache-size = <32768>; // L1 45 i-cache-size = <32768>; // L1 46 timebase-frequency = <0>; // From uboot 47 bus-frequency = <0>; // From uboot 48 clock-frequency = <0>; // From uboot 49 }; 50 PowerPC,8641@1 { 51 device_type = "cpu"; 52 reg = <1>; 53 d-cache-line-size = <32>; 54 i-cache-line-size = <32>; 55 d-cache-size = <32768>; 56 i-cache-size = <32768>; 57 timebase-frequency = <0>; // From uboot 58 bus-frequency = <0>; // From uboot 59 clock-frequency = <0>; // From uboot 60 }; 61 }; 62 63 memory { 64 device_type = "memory"; 65 reg = <0x00000000 0x20000000>; // 512M at 0x0 66 }; 67 68 localbus@f8005000 { 69 #address-cells = <2>; 70 #size-cells = <1>; 71 compatible = "fsl,mpc8641-localbus", "simple-bus"; 72 reg = <0xf8005000 0x1000>; 73 interrupts = <19 2>; 74 interrupt-parent = <&mpic>; 75 76 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash 77 1 0 0xf0000000 0x00010000 // 64KB EEPROM 78 2 0 0xf1000000 0x00100000 // EPLD (1MB) 79 3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3) 80 4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4) 81 6 0 0xf4000000 0x00100000 // LCD display (1MB) 82 7 0 0xe8000000 0x04000000>; // 64MB OneNAND 83 84 flash@0,0 { 85 compatible = "cfi-flash"; 86 reg = <0 0 0x01000000>; 87 bank-width = <2>; 88 device-width = <2>; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 partition@0 { 92 label = "dtb"; 93 reg = <0x00000000 0x00100000>; 94 read-only; 95 }; 96 partition@300000 { 97 label = "kernel"; 98 reg = <0x00100000 0x00400000>; 99 read-only; 100 }; 101 partition@400000 { 102 label = "fs"; 103 reg = <0x00500000 0x00a00000>; 104 }; 105 partition@700000 { 106 label = "firmware"; 107 reg = <0x00f00000 0x00100000>; 108 read-only; 109 }; 110 }; 111 112 epld@2,0 { 113 compatible = "wrs,epld-localbus"; 114 #address-cells = <2>; 115 #size-cells = <1>; 116 reg = <2 0 0x100000>; 117 ranges = <0 0 5 0 1 // User switches 118 1 0 5 1 1 // Board ID/Rev 119 3 0 5 3 1>; // LEDs 120 }; 121 }; 122 123 soc@f8000000 { 124 #address-cells = <1>; 125 #size-cells = <1>; 126 device_type = "soc"; 127 compatible = "simple-bus"; 128 ranges = <0x00000000 0xf8000000 0x00100000>; 129 bus-frequency = <0>; 130 131 mcm-law@0 { 132 compatible = "fsl,mcm-law"; 133 reg = <0x0 0x1000>; 134 fsl,num-laws = <10>; 135 }; 136 137 mcm@1000 { 138 compatible = "fsl,mpc8641-mcm", "fsl,mcm"; 139 reg = <0x1000 0x1000>; 140 interrupts = <17 2>; 141 interrupt-parent = <&mpic>; 142 }; 143 144 i2c@3000 { 145 #address-cells = <1>; 146 #size-cells = <0>; 147 cell-index = <0>; 148 compatible = "fsl-i2c"; 149 reg = <0x3000 0x100>; 150 interrupts = <43 2>; 151 interrupt-parent = <&mpic>; 152 dfsrr; 153 }; 154 155 i2c@3100 { 156 #address-cells = <1>; 157 #size-cells = <0>; 158 cell-index = <1>; 159 compatible = "fsl-i2c"; 160 reg = <0x3100 0x100>; 161 interrupts = <43 2>; 162 interrupt-parent = <&mpic>; 163 dfsrr; 164 }; 165 166 dma@21300 { 167 #address-cells = <1>; 168 #size-cells = <1>; 169 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; 170 reg = <0x21300 0x4>; 171 ranges = <0x0 0x21100 0x200>; 172 cell-index = <0>; 173 dma-channel@0 { 174 compatible = "fsl,mpc8641-dma-channel", 175 "fsl,eloplus-dma-channel"; 176 reg = <0x0 0x80>; 177 cell-index = <0>; 178 interrupt-parent = <&mpic>; 179 interrupts = <20 2>; 180 }; 181 dma-channel@80 { 182 compatible = "fsl,mpc8641-dma-channel", 183 "fsl,eloplus-dma-channel"; 184 reg = <0x80 0x80>; 185 cell-index = <1>; 186 interrupt-parent = <&mpic>; 187 interrupts = <21 2>; 188 }; 189 dma-channel@100 { 190 compatible = "fsl,mpc8641-dma-channel", 191 "fsl,eloplus-dma-channel"; 192 reg = <0x100 0x80>; 193 cell-index = <2>; 194 interrupt-parent = <&mpic>; 195 interrupts = <22 2>; 196 }; 197 dma-channel@180 { 198 compatible = "fsl,mpc8641-dma-channel", 199 "fsl,eloplus-dma-channel"; 200 reg = <0x180 0x80>; 201 cell-index = <3>; 202 interrupt-parent = <&mpic>; 203 interrupts = <23 2>; 204 }; 205 }; 206 207 enet0: ethernet@24000 { 208 #address-cells = <1>; 209 #size-cells = <1>; 210 cell-index = <0>; 211 device_type = "network"; 212 model = "TSEC"; 213 compatible = "gianfar"; 214 reg = <0x24000 0x1000>; 215 ranges = <0x0 0x24000 0x1000>; 216 local-mac-address = [ 00 00 00 00 00 00 ]; 217 interrupts = <29 2 30 2 34 2>; 218 interrupt-parent = <&mpic>; 219 tbi-handle = <&tbi0>; 220 phy-handle = <&phy0>; 221 phy-connection-type = "rgmii-id"; 222 223 mdio@520 { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 compatible = "fsl,gianfar-mdio"; 227 reg = <0x520 0x20>; 228 229 phy0: ethernet-phy@1f { 230 interrupt-parent = <&mpic>; 231 interrupts = <10 1>; 232 reg = <0x1f>; 233 device_type = "ethernet-phy"; 234 }; 235 phy1: ethernet-phy@0 { 236 interrupt-parent = <&mpic>; 237 interrupts = <10 1>; 238 reg = <0>; 239 device_type = "ethernet-phy"; 240 }; 241 phy2: ethernet-phy@1 { 242 interrupt-parent = <&mpic>; 243 interrupts = <10 1>; 244 reg = <1>; 245 device_type = "ethernet-phy"; 246 }; 247 phy3: ethernet-phy@2 { 248 interrupt-parent = <&mpic>; 249 interrupts = <10 1>; 250 reg = <2>; 251 device_type = "ethernet-phy"; 252 }; 253 tbi0: tbi-phy@11 { 254 reg = <0x11>; 255 device_type = "tbi-phy"; 256 }; 257 }; 258 }; 259 260 enet1: ethernet@25000 { 261 #address-cells = <1>; 262 #size-cells = <1>; 263 cell-index = <1>; 264 device_type = "network"; 265 model = "TSEC"; 266 compatible = "gianfar"; 267 reg = <0x25000 0x1000>; 268 ranges = <0x0 0x25000 0x1000>; 269 local-mac-address = [ 00 00 00 00 00 00 ]; 270 interrupts = <35 2 36 2 40 2>; 271 interrupt-parent = <&mpic>; 272 tbi-handle = <&tbi1>; 273 phy-handle = <&phy1>; 274 phy-connection-type = "rgmii-id"; 275 276 mdio@520 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 compatible = "fsl,gianfar-tbi"; 280 reg = <0x520 0x20>; 281 282 tbi1: tbi-phy@11 { 283 reg = <0x11>; 284 device_type = "tbi-phy"; 285 }; 286 }; 287 }; 288 289 enet2: ethernet@26000 { 290 #address-cells = <1>; 291 #size-cells = <1>; 292 cell-index = <2>; 293 device_type = "network"; 294 model = "TSEC"; 295 compatible = "gianfar"; 296 reg = <0x26000 0x1000>; 297 ranges = <0x0 0x26000 0x1000>; 298 local-mac-address = [ 00 00 00 00 00 00 ]; 299 interrupts = <31 2 32 2 33 2>; 300 interrupt-parent = <&mpic>; 301 tbi-handle = <&tbi2>; 302 phy-handle = <&phy2>; 303 phy-connection-type = "rgmii-id"; 304 305 mdio@520 { 306 #address-cells = <1>; 307 #size-cells = <0>; 308 compatible = "fsl,gianfar-tbi"; 309 reg = <0x520 0x20>; 310 311 tbi2: tbi-phy@11 { 312 reg = <0x11>; 313 device_type = "tbi-phy"; 314 }; 315 }; 316 }; 317 318 enet3: ethernet@27000 { 319 #address-cells = <1>; 320 #size-cells = <1>; 321 cell-index = <3>; 322 device_type = "network"; 323 model = "TSEC"; 324 compatible = "gianfar"; 325 reg = <0x27000 0x1000>; 326 ranges = <0x0 0x27000 0x1000>; 327 local-mac-address = [ 00 00 00 00 00 00 ]; 328 interrupts = <37 2 38 2 39 2>; 329 interrupt-parent = <&mpic>; 330 tbi-handle = <&tbi3>; 331 phy-handle = <&phy3>; 332 phy-connection-type = "rgmii-id"; 333 334 mdio@520 { 335 #address-cells = <1>; 336 #size-cells = <0>; 337 compatible = "fsl,gianfar-tbi"; 338 reg = <0x520 0x20>; 339 340 tbi3: tbi-phy@11 { 341 reg = <0x11>; 342 device_type = "tbi-phy"; 343 }; 344 }; 345 }; 346 347 serial0: serial@4500 { 348 cell-index = <0>; 349 device_type = "serial"; 350 compatible = "ns16550"; 351 reg = <0x4500 0x100>; 352 clock-frequency = <0>; 353 interrupts = <42 2>; 354 interrupt-parent = <&mpic>; 355 }; 356 357 serial1: serial@4600 { 358 cell-index = <1>; 359 device_type = "serial"; 360 compatible = "ns16550"; 361 reg = <0x4600 0x100>; 362 clock-frequency = <0>; 363 interrupts = <28 2>; 364 interrupt-parent = <&mpic>; 365 }; 366 367 mpic: pic@40000 { 368 clock-frequency = <0>; 369 interrupt-controller; 370 #address-cells = <0>; 371 #interrupt-cells = <2>; 372 reg = <0x40000 0x40000>; 373 compatible = "chrp,open-pic"; 374 device_type = "open-pic"; 375 big-endian; 376 }; 377 378 global-utilities@e0000 { 379 compatible = "fsl,mpc8641-guts"; 380 reg = <0xe0000 0x1000>; 381 fsl,has-rstcr; 382 }; 383 }; 384 385 pci0: pcie@f8008000 { 386 compatible = "fsl,mpc8641-pcie"; 387 device_type = "pci"; 388 #interrupt-cells = <1>; 389 #size-cells = <2>; 390 #address-cells = <3>; 391 reg = <0xf8008000 0x1000>; 392 bus-range = <0x0 0xff>; 393 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 394 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 395 clock-frequency = <33333333>; 396 interrupt-parent = <&mpic>; 397 interrupts = <24 2>; 398 interrupt-map-mask = <0xff00 0 0 7>; 399 interrupt-map = < 400 /* IDSEL 0x0 */ 401 0x0000 0 0 1 &mpic 0 1 402 0x0000 0 0 2 &mpic 1 1 403 0x0000 0 0 3 &mpic 2 1 404 0x0000 0 0 4 &mpic 3 1 405 >; 406 407 pcie@0 { 408 reg = <0 0 0 0 0>; 409 #size-cells = <2>; 410 #address-cells = <3>; 411 device_type = "pci"; 412 ranges = <0x02000000 0x0 0x80000000 413 0x02000000 0x0 0x80000000 414 0x0 0x20000000 415 416 0x01000000 0x0 0x00000000 417 0x01000000 0x0 0x00000000 418 0x0 0x00100000>; 419 }; 420 421 }; 422 423 pci1: pcie@f8009000 { 424 compatible = "fsl,mpc8641-pcie"; 425 device_type = "pci"; 426 #interrupt-cells = <1>; 427 #size-cells = <2>; 428 #address-cells = <3>; 429 reg = <0xf8009000 0x1000>; 430 bus-range = <0 0xff>; 431 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 432 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>; 433 clock-frequency = <33333333>; 434 interrupt-parent = <&mpic>; 435 interrupts = <25 2>; 436 interrupt-map-mask = <0xf800 0 0 7>; 437 interrupt-map = < 438 /* IDSEL 0x0 */ 439 0x0000 0 0 1 &mpic 4 1 440 0x0000 0 0 2 &mpic 5 1 441 0x0000 0 0 3 &mpic 6 1 442 0x0000 0 0 4 &mpic 7 1 443 >; 444 445 pcie@0 { 446 reg = <0 0 0 0 0>; 447 #size-cells = <2>; 448 #address-cells = <3>; 449 device_type = "pci"; 450 ranges = <0x02000000 0x0 0xa0000000 451 0x02000000 0x0 0xa0000000 452 0x0 0x20000000 453 454 0x01000000 0x0 0x00000000 455 0x01000000 0x0 0x00000000 456 0x0 0x00100000>; 457 }; 458 }; 459}; 460