1/* 2 * MPC8541 CDS Device Tree Source 3 * 4 * Copyright 2006, 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "MPC8541CDS"; 16 compatible = "MPC8541CDS", "MPC85xxCDS"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 pci0 = &pci0; 26 pci1 = &pci1; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 PowerPC,8541@0 { 34 device_type = "cpu"; 35 reg = <0x0>; 36 d-cache-line-size = <32>; // 32 bytes 37 i-cache-line-size = <32>; // 32 bytes 38 d-cache-size = <0x8000>; // L1, 32K 39 i-cache-size = <0x8000>; // L1, 32K 40 timebase-frequency = <0>; // 33 MHz, from uboot 41 bus-frequency = <0>; // 166 MHz 42 clock-frequency = <0>; // 825 MHz, from uboot 43 next-level-cache = <&L2>; 44 }; 45 }; 46 47 memory { 48 device_type = "memory"; 49 reg = <0x0 0x8000000>; // 128M at 0x0 50 }; 51 52 soc8541@e0000000 { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 device_type = "soc"; 56 compatible = "simple-bus"; 57 ranges = <0x0 0xe0000000 0x100000>; 58 bus-frequency = <0>; 59 60 ecm-law@0 { 61 compatible = "fsl,ecm-law"; 62 reg = <0x0 0x1000>; 63 fsl,num-laws = <8>; 64 }; 65 66 ecm@1000 { 67 compatible = "fsl,mpc8541-ecm", "fsl,ecm"; 68 reg = <0x1000 0x1000>; 69 interrupts = <17 2>; 70 interrupt-parent = <&mpic>; 71 }; 72 73 memory-controller@2000 { 74 compatible = "fsl,mpc8541-memory-controller"; 75 reg = <0x2000 0x1000>; 76 interrupt-parent = <&mpic>; 77 interrupts = <18 2>; 78 }; 79 80 L2: l2-cache-controller@20000 { 81 compatible = "fsl,mpc8541-l2-cache-controller"; 82 reg = <0x20000 0x1000>; 83 cache-line-size = <32>; // 32 bytes 84 cache-size = <0x40000>; // L2, 256K 85 interrupt-parent = <&mpic>; 86 interrupts = <16 2>; 87 }; 88 89 i2c@3000 { 90 #address-cells = <1>; 91 #size-cells = <0>; 92 cell-index = <0>; 93 compatible = "fsl-i2c"; 94 reg = <0x3000 0x100>; 95 interrupts = <43 2>; 96 interrupt-parent = <&mpic>; 97 dfsrr; 98 }; 99 100 dma@21300 { 101 #address-cells = <1>; 102 #size-cells = <1>; 103 compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; 104 reg = <0x21300 0x4>; 105 ranges = <0x0 0x21100 0x200>; 106 cell-index = <0>; 107 dma-channel@0 { 108 compatible = "fsl,mpc8541-dma-channel", 109 "fsl,eloplus-dma-channel"; 110 reg = <0x0 0x80>; 111 cell-index = <0>; 112 interrupt-parent = <&mpic>; 113 interrupts = <20 2>; 114 }; 115 dma-channel@80 { 116 compatible = "fsl,mpc8541-dma-channel", 117 "fsl,eloplus-dma-channel"; 118 reg = <0x80 0x80>; 119 cell-index = <1>; 120 interrupt-parent = <&mpic>; 121 interrupts = <21 2>; 122 }; 123 dma-channel@100 { 124 compatible = "fsl,mpc8541-dma-channel", 125 "fsl,eloplus-dma-channel"; 126 reg = <0x100 0x80>; 127 cell-index = <2>; 128 interrupt-parent = <&mpic>; 129 interrupts = <22 2>; 130 }; 131 dma-channel@180 { 132 compatible = "fsl,mpc8541-dma-channel", 133 "fsl,eloplus-dma-channel"; 134 reg = <0x180 0x80>; 135 cell-index = <3>; 136 interrupt-parent = <&mpic>; 137 interrupts = <23 2>; 138 }; 139 }; 140 141 enet0: ethernet@24000 { 142 #address-cells = <1>; 143 #size-cells = <1>; 144 cell-index = <0>; 145 device_type = "network"; 146 model = "TSEC"; 147 compatible = "gianfar"; 148 reg = <0x24000 0x1000>; 149 ranges = <0x0 0x24000 0x1000>; 150 local-mac-address = [ 00 00 00 00 00 00 ]; 151 interrupts = <29 2 30 2 34 2>; 152 interrupt-parent = <&mpic>; 153 tbi-handle = <&tbi0>; 154 phy-handle = <&phy0>; 155 156 mdio@520 { 157 #address-cells = <1>; 158 #size-cells = <0>; 159 compatible = "fsl,gianfar-mdio"; 160 reg = <0x520 0x20>; 161 162 phy0: ethernet-phy@0 { 163 interrupt-parent = <&mpic>; 164 interrupts = <5 1>; 165 reg = <0x0>; 166 device_type = "ethernet-phy"; 167 }; 168 phy1: ethernet-phy@1 { 169 interrupt-parent = <&mpic>; 170 interrupts = <5 1>; 171 reg = <0x1>; 172 device_type = "ethernet-phy"; 173 }; 174 tbi0: tbi-phy@11 { 175 reg = <0x11>; 176 device_type = "tbi-phy"; 177 }; 178 }; 179 }; 180 181 enet1: ethernet@25000 { 182 #address-cells = <1>; 183 #size-cells = <1>; 184 cell-index = <1>; 185 device_type = "network"; 186 model = "TSEC"; 187 compatible = "gianfar"; 188 reg = <0x25000 0x1000>; 189 ranges = <0x0 0x25000 0x1000>; 190 local-mac-address = [ 00 00 00 00 00 00 ]; 191 interrupts = <35 2 36 2 40 2>; 192 interrupt-parent = <&mpic>; 193 tbi-handle = <&tbi1>; 194 phy-handle = <&phy1>; 195 196 mdio@520 { 197 #address-cells = <1>; 198 #size-cells = <0>; 199 compatible = "fsl,gianfar-tbi"; 200 reg = <0x520 0x20>; 201 202 tbi1: tbi-phy@11 { 203 reg = <0x11>; 204 device_type = "tbi-phy"; 205 }; 206 }; 207 }; 208 209 serial0: serial@4500 { 210 cell-index = <0>; 211 device_type = "serial"; 212 compatible = "ns16550"; 213 reg = <0x4500 0x100>; // reg base, size 214 clock-frequency = <0>; // should we fill in in uboot? 215 interrupts = <42 2>; 216 interrupt-parent = <&mpic>; 217 }; 218 219 serial1: serial@4600 { 220 cell-index = <1>; 221 device_type = "serial"; 222 compatible = "ns16550"; 223 reg = <0x4600 0x100>; // reg base, size 224 clock-frequency = <0>; // should we fill in in uboot? 225 interrupts = <42 2>; 226 interrupt-parent = <&mpic>; 227 }; 228 229 crypto@30000 { 230 compatible = "fsl,sec2.0"; 231 reg = <0x30000 0x10000>; 232 interrupts = <45 2>; 233 interrupt-parent = <&mpic>; 234 fsl,num-channels = <4>; 235 fsl,channel-fifo-len = <24>; 236 fsl,exec-units-mask = <0x7e>; 237 fsl,descriptor-types-mask = <0x01010ebf>; 238 }; 239 240 mpic: pic@40000 { 241 interrupt-controller; 242 #address-cells = <0>; 243 #interrupt-cells = <2>; 244 reg = <0x40000 0x40000>; 245 compatible = "chrp,open-pic"; 246 device_type = "open-pic"; 247 }; 248 249 cpm@919c0 { 250 #address-cells = <1>; 251 #size-cells = <1>; 252 compatible = "fsl,mpc8541-cpm", "fsl,cpm2"; 253 reg = <0x919c0 0x30>; 254 ranges; 255 256 muram@80000 { 257 #address-cells = <1>; 258 #size-cells = <1>; 259 ranges = <0x0 0x80000 0x10000>; 260 261 data@0 { 262 compatible = "fsl,cpm-muram-data"; 263 reg = <0x0 0x2000 0x9000 0x1000>; 264 }; 265 }; 266 267 brg@919f0 { 268 compatible = "fsl,mpc8541-brg", 269 "fsl,cpm2-brg", 270 "fsl,cpm-brg"; 271 reg = <0x919f0 0x10 0x915f0 0x10>; 272 }; 273 274 cpmpic: pic@90c00 { 275 interrupt-controller; 276 #address-cells = <0>; 277 #interrupt-cells = <2>; 278 interrupts = <46 2>; 279 interrupt-parent = <&mpic>; 280 reg = <0x90c00 0x80>; 281 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; 282 }; 283 }; 284 }; 285 286 pci0: pci@e0008000 { 287 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; 288 interrupt-map = < 289 290 /* IDSEL 0x10 */ 291 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1 292 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1 293 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1 294 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1 295 296 /* IDSEL 0x11 */ 297 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1 298 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1 299 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1 300 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1 301 302 /* IDSEL 0x12 (Slot 1) */ 303 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1 304 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1 305 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 306 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1 307 308 /* IDSEL 0x13 (Slot 2) */ 309 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1 310 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1 311 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1 312 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1 313 314 /* IDSEL 0x14 (Slot 3) */ 315 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1 316 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1 317 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1 318 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1 319 320 /* IDSEL 0x15 (Slot 4) */ 321 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1 322 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1 323 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1 324 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1 325 326 /* Bus 1 (Tundra Bridge) */ 327 /* IDSEL 0x12 (ISA bridge) */ 328 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1 329 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1 330 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1 331 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>; 332 interrupt-parent = <&mpic>; 333 interrupts = <24 2>; 334 bus-range = <0 0>; 335 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 336 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; 337 clock-frequency = <66666666>; 338 #interrupt-cells = <1>; 339 #size-cells = <2>; 340 #address-cells = <3>; 341 reg = <0xe0008000 0x1000>; 342 compatible = "fsl,mpc8540-pci"; 343 device_type = "pci"; 344 345 i8259@19000 { 346 interrupt-controller; 347 device_type = "interrupt-controller"; 348 reg = <0x19000 0x0 0x0 0x0 0x1>; 349 #address-cells = <0>; 350 #interrupt-cells = <2>; 351 compatible = "chrp,iic"; 352 interrupts = <1>; 353 interrupt-parent = <&pci0>; 354 }; 355 }; 356 357 pci1: pci@e0009000 { 358 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 359 interrupt-map = < 360 361 /* IDSEL 0x15 */ 362 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 363 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1 364 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1 365 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>; 366 interrupt-parent = <&mpic>; 367 interrupts = <25 2>; 368 bus-range = <0 0>; 369 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 370 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>; 371 clock-frequency = <66666666>; 372 #interrupt-cells = <1>; 373 #size-cells = <2>; 374 #address-cells = <3>; 375 reg = <0xe0009000 0x1000>; 376 compatible = "fsl,mpc8540-pci"; 377 device_type = "pci"; 378 }; 379}; 380