1/* 2 * GE SBC310 Device Tree Source 3 * 4 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * Based on: SBS CM6 Device Tree Source 12 * Copyright 2007 SBS Technologies GmbH & Co. KG 13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source) 14 * Copyright 2006 Freescale Semiconductor Inc. 15 */ 16 17/* 18 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts 19 */ 20 21/dts-v1/; 22 23/ { 24 model = "GEF_SBC310"; 25 compatible = "gef,sbc310"; 26 #address-cells = <1>; 27 #size-cells = <1>; 28 29 aliases { 30 ethernet0 = &enet0; 31 ethernet1 = &enet1; 32 serial0 = &serial0; 33 serial1 = &serial1; 34 pci0 = &pci0; 35 pci1 = &pci1; 36 }; 37 38 cpus { 39 #address-cells = <1>; 40 #size-cells = <0>; 41 42 PowerPC,8641@0 { 43 device_type = "cpu"; 44 reg = <0>; 45 d-cache-line-size = <32>; // 32 bytes 46 i-cache-line-size = <32>; // 32 bytes 47 d-cache-size = <32768>; // L1, 32K 48 i-cache-size = <32768>; // L1, 32K 49 timebase-frequency = <0>; // From uboot 50 bus-frequency = <0>; // From uboot 51 clock-frequency = <0>; // From uboot 52 }; 53 PowerPC,8641@1 { 54 device_type = "cpu"; 55 reg = <1>; 56 d-cache-line-size = <32>; // 32 bytes 57 i-cache-line-size = <32>; // 32 bytes 58 d-cache-size = <32768>; // L1, 32K 59 i-cache-size = <32768>; // L1, 32K 60 timebase-frequency = <0>; // From uboot 61 bus-frequency = <0>; // From uboot 62 clock-frequency = <0>; // From uboot 63 }; 64 }; 65 66 memory { 67 device_type = "memory"; 68 reg = <0x0 0x40000000>; // set by uboot 69 }; 70 71 localbus@fef05000 { 72 #address-cells = <2>; 73 #size-cells = <1>; 74 compatible = "fsl,mpc8641-localbus", "simple-bus"; 75 reg = <0xfef05000 0x1000>; 76 interrupts = <19 2>; 77 interrupt-parent = <&mpic>; 78 79 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash 80 1 0 0xe0000000 0x08000000 // Paged Flash 0 81 2 0 0xe8000000 0x08000000 // Paged Flash 1 82 3 0 0xfc100000 0x00020000 // NVRAM 83 4 0 0xfc000000 0x00010000>; // FPGA 84 85 /* flash@0,0 is a mirror of part of the memory in flash@1,0 86 flash@0,0 { 87 compatible = "gef,sbc310-firmware-mirror", "cfi-flash"; 88 reg = <0x0 0x0 0x01000000>; 89 bank-width = <2>; 90 device-width = <2>; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 partition@0 { 94 label = "firmware"; 95 reg = <0x0 0x01000000>; 96 read-only; 97 }; 98 }; 99 */ 100 101 flash@1,0 { 102 compatible = "gef,sbc310-paged-flash", "cfi-flash"; 103 reg = <0x1 0x0 0x8000000>; 104 bank-width = <2>; 105 device-width = <2>; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 partition@0 { 109 label = "user"; 110 reg = <0x0 0x7800000>; 111 }; 112 partition@7800000 { 113 label = "firmware"; 114 reg = <0x7800000 0x800000>; 115 read-only; 116 }; 117 }; 118 119 nvram@3,0 { 120 device_type = "nvram"; 121 compatible = "simtek,stk14ca8"; 122 reg = <0x3 0x0 0x20000>; 123 }; 124 125 fpga@4,0 { 126 compatible = "gef,fpga-regs"; 127 reg = <0x4 0x0 0x40>; 128 }; 129 130 wdt@4,2000 { 131 compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00", 132 "gef,fpga-wdt"; 133 reg = <0x4 0x2000 0x8>; 134 interrupts = <0x1a 0x4>; 135 interrupt-parent = <&gef_pic>; 136 }; 137/* 138 wdt@4,2010 { 139 compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00", 140 "gef,fpga-wdt"; 141 reg = <0x4 0x2010 0x8>; 142 interrupts = <0x1b 0x4>; 143 interrupt-parent = <&gef_pic>; 144 }; 145*/ 146 gef_pic: pic@4,4000 { 147 #interrupt-cells = <1>; 148 interrupt-controller; 149 compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic"; 150 reg = <0x4 0x4000 0x20>; 151 interrupts = <0x8 152 0x9>; 153 interrupt-parent = <&mpic>; 154 155 }; 156 gef_gpio: gpio@4,8000 { 157 #gpio-cells = <2>; 158 compatible = "gef,sbc310-gpio"; 159 reg = <0x4 0x8000 0x24>; 160 gpio-controller; 161 }; 162 }; 163 164 soc@fef00000 { 165 #address-cells = <1>; 166 #size-cells = <1>; 167 #interrupt-cells = <2>; 168 device_type = "soc"; 169 compatible = "fsl,mpc8641-soc", "simple-bus"; 170 ranges = <0x0 0xfef00000 0x00100000>; 171 bus-frequency = <33333333>; 172 173 mcm-law@0 { 174 compatible = "fsl,mcm-law"; 175 reg = <0x0 0x1000>; 176 fsl,num-laws = <10>; 177 }; 178 179 mcm@1000 { 180 compatible = "fsl,mpc8641-mcm", "fsl,mcm"; 181 reg = <0x1000 0x1000>; 182 interrupts = <17 2>; 183 interrupt-parent = <&mpic>; 184 }; 185 186 i2c1: i2c@3000 { 187 #address-cells = <1>; 188 #size-cells = <0>; 189 compatible = "fsl-i2c"; 190 reg = <0x3000 0x100>; 191 interrupts = <0x2b 0x2>; 192 interrupt-parent = <&mpic>; 193 dfsrr; 194 195 rtc@51 { 196 compatible = "epson,rx8581"; 197 reg = <0x00000051>; 198 }; 199 }; 200 201 i2c2: i2c@3100 { 202 #address-cells = <1>; 203 #size-cells = <0>; 204 compatible = "fsl-i2c"; 205 reg = <0x3100 0x100>; 206 interrupts = <0x2b 0x2>; 207 interrupt-parent = <&mpic>; 208 dfsrr; 209 210 hwmon@48 { 211 compatible = "national,lm92"; 212 reg = <0x48>; 213 }; 214 215 hwmon@4c { 216 compatible = "adi,adt7461"; 217 reg = <0x4c>; 218 }; 219 220 eti@6b { 221 compatible = "dallas,ds1682"; 222 reg = <0x6b>; 223 }; 224 }; 225 226 dma@21300 { 227 #address-cells = <1>; 228 #size-cells = <1>; 229 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; 230 reg = <0x21300 0x4>; 231 ranges = <0x0 0x21100 0x200>; 232 cell-index = <0>; 233 dma-channel@0 { 234 compatible = "fsl,mpc8641-dma-channel", 235 "fsl,eloplus-dma-channel"; 236 reg = <0x0 0x80>; 237 cell-index = <0>; 238 interrupt-parent = <&mpic>; 239 interrupts = <20 2>; 240 }; 241 dma-channel@80 { 242 compatible = "fsl,mpc8641-dma-channel", 243 "fsl,eloplus-dma-channel"; 244 reg = <0x80 0x80>; 245 cell-index = <1>; 246 interrupt-parent = <&mpic>; 247 interrupts = <21 2>; 248 }; 249 dma-channel@100 { 250 compatible = "fsl,mpc8641-dma-channel", 251 "fsl,eloplus-dma-channel"; 252 reg = <0x100 0x80>; 253 cell-index = <2>; 254 interrupt-parent = <&mpic>; 255 interrupts = <22 2>; 256 }; 257 dma-channel@180 { 258 compatible = "fsl,mpc8641-dma-channel", 259 "fsl,eloplus-dma-channel"; 260 reg = <0x180 0x80>; 261 cell-index = <3>; 262 interrupt-parent = <&mpic>; 263 interrupts = <23 2>; 264 }; 265 }; 266 267 enet0: ethernet@24000 { 268 #address-cells = <1>; 269 #size-cells = <1>; 270 device_type = "network"; 271 model = "eTSEC"; 272 compatible = "gianfar"; 273 reg = <0x24000 0x1000>; 274 ranges = <0x0 0x24000 0x1000>; 275 local-mac-address = [ 00 00 00 00 00 00 ]; 276 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>; 277 interrupt-parent = <&mpic>; 278 phy-handle = <&phy0>; 279 phy-connection-type = "gmii"; 280 281 mdio@520 { 282 #address-cells = <1>; 283 #size-cells = <0>; 284 compatible = "fsl,gianfar-mdio"; 285 reg = <0x520 0x20>; 286 287 phy0: ethernet-phy@0 { 288 interrupt-parent = <&gef_pic>; 289 interrupts = <0x9 0x4>; 290 reg = <1>; 291 }; 292 phy2: ethernet-phy@2 { 293 interrupt-parent = <&gef_pic>; 294 interrupts = <0x8 0x4>; 295 reg = <3>; 296 }; 297 }; 298 }; 299 300 enet1: ethernet@26000 { 301 device_type = "network"; 302 model = "eTSEC"; 303 compatible = "gianfar"; 304 reg = <0x26000 0x1000>; 305 local-mac-address = [ 00 00 00 00 00 00 ]; 306 interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>; 307 interrupt-parent = <&mpic>; 308 phy-handle = <&phy2>; 309 phy-connection-type = "gmii"; 310 }; 311 312 serial0: serial@4500 { 313 cell-index = <0>; 314 device_type = "serial"; 315 compatible = "ns16550"; 316 reg = <0x4500 0x100>; 317 clock-frequency = <0>; 318 interrupts = <0x2a 0x2>; 319 interrupt-parent = <&mpic>; 320 }; 321 322 serial1: serial@4600 { 323 cell-index = <1>; 324 device_type = "serial"; 325 compatible = "ns16550"; 326 reg = <0x4600 0x100>; 327 clock-frequency = <0>; 328 interrupts = <0x1c 0x2>; 329 interrupt-parent = <&mpic>; 330 }; 331 332 mpic: pic@40000 { 333 clock-frequency = <0>; 334 interrupt-controller; 335 #address-cells = <0>; 336 #interrupt-cells = <2>; 337 reg = <0x40000 0x40000>; 338 compatible = "chrp,open-pic"; 339 device_type = "open-pic"; 340 }; 341 342 msi@41600 { 343 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; 344 reg = <0x41600 0x80>; 345 msi-available-ranges = <0 0x100>; 346 interrupts = < 347 0xe0 0 348 0xe1 0 349 0xe2 0 350 0xe3 0 351 0xe4 0 352 0xe5 0 353 0xe6 0 354 0xe7 0>; 355 interrupt-parent = <&mpic>; 356 }; 357 358 global-utilities@e0000 { 359 compatible = "fsl,mpc8641-guts"; 360 reg = <0xe0000 0x1000>; 361 fsl,has-rstcr; 362 }; 363 }; 364 365 pci0: pcie@fef08000 { 366 compatible = "fsl,mpc8641-pcie"; 367 device_type = "pci"; 368 #interrupt-cells = <1>; 369 #size-cells = <2>; 370 #address-cells = <3>; 371 reg = <0xfef08000 0x1000>; 372 bus-range = <0x0 0xff>; 373 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000 374 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>; 375 clock-frequency = <33333333>; 376 interrupt-parent = <&mpic>; 377 interrupts = <0x18 0x2>; 378 interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 379 interrupt-map = < 380 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2 381 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2 382 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2 383 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2 384 >; 385 386 pcie@0 { 387 reg = <0 0 0 0 0>; 388 #size-cells = <2>; 389 #address-cells = <3>; 390 device_type = "pci"; 391 ranges = <0x02000000 0x0 0x80000000 392 0x02000000 0x0 0x80000000 393 0x0 0x40000000 394 395 0x01000000 0x0 0x00000000 396 0x01000000 0x0 0x00000000 397 0x0 0x00400000>; 398 }; 399 }; 400 401 pci1: pcie@fef09000 { 402 compatible = "fsl,mpc8641-pcie"; 403 device_type = "pci"; 404 #interrupt-cells = <1>; 405 #size-cells = <2>; 406 #address-cells = <3>; 407 reg = <0xfef09000 0x1000>; 408 bus-range = <0x0 0xff>; 409 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000 410 0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>; 411 clock-frequency = <33333333>; 412 interrupt-parent = <&mpic>; 413 interrupts = <0x19 0x2>; 414 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 415 interrupt-map = < 416 0x0000 0x0 0x0 0x1 &mpic 0x4 0x2 417 0x0000 0x0 0x0 0x2 &mpic 0x5 0x2 418 0x0000 0x0 0x0 0x3 &mpic 0x6 0x2 419 0x0000 0x0 0x0 0x4 &mpic 0x7 0x2 420 >; 421 422 pcie@0 { 423 reg = <0 0 0 0 0>; 424 #size-cells = <2>; 425 #address-cells = <3>; 426 device_type = "pci"; 427 ranges = <0x02000000 0x0 0xc0000000 428 0x02000000 0x0 0xc0000000 429 0x0 0x20000000 430 431 0x01000000 0x0 0x00000000 432 0x01000000 0x0 0x00000000 433 0x0 0x00400000>; 434 }; 435 }; 436}; 437