1#ifndef _PARISC_TLBFLUSH_H 2#define _PARISC_TLBFLUSH_H 3 4/* TLB flushing routines.... */ 5 6#include <linux/mm.h> 7#include <linux/sched.h> 8#include <asm/mmu_context.h> 9 10 11/* This is for the serialisation of PxTLB broadcasts. At least on the 12 * N class systems, only one PxTLB inter processor broadcast can be 13 * active at any one time on the Merced bus. This tlb purge 14 * synchronisation is fairly lightweight and harmless so we activate 15 * it on all systems not just the N class. 16 */ 17extern spinlock_t pa_tlb_lock; 18 19#define purge_tlb_start(flags) spin_lock_irqsave(&pa_tlb_lock, flags) 20#define purge_tlb_end(flags) spin_unlock_irqrestore(&pa_tlb_lock, flags) 21 22extern void flush_tlb_all(void); 23extern void flush_tlb_all_local(void *); 24 25 26static inline void flush_tlb_mm(struct mm_struct *mm) 27{ 28 BUG_ON(mm == &init_mm); /* Should never happen */ 29 30 flush_tlb_all(); 31} 32 33static inline void flush_tlb_page(struct vm_area_struct *vma, 34 unsigned long addr) 35{ 36 unsigned long flags; 37 38 /* For one page, it's not worth testing the split_tlb variable */ 39 40 mb(); 41 mtsp(vma->vm_mm->context,1); 42 purge_tlb_start(flags); 43 pdtlb(addr); 44 pitlb(addr); 45 purge_tlb_end(flags); 46} 47 48void __flush_tlb_range(unsigned long sid, 49 unsigned long start, unsigned long end); 50 51#define flush_tlb_range(vma,start,end) __flush_tlb_range((vma)->vm_mm->context,start,end) 52 53#define flush_tlb_kernel_range(start, end) __flush_tlb_range(0,start,end) 54 55#endif 56